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https://gitlab.com/freepascal.org/fpc/source.git
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474 lines
16 KiB
ObjectPascal
474 lines
16 KiB
ObjectPascal
{
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Copyright (c) 2003 by Florian Klaempfl
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This unit implements an asm for the ARM
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{ This unit implements the GNU Assembler writer for the ARM
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}
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unit agarmgas;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,systems,
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aasmtai,
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assemble,aggas,
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cpubase,cpuinfo;
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type
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TARMGNUAssembler=class(TGNUassembler)
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constructor CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean); override;
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function MakeCmdLine: TCmdStr; override;
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procedure WriteExtraHeader; override;
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end;
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TArmInstrWriter=class(TCPUInstrWriter)
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unified_syntax: boolean;
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procedure WriteInstruction(hp : tai);override;
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end;
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TArmAppleGNUAssembler=class(TAppleGNUassembler)
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constructor CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean); override;
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function MakeCmdLine: TCmdStr; override;
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procedure WriteExtraHeader; override;
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end;
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const
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gas_shiftmode2str : array[tshiftmode] of string[3] = (
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'','lsl','lsr','asr','ror','rrx');
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const
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cputype_to_gas_march : array[tcputype] of string = (
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'', // cpu_none
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'armv3',
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'armv4',
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'armv4t',
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'armv5',
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'armv5t',
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'armv5te',
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'armv5tej',
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'armv6',
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'armv6k',
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'armv6t2',
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'armv6z',
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'armv6-m',
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'armv7',
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'armv7-a',
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'armv7-r',
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'armv7-m',
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'armv7e-m');
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implementation
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uses
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cutils,globals,verbose,
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aasmcpu,
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itcpugas,
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cgbase,cgutils;
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{****************************************************************************}
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{ GNU Arm Assembler writer }
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{****************************************************************************}
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constructor TArmGNUAssembler.CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean);
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begin
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inherited;
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InstrWriter := TArmInstrWriter.create(self);
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if GenerateThumb2Code then
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TArmInstrWriter(InstrWriter).unified_syntax:=true;
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end;
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function TArmGNUAssembler.MakeCmdLine: TCmdStr;
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begin
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result:=inherited MakeCmdLine;
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if (current_settings.fputype = fpu_soft) then
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result:='-mfpu=softvfp '+result;
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if (current_settings.fputype = fpu_fpa) then
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result:='-mfpu=fpa '+result;
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if (current_settings.fputype = fpu_fpa10) then
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result:='-mfpu=fpa10 '+result;
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if (current_settings.fputype = fpu_fpa11) then
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result:='-mfpu=fpa11 '+result;
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if (current_settings.fputype = fpu_vfpv2) then
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result:='-mfpu=vfpv2 '+result;
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if (current_settings.fputype = fpu_vfpv3) then
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result:='-mfpu=vfpv3 '+result;
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if (current_settings.fputype = fpu_vfpv3_d16) then
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result:='-mfpu=vfpv3-d16 '+result;
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if (current_settings.fputype = fpu_fpv4_s16) then
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result:='-mfpu=fpv4-sp-d16 '+result;
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if (current_settings.fputype = fpu_vfpv4) then
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result:='-mfpu=vfpv4 '+result;
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if GenerateThumb2Code then
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result:='-march='+cputype_to_gas_march[current_settings.cputype]+' -mthumb -mthumb-interwork '+result
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else if GenerateThumbCode then
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result:='-march='+cputype_to_gas_march[current_settings.cputype]+' -mthumb -mthumb-interwork '+result
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else
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result:='-march='+cputype_to_gas_march[current_settings.cputype]+' '+result;
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if target_info.abi = abi_eabihf then
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{ options based on what gcc uses on debian armhf }
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result:='-mfloat-abi=hard -meabi=5 '+result
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else if (target_info.abi = abi_eabi) and not(current_settings.fputype = fpu_soft) then
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result:='-mfloat-abi=softfp -meabi=5 '+result
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else if (target_info.abi = abi_eabi) and (current_settings.fputype = fpu_soft) then
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result:='-mfloat-abi=soft -meabi=5 '+result;
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end;
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procedure TArmGNUAssembler.WriteExtraHeader;
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begin
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inherited WriteExtraHeader;
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if TArmInstrWriter(InstrWriter).unified_syntax then
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writer.AsmWriteLn(#9'.syntax unified');
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end;
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{****************************************************************************}
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{ GNU/Apple ARM Assembler writer }
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{****************************************************************************}
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constructor TArmAppleGNUAssembler.CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean);
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begin
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inherited;
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InstrWriter := TArmInstrWriter.create(self);
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TArmInstrWriter(InstrWriter).unified_syntax:=true;
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end;
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function TArmAppleGNUAssembler.MakeCmdLine: TCmdStr;
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begin
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result:=inherited MakeCmdLine;
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if (asminfo^.id in [as_clang_gas,as_clang_asdarwin]) then
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begin
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if fputypestrllvm[current_settings.fputype] <> '' then
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result:='-m'+fputypestrllvm[current_settings.fputype]+' '+result;
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{ Apple arm always uses softfp floating point ABI }
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result:='-mfloat-abi=softfp '+result;
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end;
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end;
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procedure TArmAppleGNUAssembler.WriteExtraHeader;
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begin
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inherited WriteExtraHeader;
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if TArmInstrWriter(InstrWriter).unified_syntax then
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writer.AsmWriteLn(#9'.syntax unified');
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end;
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{****************************************************************************}
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{ Helper routines for Instruction Writer }
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{****************************************************************************}
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function getreferencestring(var ref : treference) : string;
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var
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s : string;
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begin
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with ref do
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begin
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{$ifdef extdebug}
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// if base=NR_NO then
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// internalerror(200308292);
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// if ((index<>NR_NO) or (shiftmode<>SM_None)) and ((offset<>0) or (symbol<>nil)) then
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// internalerror(200308293);
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{$endif extdebug}
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if assigned(symbol) then
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begin
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if (base<>NR_NO) and not(is_pc(base)) then
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internalerror(200309011);
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s:=symbol.name;
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if offset<>0 then
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s:=s+tostr_with_plus(offset);
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if refaddr=addr_pic then
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s:=s+'(PLT)';
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end
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else
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begin
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s:='['+gas_regname(base);
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if addressmode=AM_POSTINDEXED then
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s:=s+']';
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if index<>NR_NO then
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begin
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if signindex<0 then
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s:=s+', -'
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else
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s:=s+', ';
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s:=s+gas_regname(index);
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{RRX always rotates by 1 bit and does not take an imm}
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if shiftmode = SM_RRX then
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s:=s+', rrx'
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else if shiftmode <> SM_None then
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s:=s+', '+gas_shiftmode2str[shiftmode]+' #'+tostr(shiftimm);
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end
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else if offset<>0 then
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s:=s+', #'+tostr(offset);
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case addressmode of
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AM_OFFSET:
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s:=s+']';
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AM_PREINDEXED:
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s:=s+']!';
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end;
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end;
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end;
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getreferencestring:=s;
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end;
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function getopstr(const o:toper) : string;
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var
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hs : string;
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first : boolean;
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r, rs : tsuperregister;
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begin
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case o.typ of
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top_reg:
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getopstr:=gas_regname(o.reg);
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top_shifterop:
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begin
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{RRX is special, it only rotates by 1 and does not take any shiftervalue}
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if o.shifterop^.shiftmode=SM_RRX then
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getopstr:='rrx'
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else if (o.shifterop^.rs<>NR_NO) and (o.shifterop^.shiftimm=0) then
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getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs)
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else if (o.shifterop^.rs=NR_NO) then
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getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
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else internalerror(200308282);
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end;
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top_const:
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getopstr:='#'+tostr(longint(o.val));
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top_regset:
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begin
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getopstr:='{';
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first:=true;
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if R_SUBFS=o.subreg then
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begin
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for r:=0 to 31 do // S0 to S31
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if r in o.regset^ then
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begin
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if not(first) then
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getopstr:=getopstr+',';
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if odd(r) then
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rs:=(r shr 1)+RS_S1
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else
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rs:=(r shr 1)+RS_S0;
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getopstr:=getopstr+gas_regname(newreg(o.regtyp,rs,o.subreg));
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first:=false;
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end;
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end
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else if R_SUBFD=o.subreg then
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begin
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for r:=0 to 31 do
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if r in o.regset^ then
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begin
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if not(first) then
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getopstr:=getopstr+',';
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rs:=r+RS_D0;
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getopstr:=getopstr+gas_regname(newreg(o.regtyp,rs,o.subreg));
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first:=false;
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end;
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end
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else
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begin
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for r:=RS_R0 to RS_R15 do
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if r in o.regset^ then
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begin
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if not(first) then
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getopstr:=getopstr+',';
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getopstr:=getopstr+gas_regname(newreg(o.regtyp,r,o.subreg));
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first:=false;
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end;
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end;
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getopstr:=getopstr+'}';
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if o.usermode then
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getopstr:=getopstr+'^';
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end;
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top_conditioncode:
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getopstr:=cond2str[o.cc];
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top_modeflags:
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begin
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getopstr:='';
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if mfA in o.modeflags then getopstr:=getopstr+'a';
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if mfI in o.modeflags then getopstr:=getopstr+'i';
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if mfF in o.modeflags then getopstr:=getopstr+'f';
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end;
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top_ref:
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if o.ref^.refaddr=addr_full then
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begin
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hs:=o.ref^.symbol.name;
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if o.ref^.offset>0 then
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hs:=hs+'+'+tostr(o.ref^.offset)
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else
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if o.ref^.offset<0 then
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hs:=hs+tostr(o.ref^.offset);
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getopstr:=hs;
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end
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else
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getopstr:=getreferencestring(o.ref^);
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top_specialreg:
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begin
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getopstr:=gas_regname(o.specialreg);
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if o.specialflags<>[] then
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begin
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getopstr:=getopstr+'_';
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if srC in o.specialflags then getopstr:=getopstr+'c';
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if srX in o.specialflags then getopstr:=getopstr+'x';
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if srF in o.specialflags then getopstr:=getopstr+'f';
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if srS in o.specialflags then getopstr:=getopstr+'s';
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end;
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end;
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top_realconst:
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begin
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str(o.val_real,Result);
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Result:='#'+Result;
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end
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else
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internalerror(2002070604);
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end;
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end;
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Procedure TArmInstrWriter.WriteInstruction(hp : tai);
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var op: TAsmOp;
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postfix,s: string;
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i: byte;
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sep: string[3];
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begin
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op:=taicpu(hp).opcode;
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postfix:='';
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if GenerateThumb2Code then
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begin
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if taicpu(hp).wideformat then
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postfix:='.w';
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end;
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if unified_syntax then
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begin
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if taicpu(hp).ops = 0 then
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s:=#9+gas_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix]
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else if taicpu(hp).oppostfix in [PF_8..PF_U32F64] then
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s:=#9+gas_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix]
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else
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s:=#9+gas_op2str[op]+oppostfix2str[taicpu(hp).oppostfix]+cond2str[taicpu(hp).condition]+postfix; // Conditional infixes are deprecated in unified syntax
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end
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else
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s:=#9+gas_op2str[op]+cond2str[taicpu(hp).condition]+oppostfix2str[taicpu(hp).oppostfix];
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if taicpu(hp).ops<>0 then
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begin
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sep:=#9;
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for i:=0 to taicpu(hp).ops-1 do
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begin
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// debug code
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// writeln(s);
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// writeln(taicpu(hp).fileinfo.line);
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{ LDM and STM use references as first operand but they are written like a register }
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if (i=0) and (op in [A_LDM,A_STM,A_FSTM,A_FLDM,A_VSTM,A_VLDM,A_SRS,A_RFE]) then
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begin
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case taicpu(hp).oper[0]^.typ of
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top_ref:
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begin
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s:=s+sep+gas_regname(taicpu(hp).oper[0]^.ref^.index);
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if taicpu(hp).oper[0]^.ref^.addressmode=AM_PREINDEXED then
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s:=s+'!';
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end;
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top_reg:
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s:=s+sep+gas_regname(taicpu(hp).oper[0]^.reg);
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else
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internalerror(200311292);
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end;
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end
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{ register count of SFM and LFM is written without # }
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else if (i=1) and (op in [A_SFM,A_LFM]) then
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begin
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case taicpu(hp).oper[1]^.typ of
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top_const:
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s:=s+sep+tostr(taicpu(hp).oper[1]^.val);
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else
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internalerror(200311292);
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end;
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end
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else
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s:=s+sep+getopstr(taicpu(hp).oper[i]^);
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sep:=',';
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end;
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end;
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owner.writer.AsmWriteLn(s);
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end;
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const
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as_arm_gas_info : tasminfo =
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(
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id : as_gas;
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idtxt : 'AS';
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asmbin : 'as';
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asmcmd : '-o $OBJ $EXTRAOPT $ASM';
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supported_targets : [system_arm_linux,system_arm_netbsd,system_arm_wince,system_arm_gba,system_arm_palmos,system_arm_nds,
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system_arm_embedded,system_arm_symbian,system_arm_android,system_arm_aros];
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flags : [af_needar,af_smartlink_sections];
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labelprefix : '.L';
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comment : '# ';
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dollarsign: '$';
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);
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as_arm_gas_darwin_info : tasminfo =
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(
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id : as_darwin;
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idtxt : 'AS-DARWIN';
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asmbin : 'as';
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asmcmd : '-o $OBJ $EXTRAOPT $ASM -arch $ARCH';
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supported_targets : [system_arm_ios];
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flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_stabs_use_function_absolute_addresses];
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labelprefix : 'L';
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comment : '# ';
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dollarsign: '$';
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);
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as_arm_clang_darwin_info : tasminfo =
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(
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id : as_clang_asdarwin;
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idtxt : 'CLANG';
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asmbin : 'clang';
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asmcmd : '-x assembler -c -target $TRIPLET -o $OBJ $EXTRAOPT -x assembler $ASM';
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supported_targets : [system_arm_ios];
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flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm];
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labelprefix : 'L';
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comment : '# ';
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dollarsign: '$';
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);
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begin
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RegisterAssembler(as_arm_gas_info,TARMGNUAssembler);
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RegisterAssembler(as_arm_gas_darwin_info,TArmAppleGNUAssembler);
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RegisterAssembler(as_arm_clang_darwin_info,TArmAppleGNUAssembler);
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end.
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