fpc/compiler/sparcgen/spreg.dat

;
; Sparc registers
;
; layout
; <name>,<regtype>,<regnum>,<stdname>,<stabidx>,<dwarfidx>
;
NO,$00,$00,$00,INVALID,-1,-1
; Integer registers
G0,$01,$00,$00,%g0,0,0
G1,$01,$00,$01,%g1,1,1
G2,$01,$00,$02,%g2,2,2
G3,$01,$00,$03,%g3,3,3
G4,$01,$00,$04,%g4,4,4
G5,$01,$00,$05,%g5,5,5
G6,$01,$00,$06,%g6,6,6
G7,$01,$00,$07,%g7,7,7
O0,$01,$00,$08,%o0,8,8
O1,$01,$00,$09,%o1,9,9
O2,$01,$00,$0a,%o2,10,10
O3,$01,$00,$0b,%o3,11,11
O4,$01,$00,$0c,%o4,12,12
O5,$01,$00,$0d,%o5,13,13
O6,$01,$00,$0e,%o6,14,14
O7,$01,$00,$0f,%o7,15,15
L0,$01,$00,$10,%l0,16,16
L1,$01,$00,$11,%l1,17,17
L2,$01,$00,$12,%l2,18,18
L3,$01,$00,$13,%l3,19,19
L4,$01,$00,$14,%l4,20,20
L5,$01,$00,$15,%l5,21,21
L6,$01,$00,$16,%l6,22,22
L7,$01,$00,$17,%l7,23,23
I0,$01,$00,$18,%i0,24,24
I1,$01,$00,$19,%i1,25,25
I2,$01,$00,$1a,%i2,26,26
I3,$01,$00,$1b,%i3,27,27
I4,$01,$00,$1c,%i4,28,28
I5,$01,$00,$1d,%i5,29,29
I6,$01,$00,$1e,%i6,30,30
I7,$01,$00,$1f,%i7,31,31
; Aliases for stackpointer (%o6) and framepointer (%i6)
FP,$01,$04,$1e,%fp,30,30
SP,$01,$04,$0e,%sp,14,14
; Float registers, single use
F0,$02,$06,$00,%f0,32,32
F1,$02,$06,$01,%f1,33,33
F2,$02,$06,$02,%f2,34,34
F3,$02,$06,$03,%f3,35,35
F4,$02,$06,$04,%f4,36,36
F5,$02,$06,$05,%f5,37,37
F6,$02,$06,$06,%f6,38,38
F7,$02,$06,$07,%f7,39,39
F8,$02,$06,$08,%f8,40,40
F9,$02,$06,$09,%f9,41,41
F10,$02,$06,$0a,%f10,42,42
F11,$02,$06,$0b,%f11,43,43
F12,$02,$06,$0c,%f12,44,44
F13,$02,$06,$0d,%f13,45,45
F14,$02,$06,$0e,%f14,46,46
F15,$02,$06,$0f,%f15,47,47
F16,$02,$06,$10,%f16,48,48
F17,$02,$06,$11,%f17,49,49
F18,$02,$06,$12,%f18,50,50
F19,$02,$06,$13,%f19,51,51
F20,$02,$06,$14,%f20,52,52
F21,$02,$06,$15,%f21,53,53
F22,$02,$06,$16,%f22,54,54
F23,$02,$06,$17,%f23,55,55
F24,$02,$06,$18,%f24,56,56
F25,$02,$06,$19,%f25,57,57
F26,$02,$06,$1a,%f26,58,58
F27,$02,$06,$1b,%f27,59,59
F28,$02,$06,$1c,%f28,60,60
F29,$02,$06,$1d,%f29,61,61
F30,$02,$06,$1e,%f30,62,62
F31,$02,$06,$1f,%f31,63,63
; Float registers, double use
; Re-enabled 2012-03-30 Pierre
D0,$02,$07,$00,%d0,72,72
D2,$02,$07,$02,%d2,73,73
D4,$02,$07,$04,%d4,74,74
D6,$02,$07,$06,%d6,75,75
D8,$02,$07,$08,%d8,76,76
D10,$02,$07,$0a,%d10,77,77
D12,$02,$07,$0c,%d12,78,78
D14,$02,$07,$0e,%d14,79,79
D16,$02,$07,$10,%d16,80,80
D18,$02,$07,$12,%d18,81,81
D20,$02,$07,$14,%d20,82,82
D22,$02,$07,$16,%d22,83,83
D24,$02,$07,$18,%d24,84,84
D26,$02,$07,$1a,%d26,85,85
D28,$02,$07,$1c,%d28,86,86
D30,$02,$07,$1e,%d30,87,87
D32,$02,$07,$20,%d32,88,88,SPARC64
D34,$02,$07,$22,%d34,89,89,SPARC64
D36,$02,$07,$24,%d36,90,90,SPARC64
D38,$02,$07,$26,%d38,91,91,SPARC64
D40,$02,$07,$28,%d40,92,92,SPARC64
D42,$02,$07,$2A,%d42,93,93,SPARC64
D44,$02,$07,$2C,%d44,94,94,SPARC64
D46,$02,$07,$2E,%d46,95,95,SPARC64
D48,$02,$07,$30,%d48,96,96,SPARC64
D50,$02,$07,$32,%d50,97,97,SPARC64
D52,$02,$07,$34,%d52,98,98,SPARC64
D54,$02,$07,$36,%d54,99,99,SPARC64
D56,$02,$07,$38,%d56,100,100,SPARC64
D58,$02,$07,$3A,%d58,101,101,SPARC64
D60,$02,$07,$3C,%d60,102,102,SPARC64
D62,$02,$07,$3E,%d62,103,103,SPARC64

; Coprocessor registers
C0,$03,$00,$00,%c0,32,32
C1,$03,$00,$01,%c1,32,32
C2,$03,$00,$02,%c2,32,32
C3,$03,$00,$03,%c3,32,32
C4,$03,$00,$04,%c4,32,32
C5,$03,$00,$05,%c5,32,32
C6,$03,$00,$06,%c6,32,32
C7,$03,$00,$07,%c7,32,32
C8,$03,$00,$08,%c8,32,32
C9,$03,$00,$09,%c9,32,32
C10,$03,$00,$0a,%c10,32,32
C11,$03,$00,$0b,%c11,32,32
C12,$03,$00,$0c,%c12,32,32
C13,$03,$00,$0d,%c13,32,32
C14,$03,$00,$0e,%c14,32,32
C15,$03,$00,$0f,%c15,32,32
C16,$03,$00,$10,%c16,32,32
C17,$03,$00,$11,%c17,32,32
C18,$03,$00,$12,%c18,32,32
C19,$03,$00,$13,%c19,32,32
C20,$03,$00,$14,%c20,32,32
C21,$03,$00,$15,%c21,32,32
C22,$03,$00,$16,%c22,32,32
C23,$03,$00,$17,%c23,32,32
C24,$03,$00,$18,%c24,32,32
C25,$03,$00,$19,%c25,32,32
C26,$03,$00,$1a,%c26,32,32
C27,$03,$00,$1b,%c27,32,32
C28,$03,$00,$1c,%c28,32,32
C29,$03,$00,$1d,%c29,32,32
C30,$03,$00,$1e,%c30,32,32
C31,$03,$00,$1f,%c31,32,32

; Special registers
FSR,$05,$00,$00,%fsr,70,70
FQ,$05,$00,$01,%fq,65,65
CSR,$05,$00,$02,%csr,71,71
CQ,$05,$00,$03,%cq,65,65
PSR,$05,$00,$04,%psr,65,65
TBR,$05,$00,$05,%tbr,67,67
WIM,$05,$00,$06,%wim,66,66
Y,$05,$00,$07,%y,64,64
ICC,$05,$00,$08,%icc,63,63
XCC,$05,$00,$09,%xcc,62,62,SPARC64
FCC0,$05,$00,$0a,%fcc0,63,63
FCC1,$05,$00,$0b,%fcc1,63,63
FCC2,$05,$00,$0c,%fcc2,63,63
FCC3,$05,$00,$0d,%fcc3,63,63

; Ancillary State Registers
ASR0,$04,$00,$00,%asr0,32,32
ASR1,$04,$00,$01,%asr1,32,32
ASR2,$04,$00,$02,%asr2,32,32
ASR3,$04,$00,$03,%asr3,32,32
ASR4,$04,$00,$04,%asr4,32,32
ASR5,$04,$00,$05,%asr5,32,32
ASR6,$04,$00,$06,%asr6,32,32
ASR7,$04,$00,$07,%asr7,32,32
ASR8,$04,$00,$08,%asr8,32,32
ASR9,$04,$00,$09,%asr9,32,32
ASR10,$04,$00,$0a,%asr10,32,32
ASR11,$04,$00,$0b,%asr11,32,32
ASR12,$04,$00,$0c,%asr12,32,32
ASR13,$04,$00,$0d,%asr13,32,32
ASR14,$04,$00,$0e,%asr14,32,32
ASR15,$04,$00,$0f,%asr15,32,32
ASR16,$04,$00,$10,%asr16,32,32
ASR17,$04,$00,$11,%asr17,32,32
ASR18,$04,$00,$12,%asr18,32,32
ASR19,$04,$00,$13,%asr19,32,32
ASR20,$04,$00,$14,%asr20,32,32
ASR21,$04,$00,$15,%asr21,32,32
ASR22,$04,$00,$16,%asr22,32,32
ASR23,$04,$00,$17,%asr23,32,32
ASR24,$04,$00,$18,%asr24,32,32
ASR25,$04,$00,$19,%asr25,32,32
ASR26,$04,$00,$1a,%asr26,32,32
ASR27,$04,$00,$1b,%asr27,32,32
ASR28,$04,$00,$1c,%asr28,32,32
ASR29,$04,$00,$1d,%asr29,32,32
ASR30,$04,$00,$1e,%asr30,32,32
ASR31,$04,$00,$1f,%asr31,32,32