mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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838 lines
26 KiB
ObjectPascal
838 lines
26 KiB
ObjectPascal
{
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Register definitions and utility code for XMC450x series
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Created by Jeppe Johansen 2012 - jeppe@j-software.dk
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}
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unit xmc4500;
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{$goto on}
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interface
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type
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TBitvector32 = bitpacked array[0..31] of 0..1;
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{$PACKRECORDS 2}
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const
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Peripheral0Base = $40000000;
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Peripheral1Base = $48000000;
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Peripheral2Base = $50000000;
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Peripheral3Base = $58000000;
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SCUBase = Peripheral2Base+$4000;
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GCUBase = SCUBase+$0000;
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PCUBase = SCUBase+$0200;
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HCUBase = SCUBase+$0300;
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RCUBase = SCUBase+$0400;
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CCUBase = SCUBase+$0600;
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type
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TPBARegisters = record
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STS,
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WADDR: longword;
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end;
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TFLASHRegisters = record
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res1: array[0..1] of longword;
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ID: longword;
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res2: longword;
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FSR,
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FCON,
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MARP,
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PROCON0,
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PROCON1,
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PROCON2: longword;
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end;
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TWDTRegisters = record
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ID,
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CTR,
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SRV,
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TIM,
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WLB,
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WUB,
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WDTSTS,
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WDTCLR: longword;
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end;
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TRTCRegisters = record
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ID,
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CTR,
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RAWSTAT,
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STSSR,
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MSKSR,
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CLRSR,
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ATIM0,
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ATIM1,
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TIM0,
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TIM1: longword;
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end;
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TLEDTSRegisters = record
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ID,
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GLOBCTL,
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FNCTL,
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EVFR,
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TSVAL,
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LINE0,
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LINE1,
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LDCMP0,
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LDCMP1,
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TSCMP0,
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TSCMP1: longword;
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end;
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TEBURegisters = record
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CLC,
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MODCON,
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ID,
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USERCON,
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res0,res1,
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ADDRSEL0,
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ADDRSEL1,
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ADDRSEL2,
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ADDRSEL3,
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BUSRCON0,
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BUSRAP0,
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BUSWCON0,
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BUSWAP0,
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BUSRCON1,
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BUSRAP1,
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BUSWCON1,
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BUSWAP1,
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BUSRCON2,
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BUSRAP2,
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BUSWCON2,
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BUSWAP2,
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BUSRCON3,
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BUSRAP3,
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BUSWCON3,
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BUSWAP3,
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SDRMCON,
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SDRMOD,
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SDRMREF,
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SDRSTAT: longword;
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end;
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TETHRegisters = record
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MacConfiguration,
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MacFrameFilter,
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HashTableHigh,
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HashTableLow,
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GmiiAddress,
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GmiiData,
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FlowControl,
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VlanTag,
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Version,
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Debug,
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RemoteWakeUpFrameFilter,
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PmtControlStatus,
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res0,res1,
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InterruptStatus,
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InterruptMask,
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MacAddress0High,
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MacAddress0Low,
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MacAddress1High,
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MacAddress1Low,
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MacAddress2High,
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MacAddress2Low,
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MacAddress3High,
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MacAddress3Low: longword;
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res2: array[0..38] of longword;
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// $100 - $288 MMC Management Counters
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MmcRegs: array[0..96] of longword;
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res3: array[0..286] of longword;
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// $700 - $72C IEEE1588
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TimestampControl,
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SubSecondIncrement,
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SystemTimeSeconds,
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SystemTimeNanoseconds,
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SystemTimeSecondsUpdate,
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SystemTimeNanosecondsUpdate,
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TimestampAddend,
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TargetTimeSeconds,
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TargetTimeNanoseconds,
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SystemTimeHigherWordSeconds,
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TimestampStatus,
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PpsControl: longword;
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res4: array[0..563] of longword;
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// $1000 - $1024 DMA
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BusMode,
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TransmitPollDemand,
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ReceivePollDemand,
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ReceiveDescriptorListAddress,
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TransmitDescriptorListAddress,
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Status,
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OperationMode,
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InterruptEnable,
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MissedFrameAndBufferOverflowCounter,
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ReceiveInterruptWatchdogTimer,
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res5,
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AhbStatus: longword;
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doNotUse: array[0..5] of longword;
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CurrentHostTransmitDescriptor,
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CurrentHostReceiveDescriptor,
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CurrentHostTransmitBufferAddress,
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CurrentHostReceiveBufferAddress,
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HWFeatures: longword;
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end;
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TGPIORegisters = record
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Output,
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OMR,
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res0,res1: longword;
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IOCR: array[0..3] of longword;
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res2,
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Input: longword;
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res3: array[0..5] of longword;
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PDR: array[0..1] of longword;
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res5: array[0..5] of longword;
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PDISC: longword;
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res6: array[0..2] of longword;
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PPS,
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HWSel: longword;
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res7: array[0..33] of longword;
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end;
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{$ALIGN 2}
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var
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// Peripheral bus registers
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PBA0: TPBARegisters absolute Peripheral0Base;
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PBA1: TPBARegisters absolute Peripheral1Base;
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// PMU - Program memory unit
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PMU0_ID: longword absolute Peripheral3Base+$0508;
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// PREF - Prefetch unit
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PREF_PCON: longword absolute Peripheral3Base+$04000;
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FLASH0: TFLASHRegisters absolute Peripheral3Base+$02000;
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WDT: TWDTRegisters absolute Peripheral2Base+$08000;
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RTC: TRTCRegisters absolute Peripheral2Base+$04A00;
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LEDTS0: TLEDTSRegisters absolute Peripheral1Base+$10000;
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EBU: TEBURegisters absolute Peripheral3Base+$08000;
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ETH: TETHRegisters absolute Peripheral2Base+$0C000;
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// GPIO
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P0: TGPIORegisters absolute Peripheral1Base+$28000;
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P1: TGPIORegisters absolute Peripheral1Base+$28100;
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P2: TGPIORegisters absolute Peripheral1Base+$28200;
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P3: TGPIORegisters absolute Peripheral1Base+$28300;
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P4: TGPIORegisters absolute Peripheral1Base+$28400;
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P5: TGPIORegisters absolute Peripheral1Base+$28500;
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P6: TGPIORegisters absolute Peripheral1Base+$28600;
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P14: TGPIORegisters absolute Peripheral1Base+$28E00;
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P15: TGPIORegisters absolute Peripheral1Base+$28F00;
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SDMMC_BLOCK_SIZE: longword absolute Peripheral1Base+$1C004;
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SDMMC_BLOCK_COUNT: longword absolute Peripheral1Base+$1C006;
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SDMMC_ARGUMENT1: longword absolute Peripheral1Base+$1C008;
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SDMMC_TRANSFER_MODE: longword absolute Peripheral1Base+$1C00C;
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SDMMC_COMMAND: longword absolute Peripheral1Base+$1C00E;
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SDMMC_RESPONSE0: longword absolute Peripheral1Base+$1C010;
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SDMMC_RESPONSE2: longword absolute Peripheral1Base+$1C014;
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SDMMC_RESPONSE4: longword absolute Peripheral1Base+$1C018;
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SDMMC_RESPONSE6: longword absolute Peripheral1Base+$1C01C;
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SDMMC_DATA_BUFFER: longword absolute Peripheral1Base+$1C020;
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SDMMC_PRESENT_STATE: longword absolute Peripheral1Base+$1C024;
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SDMMC_HOST_CTRL: longword absolute Peripheral1Base+$1C028;
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SDMMC_POWER_CTRL: longword absolute Peripheral1Base+$1C029;
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SDMMC_BLOCK_GAP_CTRL: longword absolute Peripheral1Base+$1C02A;
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SDMMC_WAKEUP_CTRL: longword absolute Peripheral1Base+$1C02B;
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SDMMC_CLOCK_CTRL: longword absolute Peripheral1Base+$1C02C;
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SDMMC_TIMEOUT_CTRL: longword absolute Peripheral1Base+$1C02E;
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SDMMC_SW_RESET: longword absolute Peripheral1Base+$1C02F;
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SDMMC_INT_STATUS_NORM: longword absolute Peripheral1Base+$1C030;
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SDMMC_INT_STATUS_ERR: longword absolute Peripheral1Base+$1C032;
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SDMMC_EN_INT_STATUS_NORM: longword absolute Peripheral1Base+$1C034;
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SDMMC_EN_INT_STATUS_ERR: longword absolute Peripheral1Base+$1C036;
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SDMMC_EN_INT_SIGNAL_NORM: longword absolute Peripheral1Base+$1C038;
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SDMMC_ACMD_ERR_STATUS: longword absolute Peripheral1Base+$1C03C;
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SDMMC_FORCE_EVENT_ACMD_ERR_STATUS: longword absolute Peripheral1Base+$1C050;
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SDMMC_FORCE_EVENT_ERR_STATUS: longword absolute Peripheral1Base+$1C052;
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SDMMC_DEBUG_SEL: longword absolute Peripheral1Base+$1C074;
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SDMMC_SPI: longword absolute Peripheral1Base+$1C0F0;
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SDMMC_SLOT_INT_STATUS: longword absolute Peripheral1Base+$1C0FC;
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GCU_ID: longword absolute GCUBase+$000;
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GCU_IDCHIP: longword absolute GCUBase+$004;
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GCU_IDMANUF: longword absolute GCUBase+$008;
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GCU_STCON: longword absolute GCUBase+$010;
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GCU_GPR0: longword absolute GCUBase+$02C;
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GCU_GPR1: longword absolute GCUBase+$030;
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GCU_ETH0_CON: longword absolute GCUBase+$040;
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GCU_CCUCON: longword absolute GCUBase+$04C;
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GCU_SRSTAT: longword absolute GCUBase+$074;
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GCU_SRRAW: longword absolute GCUBase+$078;
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GCU_SRMSK: longword absolute GCUBase+$07C;
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GCU_SRCLR: longword absolute GCUBase+$080;
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GCU_SRSET: longword absolute GCUBase+$084;
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GCU_NMIREQEN: longword absolute GCUBase+$088;
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GCU_DTSCON: longword absolute GCUBase+$08C;
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GCU_DTSSTAT: longword absolute GCUBase+$090;
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GCU_SDMMCDEL: longword absolute GCUBase+$09C;
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GCU_G0RCEN: longword absolute GCUBase+$0A0;
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GCU_G1RCEN: longword absolute GCUBase+$0A4;
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GCU_MIRRSTS: longword absolute GCUBase+$0C4;
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GCU_RMACR: longword absolute GCUBase+$0C8;
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GCU_RMADATA: longword absolute GCUBase+$0CC;
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GCU_PEEN: longword absolute GCUBase+$13C;
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GCU_MCHKCON: longword absolute GCUBase+$140;
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GCU_PETE: longword absolute GCUBase+$144;
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GCU_PERSTEN: longword absolute GCUBase+$147;
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GCU_PEFLAG: longword absolute GCUBase+$150;
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GCU_PMTPR: longword absolute GCUBase+$154;
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GCU_PMTSR: longword absolute GCUBase+$158;
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GCU_TRAPSTAT: longword absolute GCUBase+$160;
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GCU_TRAPRAW: longword absolute GCUBase+$164;
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GCU_TRAPDIS: longword absolute GCUBase+$168;
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GCU_TRAPCLR: longword absolute GCUBase+$16C;
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GCU_TRAPSET: longword absolute GCUBase+$170;
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PCU_PWRSTAT: longword absolute PCUBase+$00;
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PCU_PWRSET: longword absolute PCUBase+$04;
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PCU_PWRCLR: longword absolute PCUBase+$08;
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PCU_EVRSTAT: longword absolute PCUBase+$10;
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PCU_EVRVADCSTAT: longword absolute PCUBase+$14;
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PCU_PWRMON: longword absolute PCUBase+$2C;
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HCU_HDSTAT:longword absolute HCUBase+$00;
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HCU_HDCLR:longword absolute HCUBase+$04;
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HCU_HDSET:longword absolute HCUBase+$08;
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HCU_HDCR:longword absolute HCUBase+$0C;
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HCU_OSCSICTRL:longword absolute HCUBase+$14;
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HCU_OSCULSTAT:longword absolute HCUBase+$18;
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HCU_OSCULCTRL:longword absolute HCUBase+$1C;
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RCU_RSTSTAT: longword absolute RCUBase+$00;
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RCU_RSTSET: longword absolute RCUBase+$04;
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RCU_RSTCLR: longword absolute RCUBase+$08;
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RCU_PRSTAT0: longword absolute RCUBase+$0C;
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RCU_PRSET0: longword absolute RCUBase+$10;
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RCU_PRCLR0: longword absolute RCUBase+$14;
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RCU_PRSTAT1: longword absolute RCUBase+$18;
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RCU_PRSET1: longword absolute RCUBase+$1C;
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RCU_PRCLR1: longword absolute RCUBase+$20;
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RCU_PRSTAT2: longword absolute RCUBase+$24;
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RCU_PRSET2: longword absolute RCUBase+$28;
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RCU_PRCLR2: longword absolute RCUBase+$2C;
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RCU_PRSTAT3: longword absolute RCUBase+$30;
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RCU_PRSET3: longword absolute RCUBase+$34;
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RCU_PRCLR3: longword absolute RCUBase+$38;
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CCU_CLKSTAT: longword absolute CCUBase+$000;
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CCU_CLKSET: longword absolute CCUBase+$004;
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CCU_CLKCLR: longword absolute CCUBase+$008;
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CCU_SYSCLKCR: longword absolute CCUBase+$00C;
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CCU_CPUCLKCR: longword absolute CCUBase+$010;
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CCU_PBCLKCR: longword absolute CCUBase+$014;
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CCU_USBCLKCR: longword absolute CCUBase+$018;
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CCU_EBUCLKCR: longword absolute CCUBase+$01C;
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CCU_CCUCLKCR: longword absolute CCUBase+$020;
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CCU_WDTCLKCR: longword absolute CCUBase+$024;
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CCU_EXTCLKCR: longword absolute CCUBase+$028;
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CCU_SLEEPCR: longword absolute CCUBase+$030;
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CCU_DSLEEPCR: longword absolute CCUBase+$034;
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CCU_OSCHPSTAT: longword absolute CCUBase+$100;
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CCU_OSCHPCTRL: longword absolute CCUBase+$104;
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CCU_CLKCALCONST: longword absolute CCUBase+$10C;
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CCU_PLLSTAT: longword absolute CCUBase+$110;
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CCU_PLLCON0: longword absolute CCUBase+$114;
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CCU_PLLCON1: longword absolute CCUBase+$118;
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CCU_PLLCON2: longword absolute CCUBase+$11C;
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CCU_USBPLLSTAT: longword absolute CCUBase+$120;
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CCU_USBPLLCON: longword absolute CCUBase+$124;
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CCU_CLKMXSTAT: longword absolute CCUBase+$138;
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implementation
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procedure NMI_interrupt; external name 'NMI_interrupt';
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procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
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procedure MemManage_interrupt; external name 'MemManage_interrupt';
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procedure BusFault_interrupt; external name 'BusFault_interrupt';
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procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
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procedure SWI_interrupt; external name 'SWI_interrupt';
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procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
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procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
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procedure SysTick_interrupt; external name 'SysTick_interrupt';
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procedure SCU_SR0_irq; external name 'SCU_SR0_irq';
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procedure ERU0_SR0_irq; external name 'ERU0_SR0_irq';
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procedure ERU0_SR1_irq; external name 'ERU0_SR1_irq';
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procedure ERU0_SR2_irq; external name 'ERU0_SR2_irq';
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procedure ERU0_SR3_irq; external name 'ERU0_SR3_irq';
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procedure ERU1_SR0_irq; external name 'ERU1_SR0_irq';
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procedure ERU1_SR1_irq; external name 'ERU1_SR1_irq';
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procedure ERU1_SR2_irq; external name 'ERU1_SR2_irq';
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procedure ERU1_SR3_irq; external name 'ERU1_SR3_irq';
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procedure PMU0_SR0_irq; external name 'PMU0_SR0_irq';
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procedure CADC_C0SR0_irq; external name 'CADC_C0SR0_irq';
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procedure CADC_C0SR1_irq; external name 'CADC_C0SR1_irq';
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procedure CADC_C0SR2_irq; external name 'CADC_C0SR2_irq';
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procedure CADC_C0SR3_irq; external name 'CADC_C0SR3_irq';
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procedure CADC_G0SR0_irq; external name 'CADC_G0SR0_irq';
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procedure CADC_G0SR1_irq; external name 'CADC_G0SR1_irq';
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procedure CADC_G0SR2_irq; external name 'CADC_G0SR2_irq';
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procedure CADC_G0SR3_irq; external name 'CADC_G0SR3_irq';
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procedure CADC_G1SR0_irq; external name 'CADC_G1SR0_irq';
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procedure CADC_G1SR1_irq; external name 'CADC_G1SR1_irq';
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procedure CADC_G1SR2_irq; external name 'CADC_G1SR2_irq';
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procedure CADC_G1SR3_irq; external name 'CADC_G1SR3_irq';
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procedure CADC_G2SR0_irq; external name 'CADC_G2SR0_irq';
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procedure CADC_G2SR1_irq; external name 'CADC_G2SR1_irq';
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procedure CADC_G2SR2_irq; external name 'CADC_G2SR2_irq';
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procedure CADC_G2SR3_irq; external name 'CADC_G2SR3_irq';
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procedure CADC_G3SR0_irq; external name 'CADC_G3SR0_irq';
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procedure CADC_G3SR1_irq; external name 'CADC_G3SR1_irq';
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procedure CADC_G3SR2_irq; external name 'CADC_G3SR2_irq';
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procedure CADC_G3SR3_irq; external name 'CADC_G3SR3_irq';
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procedure DSD_SRM0_irq; external name 'DSD_SRM0_irq';
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procedure DSD_SRM1_irq; external name 'DSD_SRM1_irq';
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procedure DSD_SRM2_irq; external name 'DSD_SRM2_irq';
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procedure DSD_SRM3_irq; external name 'DSD_SRM3_irq';
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procedure DSD_SRA0_irq; external name 'DSD_SRA0_irq';
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procedure DSD_SRA1_irq; external name 'DSD_SRA1_irq';
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procedure DSD_SRA2_irq; external name 'DSD_SRA2_irq';
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procedure DSD_SRA3_irq; external name 'DSD_SRA3_irq';
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procedure DAC_SR0_irq; external name 'DAC_SR0_irq';
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procedure DAC_SR1_irq; external name 'DAC_SR1_irq';
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procedure CCU40_SR0_irq; external name 'CCU40_SR0_irq';
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procedure CCU40_SR1_irq; external name 'CCU40_SR1_irq';
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procedure CCU40_SR2_irq; external name 'CCU40_SR2_irq';
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procedure CCU40_SR3_irq; external name 'CCU40_SR3_irq';
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procedure CCU41_SR0_irq; external name 'CCU41_SR0_irq';
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procedure CCU41_SR1_irq; external name 'CCU41_SR1_irq';
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procedure CCU41_SR2_irq; external name 'CCU41_SR2_irq';
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procedure CCU41_SR3_irq; external name 'CCU41_SR3_irq';
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procedure CCU42_SR0_irq; external name 'CCU42_SR0_irq';
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procedure CCU42_SR1_irq; external name 'CCU42_SR1_irq';
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procedure CCU42_SR2_irq; external name 'CCU42_SR2_irq';
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procedure CCU42_SR3_irq; external name 'CCU42_SR3_irq';
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procedure CCU43_SR0_irq; external name 'CCU43_SR0_irq';
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procedure CCU43_SR1_irq; external name 'CCU43_SR1_irq';
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procedure CCU43_SR2_irq; external name 'CCU43_SR2_irq';
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procedure CCU43_SR3_irq; external name 'CCU43_SR3_irq';
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procedure CCU80_SR0_irq; external name 'CCU80_SR0_irq';
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procedure CCU80_SR1_irq; external name 'CCU80_SR1_irq';
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procedure CCU80_SR2_irq; external name 'CCU80_SR2_irq';
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procedure CCU80_SR3_irq; external name 'CCU80_SR3_irq';
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procedure CCU81_SR0_irq; external name 'CCU81_SR0_irq';
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procedure CCU81_SR1_irq; external name 'CCU81_SR1_irq';
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procedure CCU81_SR2_irq; external name 'CCU81_SR2_irq';
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procedure CCU81_SR3_irq; external name 'CCU81_SR3_irq';
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procedure POSIF0_SR0_irq; external name 'POSIF0_SR0_irq';
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procedure POSIF0_SR1_irq; external name 'POSIF0_SR1_irq';
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procedure POSIF1_SR0_irq; external name 'POSIF1_SR0_irq';
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procedure POSIF1_SR1_irq; external name 'POSIF1_SR1_irq';
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procedure CAN_SR0_irq; external name 'CAN_SR0_irq';
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procedure CAN_SR1_irq; external name 'CAN_SR1_irq';
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procedure CAN_SR2_irq; external name 'CAN_SR2_irq';
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procedure CAN_SR3_irq; external name 'CAN_SR3_irq';
|
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procedure CAN_SR4_irq; external name 'CAN_SR4_irq';
|
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procedure CAN_SR5_irq; external name 'CAN_SR5_irq';
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procedure CAN_SR6_irq; external name 'CAN_SR6_irq';
|
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procedure CAN_SR7_irq; external name 'CAN_SR7_irq';
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procedure USIC0_SR0_irq; external name 'USIC0_SR0_irq';
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procedure USIC0_SR1_irq; external name 'USIC0_SR1_irq';
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procedure USIC0_SR2_irq; external name 'USIC0_SR2_irq';
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procedure USIC0_SR3_irq; external name 'USIC0_SR3_irq';
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procedure USIC0_SR4_irq; external name 'USIC0_SR4_irq';
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procedure USIC0_SR5_irq; external name 'USIC0_SR5_irq';
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procedure USIC1_SR0_irq; external name 'USIC1_SR0_irq';
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procedure USIC1_SR1_irq; external name 'USIC1_SR1_irq';
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procedure USIC1_SR2_irq; external name 'USIC1_SR2_irq';
|
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procedure USIC1_SR3_irq; external name 'USIC1_SR3_irq';
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procedure USIC1_SR4_irq; external name 'USIC1_SR4_irq';
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procedure USIC1_SR5_irq; external name 'USIC1_SR5_irq';
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procedure USIC2_SR0_irq; external name 'USIC2_SR0_irq';
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procedure USIC2_SR1_irq; external name 'USIC2_SR1_irq';
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procedure USIC2_SR2_irq; external name 'USIC2_SR2_irq';
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procedure USIC2_SR3_irq; external name 'USIC2_SR3_irq';
|
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procedure USIC2_SR4_irq; external name 'USIC2_SR4_irq';
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procedure USIC2_SR5_irq; external name 'USIC2_SR5_irq';
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procedure LEDTS0_SR0_irq; external name 'LEDTS0_SR0_irq';
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procedure FCE_SR0_irq; external name 'FCE_SR0_irq';
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procedure GPDMA0_SR0_irq; external name 'GPDMA0_SR0_irq';
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procedure SDMMC_SR0_irq; external name 'SDMMC_SR0_irq';
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procedure USB0_SR0_irq; external name 'USB0_SR0_irq';
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procedure ETH0_SR0_irq; external name 'ETH0_SR0_irq';
|
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procedure GPDMA1_SR0_irq; external name 'GPDMA1_SR0_irq';
|
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|
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{$define REMAP_VECTTAB}
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{$i cortexm4f_start.inc}
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procedure Vectors; assembler; nostackframe;
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label interrupt_vectors;
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asm
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.section ".init.interrupt_vectors"
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interrupt_vectors:
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.long _stack_top
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.long Startup
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.long NMI_interrupt
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.long Hardfault_interrupt
|
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.long MemManage_interrupt
|
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.long BusFault_interrupt
|
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.long UsageFault_interrupt
|
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.long 0
|
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.long 0
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.long 0
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.long 0
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.long SWI_interrupt
|
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.long DebugMonitor_interrupt
|
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.long 0
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.long PendingSV_interrupt
|
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.long SysTick_interrupt
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.long SCU_SR0_irq
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.long ERU0_SR0_irq
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.long ERU0_SR1_irq
|
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.long ERU0_SR2_irq
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.long ERU0_SR3_irq
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.long ERU1_SR0_irq
|
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.long ERU1_SR1_irq
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.long ERU1_SR2_irq
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.long ERU1_SR3_irq
|
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.long 0
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.long 0
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.long 0
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.long PMU0_SR0_irq
|
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.long 0
|
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.long CADC_C0SR0_irq
|
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.long CADC_C0SR1_irq
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.long CADC_C0SR2_irq
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.long CADC_C0SR3_irq
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.long CADC_G0SR0_irq
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.long CADC_G0SR1_irq
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.long CADC_G0SR2_irq
|
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.long CADC_G0SR3_irq
|
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.long CADC_G1SR0_irq
|
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.long CADC_G1SR1_irq
|
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.long CADC_G1SR2_irq
|
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.long CADC_G1SR3_irq
|
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.long CADC_G2SR0_irq
|
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.long CADC_G2SR1_irq
|
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.long CADC_G2SR2_irq
|
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.long CADC_G2SR3_irq
|
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.long CADC_G3SR0_irq
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.long CADC_G3SR1_irq
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.long CADC_G3SR2_irq
|
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.long CADC_G3SR3_irq
|
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.long DSD_SRM0_irq
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.long DSD_SRM1_irq
|
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.long DSD_SRM2_irq
|
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.long DSD_SRM3_irq
|
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.long DSD_SRA0_irq
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.long DSD_SRA1_irq
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.long DSD_SRA2_irq
|
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.long DSD_SRA3_irq
|
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.long DAC_SR0_irq
|
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.long DAC_SR1_irq
|
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.long CCU40_SR0_irq
|
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.long CCU40_SR1_irq
|
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.long CCU40_SR2_irq
|
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.long CCU40_SR3_irq
|
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.long CCU41_SR0_irq
|
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.long CCU41_SR1_irq
|
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.long CCU41_SR2_irq
|
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.long CCU41_SR3_irq
|
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.long CCU42_SR0_irq
|
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.long CCU42_SR1_irq
|
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.long CCU42_SR2_irq
|
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.long CCU42_SR3_irq
|
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.long CCU43_SR0_irq
|
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.long CCU43_SR1_irq
|
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.long CCU43_SR2_irq
|
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.long CCU43_SR3_irq
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.long CCU80_SR0_irq
|
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.long CCU80_SR1_irq
|
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.long CCU80_SR2_irq
|
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.long CCU80_SR3_irq
|
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.long CCU81_SR0_irq
|
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.long CCU81_SR1_irq
|
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.long CCU81_SR2_irq
|
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.long CCU81_SR3_irq
|
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.long POSIF0_SR0_irq
|
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.long POSIF0_SR1_irq
|
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.long POSIF1_SR0_irq
|
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.long POSIF1_SR1_irq
|
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.long 0
|
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.long 0
|
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.long 0
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.long 0
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.long CAN_SR0_irq
|
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.long CAN_SR1_irq
|
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.long CAN_SR2_irq
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.long CAN_SR3_irq
|
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.long CAN_SR4_irq
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.long CAN_SR5_irq
|
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.long CAN_SR6_irq
|
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.long CAN_SR7_irq
|
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.long USIC0_SR0_irq
|
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.long USIC0_SR1_irq
|
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.long USIC0_SR2_irq
|
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.long USIC0_SR3_irq
|
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.long USIC0_SR4_irq
|
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.long USIC0_SR5_irq
|
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.long USIC1_SR0_irq
|
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.long USIC1_SR1_irq
|
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.long USIC1_SR2_irq
|
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.long USIC1_SR3_irq
|
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.long USIC1_SR4_irq
|
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.long USIC1_SR5_irq
|
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.long USIC2_SR0_irq
|
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.long USIC2_SR1_irq
|
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.long USIC2_SR2_irq
|
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.long USIC2_SR3_irq
|
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.long USIC2_SR4_irq
|
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.long USIC2_SR5_irq
|
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.long LEDTS0_SR0_irq
|
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.long 0
|
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.long FCE_SR0_irq
|
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.long GPDMA0_SR0_irq
|
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.long SDMMC_SR0_irq
|
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.long USB0_SR0_irq
|
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.long ETH0_SR0_irq
|
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.long 0
|
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.long GPDMA1_SR0_irq
|
|
|
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.weak NMI_interrupt
|
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.weak Hardfault_interrupt
|
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.weak MemManage_interrupt
|
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.weak BusFault_interrupt
|
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.weak UsageFault_interrupt
|
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.weak SWI_interrupt
|
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.weak DebugMonitor_interrupt
|
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.weak PendingSV_interrupt
|
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.weak SysTick_interrupt
|
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.weak SCU_SR0_irq
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.weak ERU0_SR0_irq
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.weak ERU0_SR1_irq
|
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.weak ERU0_SR2_irq
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.weak ERU0_SR3_irq
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.weak ERU1_SR0_irq
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.weak ERU1_SR1_irq
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.weak ERU1_SR2_irq
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.weak ERU1_SR3_irq
|
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.weak PMU0_SR0_irq
|
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.weak CADC_C0SR0_irq
|
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.weak CADC_C0SR1_irq
|
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.weak CADC_C0SR2_irq
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.weak CADC_C0SR3_irq
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.weak CADC_G0SR0_irq
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.weak CADC_G0SR1_irq
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.weak CADC_G0SR2_irq
|
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.weak CADC_G0SR3_irq
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.weak CADC_G1SR0_irq
|
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.weak CADC_G1SR1_irq
|
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.weak CADC_G1SR2_irq
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.weak CADC_G1SR3_irq
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.weak CADC_G2SR0_irq
|
|
.weak CADC_G2SR1_irq
|
|
.weak CADC_G2SR2_irq
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|
.weak CADC_G2SR3_irq
|
|
.weak CADC_G3SR0_irq
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.weak CADC_G3SR1_irq
|
|
.weak CADC_G3SR2_irq
|
|
.weak CADC_G3SR3_irq
|
|
.weak DSD_SRM0_irq
|
|
.weak DSD_SRM1_irq
|
|
.weak DSD_SRM2_irq
|
|
.weak DSD_SRM3_irq
|
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.weak DSD_SRA0_irq
|
|
.weak DSD_SRA1_irq
|
|
.weak DSD_SRA2_irq
|
|
.weak DSD_SRA3_irq
|
|
.weak DAC_SR0_irq
|
|
.weak DAC_SR1_irq
|
|
.weak CCU40_SR0_irq
|
|
.weak CCU40_SR1_irq
|
|
.weak CCU40_SR2_irq
|
|
.weak CCU40_SR3_irq
|
|
.weak CCU41_SR0_irq
|
|
.weak CCU41_SR1_irq
|
|
.weak CCU41_SR2_irq
|
|
.weak CCU41_SR3_irq
|
|
.weak CCU42_SR0_irq
|
|
.weak CCU42_SR1_irq
|
|
.weak CCU42_SR2_irq
|
|
.weak CCU42_SR3_irq
|
|
.weak CCU43_SR0_irq
|
|
.weak CCU43_SR1_irq
|
|
.weak CCU43_SR2_irq
|
|
.weak CCU43_SR3_irq
|
|
.weak CCU80_SR0_irq
|
|
.weak CCU80_SR1_irq
|
|
.weak CCU80_SR2_irq
|
|
.weak CCU80_SR3_irq
|
|
.weak CCU81_SR0_irq
|
|
.weak CCU81_SR1_irq
|
|
.weak CCU81_SR2_irq
|
|
.weak CCU81_SR3_irq
|
|
.weak POSIF0_SR0_irq
|
|
.weak POSIF0_SR1_irq
|
|
.weak POSIF1_SR0_irq
|
|
.weak POSIF1_SR1_irq
|
|
.weak CAN_SR0_irq
|
|
.weak CAN_SR1_irq
|
|
.weak CAN_SR2_irq
|
|
.weak CAN_SR3_irq
|
|
.weak CAN_SR4_irq
|
|
.weak CAN_SR5_irq
|
|
.weak CAN_SR6_irq
|
|
.weak CAN_SR7_irq
|
|
.weak USIC0_SR0_irq
|
|
.weak USIC0_SR1_irq
|
|
.weak USIC0_SR2_irq
|
|
.weak USIC0_SR3_irq
|
|
.weak USIC0_SR4_irq
|
|
.weak USIC0_SR5_irq
|
|
.weak USIC1_SR0_irq
|
|
.weak USIC1_SR1_irq
|
|
.weak USIC1_SR2_irq
|
|
.weak USIC1_SR3_irq
|
|
.weak USIC1_SR4_irq
|
|
.weak USIC1_SR5_irq
|
|
.weak USIC2_SR0_irq
|
|
.weak USIC2_SR1_irq
|
|
.weak USIC2_SR2_irq
|
|
.weak USIC2_SR3_irq
|
|
.weak USIC2_SR4_irq
|
|
.weak USIC2_SR5_irq
|
|
.weak LEDTS0_SR0_irq
|
|
.weak FCE_SR0_irq
|
|
.weak GPDMA0_SR0_irq
|
|
.weak SDMMC_SR0_irq
|
|
.weak USB0_SR0_irq
|
|
.weak ETH0_SR0_irq
|
|
.weak GPDMA1_SR0_irq
|
|
|
|
.set NMI_interrupt, HaltProc
|
|
.set Hardfault_interrupt, HaltProc
|
|
.set MemManage_interrupt, HaltProc
|
|
.set BusFault_interrupt, HaltProc
|
|
.set UsageFault_interrupt, HaltProc
|
|
.set SWI_interrupt, HaltProc
|
|
.set DebugMonitor_interrupt, HaltProc
|
|
.set PendingSV_interrupt, HaltProc
|
|
.set SysTick_interrupt, HaltProc
|
|
|
|
.set SCU_SR0_irq, HaltProc
|
|
.set ERU0_SR0_irq, HaltProc
|
|
.set ERU0_SR1_irq, HaltProc
|
|
.set ERU0_SR2_irq, HaltProc
|
|
.set ERU0_SR3_irq, HaltProc
|
|
.set ERU1_SR0_irq, HaltProc
|
|
.set ERU1_SR1_irq, HaltProc
|
|
.set ERU1_SR2_irq, HaltProc
|
|
.set ERU1_SR3_irq, HaltProc
|
|
.set PMU0_SR0_irq, HaltProc
|
|
.set CADC_C0SR0_irq, HaltProc
|
|
.set CADC_C0SR1_irq, HaltProc
|
|
.set CADC_C0SR2_irq, HaltProc
|
|
.set CADC_C0SR3_irq, HaltProc
|
|
.set CADC_G0SR0_irq, HaltProc
|
|
.set CADC_G0SR1_irq, HaltProc
|
|
.set CADC_G0SR2_irq, HaltProc
|
|
.set CADC_G0SR3_irq, HaltProc
|
|
.set CADC_G1SR0_irq, HaltProc
|
|
.set CADC_G1SR1_irq, HaltProc
|
|
.set CADC_G1SR2_irq, HaltProc
|
|
.set CADC_G1SR3_irq, HaltProc
|
|
.set CADC_G2SR0_irq, HaltProc
|
|
.set CADC_G2SR1_irq, HaltProc
|
|
.set CADC_G2SR2_irq, HaltProc
|
|
.set CADC_G2SR3_irq, HaltProc
|
|
.set CADC_G3SR0_irq, HaltProc
|
|
.set CADC_G3SR1_irq, HaltProc
|
|
.set CADC_G3SR2_irq, HaltProc
|
|
.set CADC_G3SR3_irq, HaltProc
|
|
.set DSD_SRM0_irq, HaltProc
|
|
.set DSD_SRM1_irq, HaltProc
|
|
.set DSD_SRM2_irq, HaltProc
|
|
.set DSD_SRM3_irq, HaltProc
|
|
.set DSD_SRA0_irq, HaltProc
|
|
.set DSD_SRA1_irq, HaltProc
|
|
.set DSD_SRA2_irq, HaltProc
|
|
.set DSD_SRA3_irq, HaltProc
|
|
.set DAC_SR0_irq, HaltProc
|
|
.set DAC_SR1_irq, HaltProc
|
|
.set CCU40_SR0_irq, HaltProc
|
|
.set CCU40_SR1_irq, HaltProc
|
|
.set CCU40_SR2_irq, HaltProc
|
|
.set CCU40_SR3_irq, HaltProc
|
|
.set CCU41_SR0_irq, HaltProc
|
|
.set CCU41_SR1_irq, HaltProc
|
|
.set CCU41_SR2_irq, HaltProc
|
|
.set CCU41_SR3_irq, HaltProc
|
|
.set CCU42_SR0_irq, HaltProc
|
|
.set CCU42_SR1_irq, HaltProc
|
|
.set CCU42_SR2_irq, HaltProc
|
|
.set CCU42_SR3_irq, HaltProc
|
|
.set CCU43_SR0_irq, HaltProc
|
|
.set CCU43_SR1_irq, HaltProc
|
|
.set CCU43_SR2_irq, HaltProc
|
|
.set CCU43_SR3_irq, HaltProc
|
|
.set CCU80_SR0_irq, HaltProc
|
|
.set CCU80_SR1_irq, HaltProc
|
|
.set CCU80_SR2_irq, HaltProc
|
|
.set CCU80_SR3_irq, HaltProc
|
|
.set CCU81_SR0_irq, HaltProc
|
|
.set CCU81_SR1_irq, HaltProc
|
|
.set CCU81_SR2_irq, HaltProc
|
|
.set CCU81_SR3_irq, HaltProc
|
|
.set POSIF0_SR0_irq, HaltProc
|
|
.set POSIF0_SR1_irq, HaltProc
|
|
.set POSIF1_SR0_irq, HaltProc
|
|
.set POSIF1_SR1_irq, HaltProc
|
|
.set CAN_SR0_irq, HaltProc
|
|
.set CAN_SR1_irq, HaltProc
|
|
.set CAN_SR2_irq, HaltProc
|
|
.set CAN_SR3_irq, HaltProc
|
|
.set CAN_SR4_irq, HaltProc
|
|
.set CAN_SR5_irq, HaltProc
|
|
.set CAN_SR6_irq, HaltProc
|
|
.set CAN_SR7_irq, HaltProc
|
|
.set USIC0_SR0_irq, HaltProc
|
|
.set USIC0_SR1_irq, HaltProc
|
|
.set USIC0_SR2_irq, HaltProc
|
|
.set USIC0_SR3_irq, HaltProc
|
|
.set USIC0_SR4_irq, HaltProc
|
|
.set USIC0_SR5_irq, HaltProc
|
|
.set USIC1_SR0_irq, HaltProc
|
|
.set USIC1_SR1_irq, HaltProc
|
|
.set USIC1_SR2_irq, HaltProc
|
|
.set USIC1_SR3_irq, HaltProc
|
|
.set USIC1_SR4_irq, HaltProc
|
|
.set USIC1_SR5_irq, HaltProc
|
|
.set USIC2_SR0_irq, HaltProc
|
|
.set USIC2_SR1_irq, HaltProc
|
|
.set USIC2_SR2_irq, HaltProc
|
|
.set USIC2_SR3_irq, HaltProc
|
|
.set USIC2_SR4_irq, HaltProc
|
|
.set USIC2_SR5_irq, HaltProc
|
|
.set LEDTS0_SR0_irq, HaltProc
|
|
.set FCE_SR0_irq, HaltProc
|
|
.set GPDMA0_SR0_irq, HaltProc
|
|
.set SDMMC_SR0_irq, HaltProc
|
|
.set USB0_SR0_irq, HaltProc
|
|
.set ETH0_SR0_irq, HaltProc
|
|
.set GPDMA1_SR0_irq, HaltProc
|
|
|
|
.text
|
|
end;
|
|
|
|
end.
|