mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 04:08:04 +02:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
538 lines
21 KiB
ObjectPascal
538 lines
21 KiB
ObjectPascal
unit AT90PWM81;
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{$goto on}
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interface
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var
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// PORTB
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PORTB : byte absolute $00+$25; // Port B Data Register
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DDRB : byte absolute $00+$24; // Port B Data Direction Register
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PINB : byte absolute $00+$23; // Port B Input Pins
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// PORTD
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PORTD : byte absolute $00+$2B; // Port D Data Register
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DDRD : byte absolute $00+$2A; // Port D Data Direction Register
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PIND : byte absolute $00+$29; // Port D Input Pins
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// DA_CONVERTER
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DACH : byte absolute $00+$59; // DAC Data Register High Byte
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DACL : byte absolute $00+$58; // DAC Data Register Low Byte
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DACON : byte absolute $00+$76; // DAC Control Register
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// PORTE
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PORTE : byte absolute $00+$2E; // Port E Data Register
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DDRE : byte absolute $00+$2D; // Port E Data Direction Register
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PINE : byte absolute $00+$2C; // Port E Input Pins
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// SPI
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SPCR : byte absolute $00+$37; // SPI Control Register
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SPSR : byte absolute $00+$38; // SPI Status Register
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SPDR : byte absolute $00+$56; // SPI Data Register
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// WATCHDOG
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WDTCSR : byte absolute $00+$82; // Watchdog Timer Control Register
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$89; // External Interrupt Control Register A
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EIMSK : byte absolute $00+$41; // External Interrupt Mask Register
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EIFR : byte absolute $00+$40; // External Interrupt Flag Register
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// AD_CONVERTER
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ADMUX : byte absolute $00+$28; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$26; // The ADC Control and Status register
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ADC : word absolute $00+$4C; // ADC Data Register Bytes
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ADCL : byte absolute $00+$4C; // ADC Data Register Bytes
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ADCH : byte absolute $00+$4C+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$27; // ADC Control and Status Register B
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DIDR0 : byte absolute $00+$77; // Digital Input Disable Register 0
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DIDR1 : byte absolute $00+$78; // Digital Input Disable Register 0
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AMP0CSR : byte absolute $00+$79; //
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// ANALOG_COMPARATOR
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AC3CON : byte absolute $00+$7F; // Analog Comparator3 Control Register
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AC1CON : byte absolute $00+$7D; // Analog Comparator 1 Control Register
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AC2CON : byte absolute $00+$7E; // Analog Comparator 2 Control Register
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ACSR : byte absolute $00+$20; // Analog Comparator Status Register
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AC3ECON : byte absolute $00+$7C; //
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AC2ECON : byte absolute $00+$7B; //
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AC1ECON : byte absolute $00+$7A; //
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status Register
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OSCCAL : byte absolute $00+$88; // Oscillator Calibration Value
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CLKPR : byte absolute $00+$83; //
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SMCR : byte absolute $00+$53; // Sleep Mode Control Register
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GPIOR2 : byte absolute $00+$3B; // General Purpose IO Register 2
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GPIOR1 : byte absolute $00+$3A; // General Purpose IO Register 1
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GPIOR0 : byte absolute $00+$39; // General Purpose IO Register 0
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PLLCSR : byte absolute $00+$87; // PLL Control And Status Register
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PRR : byte absolute $00+$86; // Power Reduction Register
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CLKCSR : byte absolute $00+$84; //
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CLKSELR : byte absolute $00+$85; //
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BGCCR : byte absolute $00+$81; // BandGap Current Calibration Register
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BGCRR : byte absolute $00+$80; // BandGap Resistor Calibration Register
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// EEPROM
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EEAR : word absolute $00+$3E; // EEPROM Read/Write Access Bytes
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EEARL : byte absolute $00+$3E; // EEPROM Read/Write Access Bytes
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EEARH : byte absolute $00+$3E+1; // EEPROM Read/Write Access Bytes
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// PSC0
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PICR0 : word absolute $00+$68; // PSC 0 Input Capture Register
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PICR0L : byte absolute $00+$68; // PSC 0 Input Capture Register
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PICR0H : byte absolute $00+$68+1; // PSC 0 Input Capture Register
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PFRC0B : byte absolute $00+$63; // PSC 0 Input B Control
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PFRC0A : byte absolute $00+$62; // PSC 0 Input A Control
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PCTL0 : byte absolute $00+$32; // PSC 0 Control Register
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PCNF0 : byte absolute $00+$31; // PSC 0 Configuration Register
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OCR0RB : word absolute $00+$44; // Output Compare RB Register
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OCR0RBL : byte absolute $00+$44; // Output Compare RB Register
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OCR0RBH : byte absolute $00+$44+1; // Output Compare RB Register
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OCR0SB : word absolute $00+$42; // Output Compare SB Register
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OCR0SBL : byte absolute $00+$42; // Output Compare SB Register
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OCR0SBH : byte absolute $00+$42+1; // Output Compare SB Register
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OCR0RA : word absolute $00+$4A; // Output Compare RA Register
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OCR0RAL : byte absolute $00+$4A; // Output Compare RA Register
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OCR0RAH : byte absolute $00+$4A+1; // Output Compare RA Register
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OCR0SA : word absolute $00+$60; // Output Compare SA Register
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OCR0SAL : byte absolute $00+$60; // Output Compare SA Register
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OCR0SAH : byte absolute $00+$60+1; // Output Compare SA Register
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PSOC0 : byte absolute $00+$6A; // PSC0 Synchro and Output Configuration
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PIM0 : byte absolute $00+$2F; // PSC0 Interrupt Mask Register
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PIFR0 : byte absolute $00+$30; // PSC0 Interrupt Flag Register
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// PSC2
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PICR2H : byte absolute $00+$6D; // PSC 2 Input Capture Register High
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PICR2L : byte absolute $00+$6C; // PSC 2 Input Capture Register Low
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PFRC2B : byte absolute $00+$67; // PSC 2 Input B Control
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PFRC2A : byte absolute $00+$66; // PSC 2 Input B Control
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PCTL2 : byte absolute $00+$36; // PSC 2 Control Register
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PCNF2 : byte absolute $00+$35; // PSC 2 Configuration Register
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PCNFE2 : byte absolute $00+$70; // PSC 2 Enhanced Configuration Register
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OCR2RB : word absolute $00+$48; // Output Compare RB Register
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OCR2RBL : byte absolute $00+$48; // Output Compare RB Register
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OCR2RBH : byte absolute $00+$48+1; // Output Compare RB Register
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OCR2SB : word absolute $00+$46; // Output Compare SB Register
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OCR2SBL : byte absolute $00+$46; // Output Compare SB Register
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OCR2SBH : byte absolute $00+$46+1; // Output Compare SB Register
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OCR2RA : word absolute $00+$4E; // Output Compare RA Register
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OCR2RAL : byte absolute $00+$4E; // Output Compare RA Register
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OCR2RAH : byte absolute $00+$4E+1; // Output Compare RA Register
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OCR2SA : word absolute $00+$64; // Output Compare SA Register
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OCR2SAL : byte absolute $00+$64; // Output Compare SA Register
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OCR2SAH : byte absolute $00+$64+1; // Output Compare SA Register
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POM2 : byte absolute $00+$6F; // PSC 2 Output Matrix
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PSOC2 : byte absolute $00+$6E; // PSC2 Synchro and Output Configuration
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PIM2 : byte absolute $00+$33; // PSC2 Interrupt Mask Register
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PIFR2 : byte absolute $00+$34; // PSC2 Interrupt Flag Register
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PASDLY2 : byte absolute $00+$71; // Analog Synchronization Delay Register
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// TIMER_COUNTER_1
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TIMSK1 : byte absolute $00+$21; // Timer/Counter Interrupt Mask Register
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TIFR1 : byte absolute $00+$22; // Timer/Counter Interrupt Flag register
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TCCR1B : byte absolute $00+$8A; // Timer/Counter1 Control Register B
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TCNT1 : word absolute $00+$5A; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$5A; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$5A+1; // Timer/Counter1 Bytes
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ICR1 : word absolute $00+$8C; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$8C; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$8C+1; // Timer/Counter1 Input Capture Register Bytes
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// BOOT_LOAD
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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const
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// DACH
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// DACL
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// DACON
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DAATE = 7; // DAC Auto Trigger Enable Bit
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DATS = 4; // DAC Trigger Selection Bits
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DALA = 2; // DAC Left Adjust
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DAEN = 0; // DAC Enable Bit
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// WDTCSR
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WDIF = 7; // Watchdog Timeout Interrupt Flag
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WDIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// EICRA
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ISC2 = 4; // External Interrupt Sense Control Bit
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ISC1 = 2; // External Interrupt Sense Control Bit
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ISC0 = 0; // External Interrupt Sense Control Bit
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// EIMSK
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INT = 0; // External Interrupt Request 2 Enable
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// EIFR
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INTF = 0; // External Interrupt Flags
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADHSM = 7; // ADC High Speed Mode
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ADNCDIS = 6; // ADC Noise Canceller Disable
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ADSSEN = 4; // ADC Single Shot Enable on PSC's Synchronisation Signals
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR0
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ADC7D = 7; //
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ADC6D = 6; // ADC7 Digital input Disable
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ADC5D = 5; // ADC5 Digital input Disable
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ADC4D = 4; // ADC4 Digital input Disable
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ADC3D = 3; // ADC3 Digital input Disable
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ADC2D = 2; // ADC2 Digital input Disable
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ADC1D = 1; // ADC1 Digital input Disable
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ADC0D = 0; // ADC0 Digital input Disable
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// DIDR1
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ACMP1MD = 3; //
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AMP0POSD = 2; //
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ADC10D = 1; //
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ADC9D = 0; //
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// AMP0CSR
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AMP0EN = 7; //
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AMP0IS = 6; //
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AMP0G = 4; //
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AMP0GS = 3; //
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AMP0TS = 0; //
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// AC3CON
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AC3EN = 7; // Analog Comparator3 Enable Bit
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AC3IE = 6; // Analog Comparator 3 Interrupt Enable Bit
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AC3IS = 4; // Analog Comparator 3 Interrupt Select Bit
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AC3OEA = 3; // Analog Comparator 3 Alternate Output Enable
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AC3M = 0; // Analog Comparator 3 Multiplexer Register
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// AC1CON
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AC1EN = 7; // Analog Comparator 1 Enable Bit
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AC1IE = 6; // Analog Comparator 1 Interrupt Enable Bit
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AC1IS = 4; // Analog Comparator 1 Interrupt Select Bit
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AC1M = 0; // Analog Comparator 1 Multiplexer Register
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// AC2CON
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AC2EN = 7; // Analog Comparator 2 Enable Bit
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AC2IE = 6; // Analog Comparator 2 Interrupt Enable Bit
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AC2IS = 4; // Analog Comparator 2 Interrupt Select Bit
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AC2M = 0; // Analog Comparator 2 Multiplexer Register
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// ACSR
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AC3IF = 7; // Analog Comparator 3 Interrupt Flag Bit
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AC2IF = 6; // Analog Comparator 2 Interrupt Flag Bit
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AC1IF = 5; // Analog Comparator 1 Interrupt Flag Bit
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AC3O = 3; // Analog Comparator 3 Output Bit
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AC2O = 2; // Analog Comparator 2 Output Bit
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AC1O = 1; // Analog Comparator 1 Output Bit
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// AC3ECON
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AC3OI = 5; // Analog Comparator Ouput Invert
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AC3OE = 4; // Analog Comparator Ouput Enable
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AC3H = 0; // Analog Comparator Hysteresis Select
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// AC2ECON
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AC2OI = 5; // Analog Comparator Ouput Invert
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AC2OE = 4; // Analog Comparator Ouput Enable
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AC2H = 0; // Analog Comparator Hysteresis Select
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// AC1ECON
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AC1OI = 5; // Analog Comparator Ouput Invert
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AC1OE = 4; // Analog Comparator Ouput Enable
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AC1ICE = 3; // Analog Comparator Interrupt Capture Enable
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AC1H = 0; // Analog Comparator Hysteresis Select
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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PUD = 4; // Pull-up disable
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RSTDIS = 3; // Reset Pin Disable
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CKRC81 = 2; // Frequency Selection of the Calibrated RC Oscillator
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IVSEL = 1; // Interrupt Vector Select
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IVCE = 0; // Interrupt Vector Change Enable
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// CLKPR
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CLKPCE = 7; //
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CLKPS = 0; //
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// SMCR
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SM = 1; // Sleep Mode Select bits
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SE = 0; // Sleep Enable
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// GPIOR2
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GPIOR = 0; // General Purpose IO Register 2 bis
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// GPIOR1
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// GPIOR0
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GPIOR07 = 7; // General Purpose IO Register 0 bit 7
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GPIOR06 = 6; // General Purpose IO Register 0 bit 6
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GPIOR05 = 5; // General Purpose IO Register 0 bit 5
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GPIOR04 = 4; // General Purpose IO Register 0 bit 4
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GPIOR03 = 3; // General Purpose IO Register 0 bit 3
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GPIOR02 = 2; // General Purpose IO Register 0 bit 2
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GPIOR01 = 1; // General Purpose IO Register 0 bit 1
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GPIOR00 = 0; // General Purpose IO Register 0 bit 0
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// PLLCSR
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PLLF = 2; //
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PLLE = 1; // PLL Enable
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PLOCK = 0; // PLL Lock Detector
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// PRR
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PRPSC2 = 7; // Power Reduction PSC2
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PRPSCR = 5; // Power Reduction PSC0
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PRTIM1 = 4; // Power Reduction Timer/Counter1
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PRSPI = 2; // Power Reduction Serial Peripheral Interface
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PRADC = 0; // Power Reduction ADC
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// CLKCSR
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CLKCCE = 7; // Clock Control Change Enable
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CLKRDY = 4; // Clock Ready Flag
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CLKC = 0; // Clock Control
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// CLKSELR
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COUT = 6; // Clock OUT
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CSUT = 4; // Clock Start up Time
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CKSEL = 0; // Clock Source Select
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// BGCCR
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BGCC = 0; //
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// BGCRR
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BGCR = 0; //
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// EECR
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NVMBSY = 7; // None Volatile Busy Memory Busy
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EEPAGE = 6; // EEPROM Page Access
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EEPM = 4; // EEPROM Programming Mode
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMWE = 2; // EEPROM Master Write Enable
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EEWE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// PFRC0B
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PCAE0B = 7; // PSC 0 Capture Enable Input Part B
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PISEL0B = 6; // PSC 0 Input Select for Part B
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PELEV0B = 5; // PSC 0 Edge Level Selector on Input Part B
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PFLTE0B = 4; // PSC 0 Filter Enable on Input Part B
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PRFM0B = 0; // PSC 0 Retrigger and Fault Mode for Part B
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// PFRC0A
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PCAE0A = 7; // PSC 0 Capture Enable Input Part A
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PISEL0A = 6; // PSC 0 Input Select for Part A
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PELEV0A = 5; // PSC 0 Edge Level Selector on Input Part A
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PFLTE0A = 4; // PSC 0 Filter Enable on Input Part A
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PRFM0A = 0; // PSC 0 Retrigger and Fault Mode for Part A
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// PCTL0
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PPRE0 = 6; // PSC 0 Prescaler Selects
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PBFM0 = 2; // PSC 0 Balance Flank Width Modulation
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PAOC0B = 4; // PSC 0 Asynchronous Output Control B
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PAOC0A = 3; // PSC 0 Asynchronous Output Control A
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PCCYC0 = 1; // PSC0 Complete Cycle
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PRUN0 = 0; // PSC 0 Run
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// PCNF0
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PFIFTY0 = 7; // PSC 0 Fifty
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PALOCK0 = 6; // PSC 0 Autolock
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PLOCK0 = 5; // PSC 0 Lock
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PMODE0 = 3; // PSC 0 Mode
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POP0 = 2; // PSC 0 Output Polarity
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PCLKSEL0 = 1; // PSC 0 Input Clock Select
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// PSOC0
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PISEL0A1 = 7; // PSC Input Select
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PISEL0B1 = 6; // PSC Input Select
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PSYNC0 = 4; // Synchronisation out for ADC selection
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POEN0B = 2; // PSCOUT01 Output Enable
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POEN0A = 0; // PSCOUT00 Output Enable
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// PIM0
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PEVE0B = 4; // External Event B Interrupt Enable
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PEVE0A = 3; // External Event A Interrupt Enable
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PEOEPE0 = 1; // End of Enhanced Cycle Enable
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PEOPE0 = 0; // End of Cycle Interrupt Enable
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// PIFR0
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POAC0B = 7; // PSC 0 Output A Activity
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POAC0A = 6; // PSC 0 Output A Activity
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PEV0B = 4; // External Event B Interrupt
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PEV0A = 3; // External Event A Interrupt
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PRN0 = 1; // Ramp Number
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PEOP0 = 0; // End of PSC0 Interrupt
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// PICR2H
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PCST2 = 7; // PSC 2 Capture Software Trigger Bit
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PICR21 = 2; //
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PICR2 = 0; //
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// PFRC2B
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PCAE2B = 7; // PSC 2 Capture Enable Input Part B
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PISEL2B = 6; // PSC 2 Input Select for Part B
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PELEV2B = 5; // PSC 2 Edge Level Selector on Input Part B
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PFLTE2B = 4; // PSC 2 Filter Enable on Input Part B
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PRFM2B = 0; // PSC 2 Retrigger and Fault Mode for Part B
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// PFRC2A
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PCAE2A = 7; // PSC 2 Capture Enable Input Part A
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PISEL2A = 6; // PSC 2 Input Select for Part A
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PELEV2A = 5; // PSC 2 Edge Level Selector on Input Part A
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PFLTE2A = 4; // PSC 2 Filter Enable on Input Part A
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PRFM2A = 0; // PSC 2 Retrigger and Fault Mode for Part A
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// PCTL2
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PPRE2 = 6; // PSC 2 Prescaler Selects
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PBFM2 = 5; // Balance Flank Width Modulation
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PAOC2B = 4; // PSC 2 Asynchronous Output Control B
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PAOC2A = 3; // PSC 2 Asynchronous Output Control A
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PARUN2 = 2; // PSC2 Auto Run
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PCCYC2 = 1; // PSC2 Complete Cycle
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PRUN2 = 0; // PSC 2 Run
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// PCNF2
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PFIFTY2 = 7; // PSC 2 Fifty
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PALOCK2 = 6; // PSC 2 Autolock
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PLOCK2 = 5; // PSC 2 Lock
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PMODE2 = 3; // PSC 2 Mode
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POP2 = 2; // PSC 2 Output Polarity
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PCLKSEL2 = 1; // PSC 2 Input Clock Select
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POME2 = 0; // PSC 2 Output Matrix Enable
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// PCNFE2
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PASDLK2 = 5; //
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PBFM21 = 4; //
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PELEV2A1 = 3; //
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PELEV2B1 = 2; //
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PISEL2A1 = 1; //
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PISEL2B1 = 0; //
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// POM2
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POMV2B = 4; // Output Matrix Output B Ramps
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POMV2A = 0; // Output Matrix Output A Ramps
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// PSOC2
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POS2 = 6; // PSC 2 Output 23 Select
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PSYNC2 = 4; // Synchronization Out for ADC Selection
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POEN2D = 3; // PSCOUT23 Output Enable
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POEN2B = 2; // PSCOUT21 Output Enable
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POEN2C = 1; // PSCOUT22 Output Enable
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POEN2A = 0; // PSCOUT20 Output Enable
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// PIM2
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PSEIE2 = 5; // PSC 2 Synchro Error Interrupt Enable
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PEVE2B = 4; // External Event B Interrupt Enable
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PEVE2A = 3; // External Event A Interrupt Enable
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PEOEPE2 = 1; // End of Enhanced Cycle Interrupt Enable
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PEOPE2 = 0; // End of Cycle Interrupt Enable
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// PIFR2
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POAC2B = 7; // PSC 2 Output A Activity
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POAC2A = 6; // PSC 2 Output A Activity
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PSEI2 = 5; // PSC 2 Synchro Error Interrupt
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PEV2B = 4; // External Event B Interrupt
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PEV2A = 3; // External Event A Interrupt
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PRN2 = 1; // Ramp Number
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PEOP2 = 0; // End of PSC2 Interrupt
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// TIMSK1
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ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 5; // Input Capture Flag 1
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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WGM13 = 4; // Waveform Generation Mode
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CS1 = 0; // Prescaler source of Timer/Counter 1
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// SPMCSR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read While Write Section Busy
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SIGRD = 5; // Signature Row Read
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RWWSRE = 4; // Read While Write section read enable
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BLBSET = 3; // Boot Lock Bit Set
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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|
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procedure PSC2_CAPT_ISR; external name 'PSC2_CAPT_ISR'; // Interrupt 1 PSC2 Capture Event
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procedure PSC2_EC_ISR; external name 'PSC2_EC_ISR'; // Interrupt 2 PSC2 End Cycle
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procedure PSC2_EEC_ISR; external name 'PSC2_EEC_ISR'; // Interrupt 3 PSC2 End Of Enhanced Cycle
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procedure PSC0_CAPT_ISR; external name 'PSC0_CAPT_ISR'; // Interrupt 4 PSC0 Capture Event
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procedure PSC0_EC_ISR; external name 'PSC0_EC_ISR'; // Interrupt 5 PSC0 End Cycle
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procedure PSC0_EEC_ISR; external name 'PSC0_EEC_ISR'; // Interrupt 6 PSC0 End Of Enhanced Cycle
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procedure ANALOG_COMP_1_ISR; external name 'ANALOG_COMP_1_ISR'; // Interrupt 7 Analog Comparator 1
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procedure ANALOG_COMP_2_ISR; external name 'ANALOG_COMP_2_ISR'; // Interrupt 8 Analog Comparator 2
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procedure ANALOG_COMP_3_ISR; external name 'ANALOG_COMP_3_ISR'; // Interrupt 9 Analog Comparator 3
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 10 External Interrupt Request 0
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 12 Timer/Counter1 Overflow
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 13 ADC Conversion Complete
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 14 External Interrupt Request 1
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|
procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 15 SPI Serial Transfer Complet
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procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 16 External Interrupt Request 2
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 17 Watchdog Timeout Interrupt
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 18 EEPROM Ready
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procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 19 Store Program Memory Read
|
|
|
|
procedure _FPC_start; assembler; nostackframe;
|
|
label
|
|
_start;
|
|
asm
|
|
.init
|
|
.globl _start
|
|
|
|
rjmp _start
|
|
rjmp PSC2_CAPT_ISR
|
|
rjmp PSC2_EC_ISR
|
|
rjmp PSC2_EEC_ISR
|
|
rjmp PSC0_CAPT_ISR
|
|
rjmp PSC0_EC_ISR
|
|
rjmp PSC0_EEC_ISR
|
|
rjmp ANALOG_COMP_1_ISR
|
|
rjmp ANALOG_COMP_2_ISR
|
|
rjmp ANALOG_COMP_3_ISR
|
|
rjmp INT0_ISR
|
|
rjmp TIMER1_CAPT_ISR
|
|
rjmp TIMER1_OVF_ISR
|
|
rjmp ADC_ISR
|
|
rjmp INT1_ISR
|
|
rjmp SPI__STC_ISR
|
|
rjmp INT2_ISR
|
|
rjmp WDT_ISR
|
|
rjmp EE_READY_ISR
|
|
rjmp SPM_READY_ISR
|
|
|
|
{$i start.inc}
|
|
|
|
.weak PSC2_CAPT_ISR
|
|
.weak PSC2_EC_ISR
|
|
.weak PSC2_EEC_ISR
|
|
.weak PSC0_CAPT_ISR
|
|
.weak PSC0_EC_ISR
|
|
.weak PSC0_EEC_ISR
|
|
.weak ANALOG_COMP_1_ISR
|
|
.weak ANALOG_COMP_2_ISR
|
|
.weak ANALOG_COMP_3_ISR
|
|
.weak INT0_ISR
|
|
.weak TIMER1_CAPT_ISR
|
|
.weak TIMER1_OVF_ISR
|
|
.weak ADC_ISR
|
|
.weak INT1_ISR
|
|
.weak SPI__STC_ISR
|
|
.weak INT2_ISR
|
|
.weak WDT_ISR
|
|
.weak EE_READY_ISR
|
|
.weak SPM_READY_ISR
|
|
|
|
.set PSC2_CAPT_ISR, Default_IRQ_handler
|
|
.set PSC2_EC_ISR, Default_IRQ_handler
|
|
.set PSC2_EEC_ISR, Default_IRQ_handler
|
|
.set PSC0_CAPT_ISR, Default_IRQ_handler
|
|
.set PSC0_EC_ISR, Default_IRQ_handler
|
|
.set PSC0_EEC_ISR, Default_IRQ_handler
|
|
.set ANALOG_COMP_1_ISR, Default_IRQ_handler
|
|
.set ANALOG_COMP_2_ISR, Default_IRQ_handler
|
|
.set ANALOG_COMP_3_ISR, Default_IRQ_handler
|
|
.set INT0_ISR, Default_IRQ_handler
|
|
.set TIMER1_CAPT_ISR, Default_IRQ_handler
|
|
.set TIMER1_OVF_ISR, Default_IRQ_handler
|
|
.set ADC_ISR, Default_IRQ_handler
|
|
.set INT1_ISR, Default_IRQ_handler
|
|
.set SPI__STC_ISR, Default_IRQ_handler
|
|
.set INT2_ISR, Default_IRQ_handler
|
|
.set WDT_ISR, Default_IRQ_handler
|
|
.set EE_READY_ISR, Default_IRQ_handler
|
|
.set SPM_READY_ISR, Default_IRQ_handler
|
|
end;
|
|
|
|
end.
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