mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 04:08:04 +02:00
a124adb9a7
git-svn-id: trunk@44128 -
(cherry picked from commit 5040e31f11)
# Conflicts:
# .gitattributes
842 lines
32 KiB
ObjectPascal
842 lines
32 KiB
ObjectPascal
unit ATmega324PB;
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{$goto on}
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interface
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var
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PINA: byte absolute $20; // Port A Input Pins
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DDRA: byte absolute $21; // Port A Data Direction Register
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PORTA: byte absolute $22; // Port A Data Register
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PINB: byte absolute $23; // Port B Input Pins
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DDRB: byte absolute $24; // Port B Data Direction Register
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PORTB: byte absolute $25; // Port B Data Register
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PINC: byte absolute $26; // Port C Input Pins
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DDRC: byte absolute $27; // Port C Data Direction Register
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PORTC: byte absolute $28; // Port C Data Register
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PIND: byte absolute $29; // Port D Input Pins
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DDRD: byte absolute $2A; // Port D Data Direction Register
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PORTD: byte absolute $2B; // Port D Data Register
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PINE: byte absolute $2C; // Port E Input Pins
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DDRE: byte absolute $2D; // Port E Data Direction Register
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PORTE: byte absolute $2E; // Port E Data Register
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TIFR0: byte absolute $35; // Timer/Counter0 Interrupt Flag register
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TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
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TIFR2: byte absolute $37; // Timer/Counter Interrupt Flag Register
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TIFR3: byte absolute $38; // Timer/Counter Interrupt Flag register
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TIFR4: byte absolute $39; // Timer/Counter Interrupt Flag register
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PCIFR: byte absolute $3B; // Pin Change Interrupt Flag Register
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EIFR: byte absolute $3C; // External Interrupt Flag Register
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EIMSK: byte absolute $3D; // External Interrupt Mask Register
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GPIOR0: byte absolute $3E; // General Purpose IO Register 0
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EECR: byte absolute $3F; // EEPROM Control Register
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EEDR: byte absolute $40; // EEPROM Data Register
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EEAR: word absolute $41; // EEPROM Address Register Low Bytes
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EEARL: byte absolute $41; // EEPROM Address Register Low Bytes
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EEARH: byte absolute $42; // EEPROM Address Register Low Bytes;
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GTCCR: byte absolute $43; // General Timer/Counter Control Register
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TCCR0A: byte absolute $44; // Timer/Counter0 Control Register A
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TCCR0B: byte absolute $45; // Timer/Counter0 Control Register B
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TCNT0: byte absolute $46; // Timer/Counter0
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OCR0A: byte absolute $47; // Timer/Counter0 Output Compare Register
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OCR0B: byte absolute $48; // Timer/Counter0 Output Compare Register
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GPIOR1: byte absolute $4A; // General Purpose IO Register 1
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GPIOR2: byte absolute $4B; // General Purpose IO Register 2
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SPCR0: byte absolute $4C; // SPI Control Register
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SPSR0: byte absolute $4D; // SPI Status Register
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SPDR0: byte absolute $4E; // SPI Data Register
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ACSRB: byte absolute $4F; // Analog Comparator Control And Status Register B
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ACSR: byte absolute $50; // Analog Comparator Control And Status Register
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OCDR: byte absolute $51; // On-Chip Debug Related Register in I/O Memory
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SMCR: byte absolute $53; // Sleep Mode Control Register
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MCUSR: byte absolute $54; // MCU Status Register
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MCUCR: byte absolute $55; // MCU Control Register
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SPMCSR: byte absolute $57; // Store Program Memory Control Register
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SP: word absolute $5D; // Stack Pointer
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SPL: byte absolute $5D; // Stack Pointer
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SPH: byte absolute $5E; // Stack Pointer ;
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SREG: byte absolute $5F; // Status Register
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WDTCSR: byte absolute $60; // Watchdog Timer Control Register
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CLKPR: byte absolute $61;
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XFDCSR: byte absolute $62; // XOSC Failure Detection Control and Status Register
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PRR2: byte absolute $63; // Power Reduction Register2
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PRR0: byte absolute $64; // Power Reduction Register0
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PRR1: byte absolute $65; // Power Reduction Register1
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OSCCAL: byte absolute $66; // Oscillator Calibration Value
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PCICR: byte absolute $68; // Pin Change Interrupt Control Register
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EICRA: byte absolute $69; // External Interrupt Control Register A
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PCMSK0: byte absolute $6B; // Pin Change Mask Register 0
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PCMSK1: byte absolute $6C; // Pin Change Mask Register 1
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PCMSK2: byte absolute $6D; // Pin Change Mask Register 2
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TIMSK0: byte absolute $6E; // Timer/Counter0 Interrupt Mask Register
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TIMSK1: byte absolute $6F; // Timer/Counter1 Interrupt Mask Register
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TIMSK2: byte absolute $70; // Timer/Counter Interrupt Mask register
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TIMSK3: byte absolute $71; // Timer/Counter3 Interrupt Mask Register
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TIMSK4: byte absolute $72; // Timer/Counter4 Interrupt Mask Register
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PCMSK3: byte absolute $73; // Pin Change Mask Register 3
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PCMSK4: byte absolute $75; // Pin Change Mask Register 4
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ADC: word absolute $78; // ADC Data Register Bytes
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ADCL: byte absolute $78; // ADC Data Register Bytes
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ADCH: byte absolute $79; // ADC Data Register Bytes;
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ADCSRA: byte absolute $7A; // ADC Control and Status register A
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ADCSRB: byte absolute $7B; // ADC Control and Status register B
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ADMUX: byte absolute $7C; // ADC multiplexer Selection Register
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DIDR0: byte absolute $7E; // Digital Input Disable Register
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DIDR1: byte absolute $7F; // Digital Input Disable Register 1
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TCCR1A: byte absolute $80; // Timer/Counter1 Control Register A
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TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
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TCCR1C: byte absolute $82; // Timer/Counter1 Control Register C
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TCNT1: word absolute $84; // Timer/Counter1 Bytes
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TCNT1L: byte absolute $84; // Timer/Counter1 Bytes
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TCNT1H: byte absolute $85; // Timer/Counter1 Bytes;
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ICR1: word absolute $86; // Timer/Counter1 Input Capture Register Bytes
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ICR1L: byte absolute $86; // Timer/Counter1 Input Capture Register Bytes
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ICR1H: byte absolute $87; // Timer/Counter1 Input Capture Register Bytes;
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OCR1A: word absolute $88; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AL: byte absolute $88; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AH: byte absolute $89; // Timer/Counter1 Output Compare Register A Bytes;
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OCR1B: word absolute $8A; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BL: byte absolute $8A; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BH: byte absolute $8B; // Timer/Counter1 Output Compare Register B Bytes;
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TCCR3A: byte absolute $90; // Timer/Counter3 Control Register A
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TCCR3B: byte absolute $91; // Timer/Counter3 Control Register B
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TCCR3C: byte absolute $92; // Timer/Counter3 Control Register C
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TCNT3: word absolute $94; // Timer/Counter3 Bytes
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TCNT3L: byte absolute $94; // Timer/Counter3 Bytes
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TCNT3H: byte absolute $95; // Timer/Counter3 Bytes;
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ICR3: word absolute $96; // Timer/Counter3 Input Capture Register Bytes
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ICR3L: byte absolute $96; // Timer/Counter3 Input Capture Register Bytes
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ICR3H: byte absolute $97; // Timer/Counter3 Input Capture Register Bytes;
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OCR3A: word absolute $98; // Timer/Counter3 Output Compare Register A Bytes
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OCR3AL: byte absolute $98; // Timer/Counter3 Output Compare Register A Bytes
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OCR3AH: byte absolute $99; // Timer/Counter3 Output Compare Register A Bytes;
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OCR3B: word absolute $9A; // Timer/Counter3 Output Compare Register B Bytes
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OCR3BL: byte absolute $9A; // Timer/Counter3 Output Compare Register B Bytes
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OCR3BH: byte absolute $9B; // Timer/Counter3 Output Compare Register B Bytes;
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TCCR4A: byte absolute $A0; // Timer/Counter4 Control Register A
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TCCR4B: byte absolute $A1; // Timer/Counter4 Control Register B
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TCCR4C: byte absolute $A2; // Timer/Counter4 Control Register C
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TCNT4: word absolute $A4; // Timer/Counter4 Bytes
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TCNT4L: byte absolute $A4; // Timer/Counter4 Bytes
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TCNT4H: byte absolute $A5; // Timer/Counter4 Bytes;
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ICR4: word absolute $A6; // Timer/Counter4 Input Capture Register Bytes
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ICR4L: byte absolute $A6; // Timer/Counter4 Input Capture Register Bytes
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ICR4H: byte absolute $A7; // Timer/Counter4 Input Capture Register Bytes;
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OCR4A: word absolute $A8; // Timer/Counter4 Output Compare Register A Bytes
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OCR4AL: byte absolute $A8; // Timer/Counter4 Output Compare Register A Bytes
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OCR4AH: byte absolute $A9; // Timer/Counter4 Output Compare Register A Bytes;
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OCR4B: word absolute $AA; // Timer/Counter4 Output Compare Register B Bytes
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OCR4BL: byte absolute $AA; // Timer/Counter4 Output Compare Register B Bytes
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OCR4BH: byte absolute $AB; // Timer/Counter4 Output Compare Register B Bytes;
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SPCR1: byte absolute $AC; // SPI Control Register
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SPSR1: byte absolute $AD; // SPI Status Register
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SPDR1: byte absolute $AE; // SPI Data Register
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TCCR2A: byte absolute $B0; // Timer/Counter2 Control Register A
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TCCR2B: byte absolute $B1; // Timer/Counter2 Control Register B
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TCNT2: byte absolute $B2; // Timer/Counter2
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OCR2A: byte absolute $B3; // Timer/Counter2 Output Compare Register A
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OCR2B: byte absolute $B4; // Timer/Counter2 Output Compare Register B
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ASSR: byte absolute $B6; // Asynchronous Status Register
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TWBR0: byte absolute $B8; // TWI Bit Rate register
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TWSR0: byte absolute $B9; // TWI Status Register
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TWAR0: byte absolute $BA; // TWI (Slave) Address register
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TWDR0: byte absolute $BB; // TWI Data register
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TWCR0: byte absolute $BC; // TWI Control Register
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TWAMR0: byte absolute $BD; // TWI (Slave) Address Mask Register
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UCSR0A: byte absolute $C0; // USART Control and Status Register A
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UCSR0B: byte absolute $C1; // USART Control and Status Register B
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UCSR0C: byte absolute $C2; // USART Control and Status Register C
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UCSR0D: byte absolute $C3; // USART Control and Status Register D
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UBRR0: word absolute $C4; // USART Baud Rate Register Bytes
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UBRR0L: byte absolute $C4; // USART Baud Rate Register Bytes
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UBRR0H: byte absolute $C5; // USART Baud Rate Register Bytes;
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UDR0: byte absolute $C6; // USART I/O Data Register
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UCSR1A: byte absolute $C8; // USART Control and Status Register A
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UCSR1B: byte absolute $C9; // USART Control and Status Register B
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UCSR1C: byte absolute $CA; // USART Control and Status Register C
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UCSR1D: byte absolute $CB; // USART Control and Status Register D
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UBRR1: word absolute $CC; // USART Baud Rate Register Bytes
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UBRR1L: byte absolute $CC; // USART Baud Rate Register Bytes
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UBRR1H: byte absolute $CD; // USART Baud Rate Register Bytes;
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UDR1: byte absolute $CE; // USART I/O Data Register
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UCSR2A: byte absolute $D0; // USART Control and Status Register A
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UCSR2B: byte absolute $D1; // USART Control and Status Register B
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UCSR2C: byte absolute $D2; // USART Control and Status Register C
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UCSR2D: byte absolute $D3; // USART Control and Status Register D
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UBRR2: word absolute $D4; // USART Baud Rate Register Bytes
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UBRR2L: byte absolute $D4; // USART Baud Rate Register Bytes
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UBRR2H: byte absolute $D5; // USART Baud Rate Register Bytes;
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UDR2: byte absolute $D6; // USART I/O Data Register
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TWBR1: byte absolute $D8; // TWI Bit Rate register
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TWSR1: byte absolute $D9; // TWI Status Register
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TWAR1: byte absolute $DA; // TWI (Slave) Address register
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TWDR1: byte absolute $DB; // TWI Data register
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TWCR1: byte absolute $DC; // TWI Control Register
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TWAMR1: byte absolute $DD; // TWI (Slave) Address Mask Register
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const
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// Port A Data Register
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PA0 = $00;
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PA1 = $01;
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PA2 = $02;
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PA3 = $03;
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PA4 = $04;
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PA5 = $05;
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PA6 = $06;
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PA7 = $07;
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// Port B Data Register
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PB0 = $00;
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PB1 = $01;
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PB2 = $02;
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PB3 = $03;
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PB4 = $04;
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PB5 = $05;
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PB6 = $06;
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PB7 = $07;
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// Port C Data Register
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PC0 = $00;
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PC1 = $01;
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PC2 = $02;
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PC3 = $03;
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PC4 = $04;
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PC5 = $05;
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PC6 = $06;
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PC7 = $07;
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// Port D Data Register
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PD0 = $00;
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PD1 = $01;
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PD2 = $02;
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PD3 = $03;
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PD4 = $04;
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PD5 = $05;
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PD6 = $06;
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PD7 = $07;
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// Port E Data Register
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PE0 = $00;
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PE1 = $01;
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PE2 = $02;
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PE3 = $03;
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PE4 = $04;
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PE5 = $05;
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PE6 = $06;
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// Timer/Counter0 Interrupt Flag register
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TOV0 = $00;
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OCF0A = $01;
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OCF0B = $02;
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// Timer/Counter Interrupt Flag register
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TOV1 = $00;
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OCF1A = $01;
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OCF1B = $02;
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ICF1 = $05;
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// Timer/Counter Interrupt Flag Register
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TOV2 = $00;
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OCF2A = $01;
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OCF2B = $02;
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// Timer/Counter Interrupt Flag register
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TOV3 = $00;
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OCF3A = $01;
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OCF3B = $02;
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ICF3 = $05;
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// Timer/Counter Interrupt Flag register
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TOV4 = $00;
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OCF4A = $01;
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OCF4B = $02;
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ICF4 = $05;
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// Pin Change Interrupt Flag Register
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PCIF0 = $00; // Pin Change Interrupt Flags
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PCIF1 = $01; // Pin Change Interrupt Flags
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PCIF2 = $02; // Pin Change Interrupt Flags
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PCIF3 = $03; // Pin Change Interrupt Flags
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PCIF4 = $04; // Pin Change Interrupt Flags
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// External Interrupt Flag Register
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INTF0 = $00; // External Interrupt Flags
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INTF1 = $01; // External Interrupt Flags
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INTF2 = $02; // External Interrupt Flags
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// External Interrupt Mask Register
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INT0 = $00; // External Interrupt Request Enable
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INT1 = $01; // External Interrupt Request Enable
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INT2 = $02; // External Interrupt Request Enable
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// EEPROM Control Register
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EERE = $00;
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EEPE = $01;
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EEMPE = $02;
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EERIE = $03;
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EEPM0 = $04; // EEPROM Programming Mode Bits
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EEPM1 = $05; // EEPROM Programming Mode Bits
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// General Timer/Counter Control Register
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PSRSYNC = $00;
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PSRASY = $01;
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TSM = $07;
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// Timer/Counter0 Control Register A
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WGM00 = $00; // Waveform Generation Mode
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WGM01 = $01; // Waveform Generation Mode
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COM0B0 = $04; // Compare Match Output B Mode
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COM0B1 = $05; // Compare Match Output B Mode
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COM0A0 = $06; // Compare Match Output A Mode
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COM0A1 = $07; // Compare Match Output A Mode
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// Timer/Counter0 Control Register B
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CS00 = $00; // Clock Select
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CS01 = $01; // Clock Select
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CS02 = $02; // Clock Select
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WGM02 = $03;
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FOC0B = $06;
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FOC0A = $07;
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// SPI Control Register
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SPR0 = $00; // SPI Clock Rate Select
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SPR1 = $01; // SPI Clock Rate Select
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CPHA = $02;
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CPOL = $03;
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MSTR = $04;
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DORD = $05;
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SPE = $06;
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SPIE = $07;
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// SPI Status Register
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SPI2X = $00;
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WCOL = $06;
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SPIF = $07;
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// Analog Comparator Control And Status Register B
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ACOE = $00;
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// Analog Comparator Control And Status Register
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ACIS0 = $00; // Analog Comparator Interrupt Mode Select bits
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ACIS1 = $01; // Analog Comparator Interrupt Mode Select bits
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ACIC = $02;
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ACIE = $03;
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ACI = $04;
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ACO = $05;
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ACBG = $06;
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ACD = $07;
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// Sleep Mode Control Register
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SE = $00;
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SM0 = $01; // Sleep Mode Select bits
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SM1 = $02; // Sleep Mode Select bits
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SM2 = $03; // Sleep Mode Select bits
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// MCU Status Register
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PORF = $00;
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EXTRF = $01;
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BORF = $02;
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WDRF = $03;
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JTRF = $04;
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// MCU Control Register
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IVCE = $00;
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IVSEL = $01;
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PUD = $04;
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BODSE = $05;
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BODS = $06;
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JTD = $07;
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// Store Program Memory Control Register
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SPMEN = $00;
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PGERS = $01;
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PGWRT = $02;
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BLBSET = $03;
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RWWSRE = $04;
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SIGRD = $05;
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RWWSB = $06;
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SPMIE = $07;
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// Status Register
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C = $00;
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Z = $01;
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N = $02;
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V = $03;
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S = $04;
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H = $05;
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T = $06;
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I = $07;
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// Watchdog Timer Control Register
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WDE = $03;
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WDCE = $04;
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WDP0 = $00; // Watchdog Timer Prescaler Bits
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WDP1 = $01; // Watchdog Timer Prescaler Bits
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WDP2 = $02; // Watchdog Timer Prescaler Bits
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WDP3 = $05; // Watchdog Timer Prescaler Bits
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WDIE = $06;
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WDIF = $07;
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CLKPS0 = $00;
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CLKPS1 = $01;
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CLKPS2 = $02;
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CLKPS3 = $03;
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CLKPCE = $07;
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// XOSC Failure Detection Control and Status Register
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XFDIE = $00;
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XFDIF = $01;
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// Power Reduction Register2
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PRTWI1 = $00;
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PRSPI1 = $01;
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PRUSART2 = $02;
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PRPTC = $03;
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// Power Reduction Register0
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PRADC = $00;
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PRUSART0 = $01;
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PRSPI0 = $02;
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PRTIM1 = $03;
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PRUSART1 = $04;
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PRTIM0 = $05;
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PRTIM2 = $06;
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PRTWI0 = $07;
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// Power Reduction Register1
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PRTIM3 = $00;
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PRTIM4 = $01;
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// Oscillator Calibration Value
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OSCCAL0 = $00; // Oscillator Calibration
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OSCCAL1 = $01; // Oscillator Calibration
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OSCCAL2 = $02; // Oscillator Calibration
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OSCCAL3 = $03; // Oscillator Calibration
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OSCCAL4 = $04; // Oscillator Calibration
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OSCCAL5 = $05; // Oscillator Calibration
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OSCCAL6 = $06; // Oscillator Calibration
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OSCCAL7 = $07; // Oscillator Calibration
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// Pin Change Interrupt Control Register
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PCIE0 = $00; // Pin Change Interrupt Enables
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PCIE1 = $01; // Pin Change Interrupt Enables
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PCIE2 = $02; // Pin Change Interrupt Enables
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PCIE3 = $03; // Pin Change Interrupt Enables
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PCIE4 = $04; // Pin Change Interrupt Enables
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// External Interrupt Control Register A
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ISC00 = $00; // External Interrupt Sense Control Bit
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ISC01 = $01; // External Interrupt Sense Control Bit
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ISC10 = $02; // External Interrupt Sense Control Bit
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ISC11 = $03; // External Interrupt Sense Control Bit
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ISC20 = $04; // External Interrupt Sense Control Bit
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ISC21 = $05; // External Interrupt Sense Control Bit
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// Timer/Counter0 Interrupt Mask Register
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TOIE0 = $00;
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OCIE0A = $01;
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OCIE0B = $02;
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// Timer/Counter1 Interrupt Mask Register
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TOIE1 = $00;
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OCIE1A = $01;
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OCIE1B = $02;
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ICIE1 = $05;
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// Timer/Counter Interrupt Mask register
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TOIE2 = $00;
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OCIE2A = $01;
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OCIE2B = $02;
|
|
// Timer/Counter3 Interrupt Mask Register
|
|
TOIE3 = $00;
|
|
OCIE3A = $01;
|
|
OCIE3B = $02;
|
|
ICIE3 = $05;
|
|
// Timer/Counter4 Interrupt Mask Register
|
|
TOIE4 = $00;
|
|
OCIE4A = $01;
|
|
OCIE4B = $02;
|
|
ICIE4 = $05;
|
|
// Pin Change Mask Register 4
|
|
PCINT32 = $00; // Pin Change Enable Masks
|
|
PCINT33 = $01; // Pin Change Enable Masks
|
|
PCINT34 = $02; // Pin Change Enable Masks
|
|
PCINT35 = $03; // Pin Change Enable Masks
|
|
PCINT36 = $04; // Pin Change Enable Masks
|
|
PCINT37 = $05; // Pin Change Enable Masks
|
|
PCINT38 = $06; // Pin Change Enable Masks
|
|
// ADC Control and Status register A
|
|
ADPS0 = $00; // ADC Prescaler Select Bits
|
|
ADPS1 = $01; // ADC Prescaler Select Bits
|
|
ADPS2 = $02; // ADC Prescaler Select Bits
|
|
ADIE = $03;
|
|
ADIF = $04;
|
|
ADATE = $05;
|
|
ADSC = $06;
|
|
ADEN = $07;
|
|
// ADC Control and Status register B
|
|
ADTS0 = $00; // ADC Auto Trigger Source bits
|
|
ADTS1 = $01; // ADC Auto Trigger Source bits
|
|
ADTS2 = $02; // ADC Auto Trigger Source bits
|
|
ACME = $06;
|
|
GPIOEN = $07;
|
|
// ADC multiplexer Selection Register
|
|
MUX0 = $00; // Analog Channel and Gain Selection Bits
|
|
MUX1 = $01; // Analog Channel and Gain Selection Bits
|
|
MUX2 = $02; // Analog Channel and Gain Selection Bits
|
|
MUX3 = $03; // Analog Channel and Gain Selection Bits
|
|
MUX4 = $04; // Analog Channel and Gain Selection Bits
|
|
ADLAR = $05;
|
|
REFS0 = $06; // Reference Selection Bits
|
|
REFS1 = $07; // Reference Selection Bits
|
|
// Digital Input Disable Register
|
|
ADC0D = $00;
|
|
ADC1D = $01;
|
|
ADC2D = $02;
|
|
ADC3D = $03;
|
|
ADC4D = $04;
|
|
ADC5D = $05;
|
|
ADC6D = $06;
|
|
ADC7D = $07;
|
|
// Digital Input Disable Register 1
|
|
AIN0D = $00;
|
|
AIN1D = $01;
|
|
// Timer/Counter1 Control Register A
|
|
WGM10 = $00; // Pulse Width Modulator Select Bits
|
|
WGM11 = $01; // Pulse Width Modulator Select Bits
|
|
COM1B0 = $04; // Compare Output Mode 1B, bits
|
|
COM1B1 = $05; // Compare Output Mode 1B, bits
|
|
COM1A0 = $06; // Compare Output Mode 1A, bits
|
|
COM1A1 = $07; // Compare Output Mode 1A, bits
|
|
// Timer/Counter1 Control Register B
|
|
CS10 = $00; // Clock Select1 bits
|
|
CS11 = $01; // Clock Select1 bits
|
|
CS12 = $02; // Clock Select1 bits
|
|
ICES1 = $06;
|
|
ICNC1 = $07;
|
|
// Timer/Counter1 Control Register C
|
|
FOC1B = $06;
|
|
FOC1A = $07;
|
|
// Timer/Counter3 Control Register A
|
|
WGM30 = $00; // Pulse Width Modulator Select Bits
|
|
WGM31 = $01; // Pulse Width Modulator Select Bits
|
|
COM3B0 = $04; // Compare Output Mode 3B, bits
|
|
COM3B1 = $05; // Compare Output Mode 3B, bits
|
|
COM3A0 = $06; // Compare Output Mode 3A, bits
|
|
COM3A1 = $07; // Compare Output Mode 3A, bits
|
|
// Timer/Counter3 Control Register B
|
|
CS30 = $00; // Clock Select3 bits
|
|
CS31 = $01; // Clock Select3 bits
|
|
CS32 = $02; // Clock Select3 bits
|
|
ICES3 = $06;
|
|
ICNC3 = $07;
|
|
// Timer/Counter3 Control Register C
|
|
FOC3B = $06;
|
|
FOC3A = $07;
|
|
// Timer/Counter4 Control Register A
|
|
WGM40 = $00; // Pulse Width Modulator Select Bits
|
|
WGM41 = $01; // Pulse Width Modulator Select Bits
|
|
COM4B0 = $04; // Compare Output Mode 4B, bits
|
|
COM4B1 = $05; // Compare Output Mode 4B, bits
|
|
COM4A0 = $06; // Compare Output Mode 4A, bits
|
|
COM4A1 = $07; // Compare Output Mode 4A, bits
|
|
// Timer/Counter4 Control Register B
|
|
CS40 = $00; // Clock Select4 bits
|
|
CS41 = $01; // Clock Select4 bits
|
|
CS42 = $02; // Clock Select4 bits
|
|
ICES4 = $06;
|
|
ICNC4 = $07;
|
|
// Timer/Counter4 Control Register C
|
|
FOC4B = $06;
|
|
FOC4A = $07;
|
|
// Timer/Counter2 Control Register A
|
|
WGM20 = $00; // Waveform Genration Mode
|
|
WGM21 = $01; // Waveform Genration Mode
|
|
COM2B0 = $04; // Compare Output Mode 2B bits
|
|
COM2B1 = $05; // Compare Output Mode 2B bits
|
|
COM2A0 = $06; // Compare Output Mode 2A bits
|
|
COM2A1 = $07; // Compare Output Mode 2A bits
|
|
// Timer/Counter2 Control Register B
|
|
CS20 = $00; // Clock Select bits
|
|
CS21 = $01; // Clock Select bits
|
|
CS22 = $02; // Clock Select bits
|
|
WGM22 = $03;
|
|
FOC2B = $06;
|
|
FOC2A = $07;
|
|
// Asynchronous Status Register
|
|
TCR2BUB = $00;
|
|
TCR2AUB = $01;
|
|
OCR2BUB = $02;
|
|
OCR2AUB = $03;
|
|
TCN2UB = $04;
|
|
AS2 = $05;
|
|
EXCLK = $06;
|
|
// TWI Status Register
|
|
TWPS0 = $00; // TWI Prescaler
|
|
TWPS1 = $01; // TWI Prescaler
|
|
TWS03 = $03; // TWI Status
|
|
TWS04 = $04; // TWI Status
|
|
TWS05 = $05; // TWI Status
|
|
TWS06 = $06; // TWI Status
|
|
TWS07 = $07; // TWI Status
|
|
// TWI (Slave) Address register
|
|
TWGCE = $00;
|
|
TWA0 = $01; // TWI (Slave) Address register Bits
|
|
TWA1 = $02; // TWI (Slave) Address register Bits
|
|
TWA2 = $03; // TWI (Slave) Address register Bits
|
|
TWA3 = $04; // TWI (Slave) Address register Bits
|
|
TWA4 = $05; // TWI (Slave) Address register Bits
|
|
TWA5 = $06; // TWI (Slave) Address register Bits
|
|
TWA6 = $07; // TWI (Slave) Address register Bits
|
|
// TWI Control Register
|
|
TWIE = $00;
|
|
TWEN = $02;
|
|
TWWC = $03;
|
|
TWSTO = $04;
|
|
TWSTA = $05;
|
|
TWEA = $06;
|
|
TWINT = $07;
|
|
// TWI (Slave) Address Mask Register
|
|
TWAM00 = $01;
|
|
TWAM01 = $02;
|
|
TWAM02 = $03;
|
|
TWAM03 = $04;
|
|
TWAM04 = $05;
|
|
TWAM05 = $06;
|
|
TWAM06 = $07;
|
|
// USART Control and Status Register A
|
|
MPCM = $00;
|
|
U2X = $01;
|
|
UPE = $02;
|
|
DOR = $03;
|
|
FE = $04;
|
|
UDRE = $05;
|
|
TXC = $06;
|
|
RXC = $07;
|
|
// USART Control and Status Register B
|
|
TXB8 = $00;
|
|
RXB8 = $01;
|
|
UCSZ2 = $02;
|
|
TXEN = $03;
|
|
RXEN = $04;
|
|
UDRIE = $05;
|
|
TXCIE = $06;
|
|
RXCIE = $07;
|
|
// USART Control and Status Register C
|
|
UCPOL = $00;
|
|
UCSZ0 = $01; // Character Size
|
|
UCSZ1 = $02; // Character Size
|
|
USBS = $03;
|
|
UPM0 = $04; // Parity Mode Bits
|
|
UPM1 = $05; // Parity Mode Bits
|
|
UMSEL0 = $06; // USART Mode Select
|
|
UMSEL1 = $07; // USART Mode Select
|
|
// USART Control and Status Register D
|
|
SFDE = $05;
|
|
RXS = $06;
|
|
RXSIE = $07;
|
|
// TWI (Slave) Address Mask Register
|
|
TWAM10 = $01;
|
|
TWAM11 = $02;
|
|
TWAM12 = $03;
|
|
TWAM13 = $04;
|
|
TWAM14 = $05;
|
|
TWAM15 = $06;
|
|
TWAM16 = $07;
|
|
|
|
|
|
implementation
|
|
|
|
{$i avrcommon.inc}
|
|
|
|
procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
|
|
procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
|
|
procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
|
|
procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 4 Pin Change Interrupt Request 0
|
|
procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 5 Pin Change Interrupt Request 1
|
|
procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 6 Pin Change Interrupt Request 2
|
|
procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 7 Pin Change Interrupt Request 3
|
|
procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 8 Watchdog Time-out Interrupt
|
|
procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 9 Timer/Counter2 Compare Match A
|
|
procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 10 Timer/Counter2 Compare Match B
|
|
procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 11 Timer/Counter2 Overflow
|
|
procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 12 Timer/Counter1 Capture Event
|
|
procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer/Counter1 Compare Match A
|
|
procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer/Counter1 Compare Match B
|
|
procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer/Counter1 Overflow
|
|
procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 16 Timer/Counter0 Compare Match A
|
|
procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 17 Timer/Counter0 Compare Match B
|
|
procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 18 Timer/Counter0 Overflow
|
|
procedure SPI0_STC_ISR; external name 'SPI0_STC_ISR'; // Interrupt 19 SPI0 Serial Transfer Complete
|
|
procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 20 USART0 Rx Complete
|
|
procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 21 USART0 Data register Empty
|
|
procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 22 USART0 Tx Complete
|
|
procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 23 Analog Comparator
|
|
procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 24 ADC Conversion Complete
|
|
procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 25 EEPROM Ready
|
|
procedure TWI0_ISR; external name 'TWI0_ISR'; // Interrupt 26 2-wire Serial Interface 0
|
|
procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 27 Store Program Memory Read
|
|
procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 28 USART1 RX complete
|
|
procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 29 USART1 Data Register Empty
|
|
procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 30 USART1 TX complete
|
|
procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
|
|
procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
|
|
procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
|
|
procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 34 Timer/Counter3 Overflow
|
|
procedure USART0_RXS_ISR; external name 'USART0_RXS_ISR'; // Interrupt 35 USART0 RX start edge detect
|
|
procedure USART0_START_ISR; external name 'USART0_START_ISR'; // Interrupt 35 USART0 RX start edge detect
|
|
procedure USART1_RXS_ISR; external name 'USART1_RXS_ISR'; // Interrupt 36 USART1 RX start edge detect
|
|
procedure USART1_START_ISR; external name 'USART1_START_ISR'; // Interrupt 36 USART1 RX start edge detect
|
|
procedure PCINT4_ISR; external name 'PCINT4_ISR'; // Interrupt 37 Pin Change Interrupt Request 4
|
|
procedure XOSCFD_ISR; external name 'XOSCFD_ISR'; // Interrupt 38 Crystal failure detect
|
|
procedure PTC_EOC_ISR; external name 'PTC_EOC_ISR'; // Interrupt 39 PTC end of conversion
|
|
procedure PTC_WCOMP_ISR; external name 'PTC_WCOMP_ISR'; // Interrupt 40 PTC window comparator interrupt
|
|
procedure SPI1_STC_ISR; external name 'SPI1_STC_ISR'; // Interrupt 41 SPI1 Serial Transfer Complete
|
|
procedure TWI1_ISR; external name 'TWI1_ISR'; // Interrupt 42 2-wire Serial Interface 1
|
|
procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 43 Timer/Counter4 Capture Event
|
|
procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 44 Timer/Counter4 Compare Match A
|
|
procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 45 Timer/Counter4 Compare Match B
|
|
procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 46 Timer/Counter4 Overflow
|
|
procedure USART2_RX_ISR; external name 'USART2_RX_ISR'; // Interrupt 47 USART2 Rx Complete
|
|
procedure USART2_UDRE_ISR; external name 'USART2_UDRE_ISR'; // Interrupt 48 USART2 Data register Empty
|
|
procedure USART2_TX_ISR; external name 'USART2_TX_ISR'; // Interrupt 49 USART2 Tx Complete
|
|
procedure USART2_RXS_ISR; external name 'USART2_RXS_ISR'; // Interrupt 50 USART2 RX start edge detect
|
|
procedure USART2_START_ISR; external name 'USART2_START_ISR'; // Interrupt 50 USART2 RX start edge detect
|
|
|
|
procedure _FPC_start; assembler; nostackframe;
|
|
label
|
|
_start;
|
|
asm
|
|
.init
|
|
.globl _start
|
|
|
|
jmp _start
|
|
jmp INT0_ISR
|
|
jmp INT1_ISR
|
|
jmp INT2_ISR
|
|
jmp PCINT0_ISR
|
|
jmp PCINT1_ISR
|
|
jmp PCINT2_ISR
|
|
jmp PCINT3_ISR
|
|
jmp WDT_ISR
|
|
jmp TIMER2_COMPA_ISR
|
|
jmp TIMER2_COMPB_ISR
|
|
jmp TIMER2_OVF_ISR
|
|
jmp TIMER1_CAPT_ISR
|
|
jmp TIMER1_COMPA_ISR
|
|
jmp TIMER1_COMPB_ISR
|
|
jmp TIMER1_OVF_ISR
|
|
jmp TIMER0_COMPA_ISR
|
|
jmp TIMER0_COMPB_ISR
|
|
jmp TIMER0_OVF_ISR
|
|
jmp SPI0_STC_ISR
|
|
jmp USART0_RX_ISR
|
|
jmp USART0_UDRE_ISR
|
|
jmp USART0_TX_ISR
|
|
jmp ANALOG_COMP_ISR
|
|
jmp ADC_ISR
|
|
jmp EE_READY_ISR
|
|
jmp TWI0_ISR
|
|
jmp SPM_READY_ISR
|
|
jmp USART1_RX_ISR
|
|
jmp USART1_UDRE_ISR
|
|
jmp USART1_TX_ISR
|
|
jmp TIMER3_CAPT_ISR
|
|
jmp TIMER3_COMPA_ISR
|
|
jmp TIMER3_COMPB_ISR
|
|
jmp TIMER3_OVF_ISR
|
|
jmp USART0_RXS_ISR
|
|
jmp USART0_START_ISR
|
|
jmp USART1_RXS_ISR
|
|
jmp USART1_START_ISR
|
|
jmp PCINT4_ISR
|
|
jmp XOSCFD_ISR
|
|
jmp PTC_EOC_ISR
|
|
jmp PTC_WCOMP_ISR
|
|
jmp SPI1_STC_ISR
|
|
jmp TWI1_ISR
|
|
jmp TIMER4_CAPT_ISR
|
|
jmp TIMER4_COMPA_ISR
|
|
jmp TIMER4_COMPB_ISR
|
|
jmp TIMER4_OVF_ISR
|
|
jmp USART2_RX_ISR
|
|
jmp USART2_UDRE_ISR
|
|
jmp USART2_TX_ISR
|
|
jmp USART2_RXS_ISR
|
|
jmp USART2_START_ISR
|
|
|
|
{$i start.inc}
|
|
|
|
.weak INT0_ISR
|
|
.weak INT1_ISR
|
|
.weak INT2_ISR
|
|
.weak PCINT0_ISR
|
|
.weak PCINT1_ISR
|
|
.weak PCINT2_ISR
|
|
.weak PCINT3_ISR
|
|
.weak WDT_ISR
|
|
.weak TIMER2_COMPA_ISR
|
|
.weak TIMER2_COMPB_ISR
|
|
.weak TIMER2_OVF_ISR
|
|
.weak TIMER1_CAPT_ISR
|
|
.weak TIMER1_COMPA_ISR
|
|
.weak TIMER1_COMPB_ISR
|
|
.weak TIMER1_OVF_ISR
|
|
.weak TIMER0_COMPA_ISR
|
|
.weak TIMER0_COMPB_ISR
|
|
.weak TIMER0_OVF_ISR
|
|
.weak SPI0_STC_ISR
|
|
.weak USART0_RX_ISR
|
|
.weak USART0_UDRE_ISR
|
|
.weak USART0_TX_ISR
|
|
.weak ANALOG_COMP_ISR
|
|
.weak ADC_ISR
|
|
.weak EE_READY_ISR
|
|
.weak TWI0_ISR
|
|
.weak SPM_READY_ISR
|
|
.weak USART1_RX_ISR
|
|
.weak USART1_UDRE_ISR
|
|
.weak USART1_TX_ISR
|
|
.weak TIMER3_CAPT_ISR
|
|
.weak TIMER3_COMPA_ISR
|
|
.weak TIMER3_COMPB_ISR
|
|
.weak TIMER3_OVF_ISR
|
|
.weak USART0_RXS_ISR
|
|
.weak USART0_START_ISR
|
|
.weak USART1_RXS_ISR
|
|
.weak USART1_START_ISR
|
|
.weak PCINT4_ISR
|
|
.weak XOSCFD_ISR
|
|
.weak PTC_EOC_ISR
|
|
.weak PTC_WCOMP_ISR
|
|
.weak SPI1_STC_ISR
|
|
.weak TWI1_ISR
|
|
.weak TIMER4_CAPT_ISR
|
|
.weak TIMER4_COMPA_ISR
|
|
.weak TIMER4_COMPB_ISR
|
|
.weak TIMER4_OVF_ISR
|
|
.weak USART2_RX_ISR
|
|
.weak USART2_UDRE_ISR
|
|
.weak USART2_TX_ISR
|
|
.weak USART2_RXS_ISR
|
|
.weak USART2_START_ISR
|
|
|
|
.set INT0_ISR, Default_IRQ_handler
|
|
.set INT1_ISR, Default_IRQ_handler
|
|
.set INT2_ISR, Default_IRQ_handler
|
|
.set PCINT0_ISR, Default_IRQ_handler
|
|
.set PCINT1_ISR, Default_IRQ_handler
|
|
.set PCINT2_ISR, Default_IRQ_handler
|
|
.set PCINT3_ISR, Default_IRQ_handler
|
|
.set WDT_ISR, Default_IRQ_handler
|
|
.set TIMER2_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER2_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER2_OVF_ISR, Default_IRQ_handler
|
|
.set TIMER1_CAPT_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER1_OVF_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER0_OVF_ISR, Default_IRQ_handler
|
|
.set SPI0_STC_ISR, Default_IRQ_handler
|
|
.set USART0_RX_ISR, Default_IRQ_handler
|
|
.set USART0_UDRE_ISR, Default_IRQ_handler
|
|
.set USART0_TX_ISR, Default_IRQ_handler
|
|
.set ANALOG_COMP_ISR, Default_IRQ_handler
|
|
.set ADC_ISR, Default_IRQ_handler
|
|
.set EE_READY_ISR, Default_IRQ_handler
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.set TWI0_ISR, Default_IRQ_handler
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.set SPM_READY_ISR, Default_IRQ_handler
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.set USART1_RX_ISR, Default_IRQ_handler
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.set USART1_UDRE_ISR, Default_IRQ_handler
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.set USART1_TX_ISR, Default_IRQ_handler
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.set TIMER3_CAPT_ISR, Default_IRQ_handler
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.set TIMER3_COMPA_ISR, Default_IRQ_handler
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.set TIMER3_COMPB_ISR, Default_IRQ_handler
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.set TIMER3_OVF_ISR, Default_IRQ_handler
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.set USART0_RXS_ISR, Default_IRQ_handler
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.set USART0_START_ISR, Default_IRQ_handler
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.set USART1_RXS_ISR, Default_IRQ_handler
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.set USART1_START_ISR, Default_IRQ_handler
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.set PCINT4_ISR, Default_IRQ_handler
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.set XOSCFD_ISR, Default_IRQ_handler
|
|
.set PTC_EOC_ISR, Default_IRQ_handler
|
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.set PTC_WCOMP_ISR, Default_IRQ_handler
|
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.set SPI1_STC_ISR, Default_IRQ_handler
|
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.set TWI1_ISR, Default_IRQ_handler
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|
.set TIMER4_CAPT_ISR, Default_IRQ_handler
|
|
.set TIMER4_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER4_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER4_OVF_ISR, Default_IRQ_handler
|
|
.set USART2_RX_ISR, Default_IRQ_handler
|
|
.set USART2_UDRE_ISR, Default_IRQ_handler
|
|
.set USART2_TX_ISR, Default_IRQ_handler
|
|
.set USART2_RXS_ISR, Default_IRQ_handler
|
|
.set USART2_START_ISR, Default_IRQ_handler
|
|
end;
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|
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|
end.
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