mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 04:28:05 +02:00
3cb2cff444
git-svn-id: trunk@44130 -
(cherry picked from commit 04ad607bb4)
# Conflicts:
# .gitattributes
558 lines
20 KiB
ObjectPascal
558 lines
20 KiB
ObjectPascal
unit ATmega64HVE2;
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{$goto on}
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interface
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var
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PINA: byte absolute $20; // Port A Input Pins
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DDRA: byte absolute $21; // Port A Data Direction Register
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PORTA: byte absolute $22; // Port A Data Register
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PINB: byte absolute $23; // Port B Input Pins
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DDRB: byte absolute $24; // Port B Data Direction Register
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PORTB: byte absolute $25; // Port B Data Register
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TIFR0: byte absolute $35; // Timer/Counter Interrupt Flag register
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TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
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PCIFR: byte absolute $3B; // Pin Change Interrupt Flag Register
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EIFR: byte absolute $3C; // External Interrupt Flag Register
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EIMSK: byte absolute $3D; // External Interrupt Mask Register
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GPIOR0: byte absolute $3E; // General Purpose IO Register 0
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EECR: byte absolute $3F; // EEPROM Control Register
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EEDR: byte absolute $40; // EEPROM Data Register
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EEAR: word absolute $41; // EEPROM Read/Write Access
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EEARL: byte absolute $41; // EEPROM Read/Write Access
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EEARH: byte absolute $42; // EEPROM Read/Write Access;
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GTCCR: byte absolute $43; // General Timer/Counter Control Register
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TCCR0A: byte absolute $44; // Timer/Counter 0 Control Register A
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TCCR0B: byte absolute $45; // Timer/Counter0 Control Register B
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TCNT0: word absolute $46; // Timer Counter 0 Bytes
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TCNT0L: byte absolute $46; // Timer Counter 0 Bytes
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TCNT0H: byte absolute $47; // Timer Counter 0 Bytes;
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OCR0A: byte absolute $48; // Output Compare Register 0A
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OCR0B: byte absolute $49; // Output Compare Register B
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GPIOR1: byte absolute $4A; // General Purpose IO Register 1
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GPIOR2: byte absolute $4B; // General Purpose IO Register 2
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SPCR: byte absolute $4C; // SPI Control Register
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SPSR: byte absolute $4D; // SPI Status Register
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SPDR: byte absolute $4E; // SPI Data Register
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SMCR: byte absolute $53; // Sleep Mode Control Register
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MCUSR: byte absolute $54; // MCU Status Register
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MCUCR: byte absolute $55; // MCU Control Register
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SPMCSR: byte absolute $57; // Store Program Memory Control and Status Register
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SP: word absolute $5D; // Stack Pointer
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SPL: byte absolute $5D; // Stack Pointer
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SPH: byte absolute $5E; // Stack Pointer ;
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SREG: byte absolute $5F; // Status Register
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WDTCSR: byte absolute $60; // Watchdog Timer Control Register
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CLKPR: byte absolute $61; // Clock Prescale Register
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WUTCSR: byte absolute $62; // Wake-up Timer Control and Status Register
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WDTCLR: byte absolute $63; // Watchdog Timer Configuration Lock Register
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PRR0: byte absolute $64; // Power Reduction Register 0
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SOSCCALA: byte absolute $66; // Slow Oscillator Calibration Register A
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SOSCCALB: byte absolute $67; // Oscillator Calibration Register B
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PCICR: byte absolute $68; // Pin Change Interrupt Control Register
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EICRA: byte absolute $69; // External Interrupt Control Register
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PCMSK0: byte absolute $6B; // Pin Change Enable Mask Register 0
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PCMSK1: byte absolute $6C; // Pin Change Enable Mask Register 1
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TIMSK0: byte absolute $6E; // Timer/Counter Interrupt Mask Register
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TIMSK1: byte absolute $6F; // Timer/Counter Interrupt Mask Register
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DIDR0: byte absolute $7E; // Digital Input Disable Register
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TCCR1A: byte absolute $80; // Timer/Counter 1 Control Register A
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TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
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TCNT1: word absolute $84; // Timer Counter 1 Bytes
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TCNT1L: byte absolute $84; // Timer Counter 1 Bytes
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TCNT1H: byte absolute $85; // Timer Counter 1 Bytes;
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OCR1A: byte absolute $88; // Output Compare Register 1A
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OCR1B: byte absolute $89; // Output Compare Register B
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LINCR: byte absolute $C0; // LIN Control Register
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LINSIR: byte absolute $C1; // LIN Status and Interrupt Register
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LINENIR: byte absolute $C2; // LIN Enable Interrupt Register
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LINERR: byte absolute $C3; // LIN Error Register
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LINBTR: byte absolute $C4; // LIN Bit Timing Register
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LINBRRL: byte absolute $C5; // LIN Baud Rate Low Register
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LINBRRH: byte absolute $C6; // LIN Baud Rate High Register
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LINDLR: byte absolute $C7; // LIN Data Length Register
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LINIDR: byte absolute $C8; // LIN Identifier Register
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LINSEL: byte absolute $C9; // LIN Data Buffer Selection Register
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LINDAT: byte absolute $CA; // LIN Data Register
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BGCSRA: byte absolute $D1; // Bandgap Control and Status Register A
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BGCRB: byte absolute $D2; // Band Gap Calibration Register B
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BGCRA: byte absolute $D3; // Band Gap Calibration Register A
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BGLR: byte absolute $D4; // Band Gap Lock Register
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PLLCSR: byte absolute $D8; // PLL Control and Status Register
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PBOV: byte absolute $DC; // Port B Override
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ADSCSRA: byte absolute $E0; // ADC Synchronization Control and Status Register
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ADSCSRB: byte absolute $E1; // ADC Synchronization Control and Status Register
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ADCRA: byte absolute $E2; // ADC Control Register A
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ADCRB: byte absolute $E3; // ADC Control Register B
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ADCRC: byte absolute $E4; // ADC Control Register B
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ADCRD: byte absolute $E5; // ADC Control Register D
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ADCRE: byte absolute $E6; // ADC Control Register E
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ADIFR: byte absolute $E7; // ADC Interrupt Flag Register
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ADIMR: byte absolute $E8; // ADC Interrupt Mask Register
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CADRCL: word absolute $E9; // CC-ADC Regulator Current Comparator Threshold Level
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CADRCLL: byte absolute $E9; // CC-ADC Regulator Current Comparator Threshold Level
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CADRCLH: byte absolute $EA; // CC-ADC Regulator Current Comparator Threshold Level;
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CADIC: word absolute $EB; // C-ADC Instantaneous Conversion Result
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CADICL: byte absolute $EB; // C-ADC Instantaneous Conversion Result
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CADICH: byte absolute $EC; // C-ADC Instantaneous Conversion Result;
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CADAC0: byte absolute $ED; // C-ADC Accumulated Conversion Result
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CADAC1: byte absolute $EE; // C-ADC Accumulated Conversion Result
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CADAC2: byte absolute $EF; // C-ADC Accumulated Conversion Result
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CADAC3: byte absolute $F0; // C-ADC Accumulated Conversion Result
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VADIC: word absolute $F1; // V-ADC Instantaneous Conversion Result
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VADICL: byte absolute $F1; // V-ADC Instantaneous Conversion Result
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VADICH: byte absolute $F2; // V-ADC Instantaneous Conversion Result;
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VADAC0: byte absolute $F3; // V-ADC Accumulated Conversion Result
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VADAC1: byte absolute $F4; // V-ADC Accumulated Conversion Result
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VADAC2: byte absolute $F5; // V-ADC Accumulated Conversion Result
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VADAC3: byte absolute $F6; // V-ADC Accumulated Conversion Result
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const
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// Port A Data Register
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PA0 = $00;
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PA1 = $01;
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// Port B Data Register
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PB0 = $00;
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PB1 = $01;
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PB2 = $02;
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PB3 = $03;
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PB4 = $04;
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PB5 = $05;
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PB6 = $06;
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PB7 = $07;
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// Timer/Counter Interrupt Flag register
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TOV0 = $00;
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OCF0A = $01;
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OCF0B = $02;
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ICF0 = $03;
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// Timer/Counter Interrupt Flag register
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TOV1 = $00;
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OCF1A = $01;
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OCF1B = $02;
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ICF1 = $03;
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// Pin Change Interrupt Flag Register
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PCIF0 = $00; // Pin Change Interrupt Flags
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PCIF1 = $01; // Pin Change Interrupt Flags
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// External Interrupt Flag Register
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INTF0 = $00;
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// External Interrupt Mask Register
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INT0 = $00;
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// EEPROM Control Register
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EERE = $00;
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EEPE = $01;
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EEMPE = $02;
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EERIE = $03;
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EEPM0 = $04;
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EEPM1 = $05;
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// General Timer/Counter Control Register
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PSRSYNC = $00;
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TSM = $07;
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// Timer/Counter 0 Control Register A
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WGM00 = $00;
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ICS0 = $03;
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ICES0 = $04;
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ICNC0 = $05;
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ICEN0 = $06;
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TCW0 = $07;
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// Timer/Counter0 Control Register B
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CS00 = $00;
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CS01 = $01;
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CS02 = $02;
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// SPI Control Register
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SPR0 = $00; // SPI Clock Rate Selects
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SPR1 = $01; // SPI Clock Rate Selects
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CPHA = $02;
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CPOL = $03;
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MSTR = $04;
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DORD = $05;
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SPE = $06;
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SPIE = $07;
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// SPI Status Register
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SPI2X = $00;
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WCOL = $06;
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SPIF = $07;
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// Sleep Mode Control Register
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SE = $00;
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SM0 = $01; // Sleep Mode Select bits
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SM1 = $02; // Sleep Mode Select bits
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SM2 = $03; // Sleep Mode Select bits
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// MCU Status Register
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PORF = $00;
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EXTRF = $01;
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BODRF = $02;
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WDRF = $03;
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OCDRF = $04;
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// MCU Control Register
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IVCE = $00;
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IVSEL = $01;
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PUD = $04;
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CKOE = $05;
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// Store Program Memory Control and Status Register
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SPMEN = $00;
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PGERS = $01;
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PGWRT = $02;
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LBSET = $03;
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RWWSRE = $04;
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SIGRD = $05;
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RWWSB = $06;
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SPMIE = $07;
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// Status Register
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C = $00;
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Z = $01;
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N = $02;
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V = $03;
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S = $04;
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H = $05;
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T = $06;
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I = $07;
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// Watchdog Timer Control Register
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WDE = $03;
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WDCE = $04;
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WDP0 = $00; // Watchdog Timer Prescaler Bits
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WDP1 = $01; // Watchdog Timer Prescaler Bits
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WDP2 = $02; // Watchdog Timer Prescaler Bits
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WDP3 = $05; // Watchdog Timer Prescaler Bits
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WDIE = $06;
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WDIF = $07;
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// Clock Prescale Register
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CLKPS0 = $00; // Clock Prescaler Select Bits
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CLKPS1 = $01; // Clock Prescaler Select Bits
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CLKPCE = $07;
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// Wake-up Timer Control and Status Register
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WUTP0 = $00; // Wake-up Timer Prescaler Bits
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WUTP1 = $01; // Wake-up Timer Prescaler Bits
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WUTP2 = $02; // Wake-up Timer Prescaler Bits
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WUTE = $03;
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WUTR = $04;
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WUTIE = $06;
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WUTIF = $07;
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// Watchdog Timer Configuration Lock Register
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WDCLE = $00;
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WDCL0 = $01; // Watchdog Timer Comfiguration Lock bits
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WDCL1 = $02; // Watchdog Timer Comfiguration Lock bits
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// Power Reduction Register 0
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PRTIM0 = $00;
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PRTIM1 = $01;
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PRSPI = $02;
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PRLIN = $03;
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// Pin Change Interrupt Control Register
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PCIE0 = $00; // Pin Change Interrupt Enables
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PCIE1 = $01; // Pin Change Interrupt Enables
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// External Interrupt Control Register
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ISC00 = $00;
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ISC01 = $01;
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// Timer/Counter Interrupt Mask Register
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TOIE0 = $00;
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OCIE0A = $01;
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OCIE0B = $02;
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ICIE0 = $03;
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// Timer/Counter Interrupt Mask Register
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TOIE1 = $00;
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OCIE1A = $01;
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OCIE1B = $02;
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ICIE1 = $03;
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// Digital Input Disable Register
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PA0DID = $00;
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PA1DID = $01;
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// Timer/Counter 1 Control Register A
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WGM10 = $00;
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ICS1 = $03;
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ICES1 = $04;
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ICNC1 = $05;
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ICEN1 = $06;
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TCW1 = $07;
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// Timer/Counter1 Control Register B
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CS10 = $00; // Clock Select1 bis
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CS11 = $01; // Clock Select1 bis
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CS12 = $02; // Clock Select1 bis
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// LIN Control Register
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LCMD0 = $00; // LIN Command and Mode bits
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LCMD1 = $01; // LIN Command and Mode bits
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LCMD2 = $02; // LIN Command and Mode bits
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LENA = $03;
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LCONF0 = $04; // LIN Configuration bits
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LCONF1 = $05; // LIN Configuration bits
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LIN13 = $06;
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LSWRES = $07;
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// LIN Status and Interrupt Register
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LRXOK = $00;
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LTXOK = $01;
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LIDOK = $02;
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LERR = $03;
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LBUSY = $04;
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LIDST0 = $05; // Identifier Status bits
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LIDST1 = $06; // Identifier Status bits
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LIDST2 = $07; // Identifier Status bits
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// LIN Enable Interrupt Register
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LENRXOK = $00;
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LENTXOK = $01;
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LENIDOK = $02;
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LENERR = $03;
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// LIN Error Register
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LBERR = $00;
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LCERR = $01;
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LPERR = $02;
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LSERR = $03;
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LFERR = $04;
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LOVERR = $05;
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LTOERR = $06;
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LABORT = $07;
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// LIN Bit Timing Register
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LBT0 = $00; // LIN Bit Timing bits
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LBT1 = $01; // LIN Bit Timing bits
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LBT2 = $02; // LIN Bit Timing bits
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LBT3 = $03; // LIN Bit Timing bits
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LBT4 = $04; // LIN Bit Timing bits
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LBT5 = $05; // LIN Bit Timing bits
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LDISR = $07;
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// LIN Baud Rate Low Register
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LDIV0 = $00;
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LDIV1 = $01;
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LDIV2 = $02;
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LDIV3 = $03;
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LDIV4 = $04;
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LDIV5 = $05;
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LDIV6 = $06;
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LDIV7 = $07;
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// LIN Data Length Register
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LRXDL0 = $00; // LIN Receive Data Length bits
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LRXDL1 = $01; // LIN Receive Data Length bits
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LRXDL2 = $02; // LIN Receive Data Length bits
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LRXDL3 = $03; // LIN Receive Data Length bits
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LTXDL0 = $04; // LIN Transmit Data Length bits
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LTXDL1 = $05; // LIN Transmit Data Length bits
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LTXDL2 = $06; // LIN Transmit Data Length bits
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LTXDL3 = $07; // LIN Transmit Data Length bits
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// LIN Identifier Register
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LID0 = $00; // Identifier bit 5 or Data Length bits
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LID1 = $01; // Identifier bit 5 or Data Length bits
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LID2 = $02; // Identifier bit 5 or Data Length bits
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LID3 = $03; // Identifier bit 5 or Data Length bits
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LID4 = $04; // Identifier bit 5 or Data Length bits
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LID5 = $05; // Identifier bit 5 or Data Length bits
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LP0 = $06; // Parity bits
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LP1 = $07; // Parity bits
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// LIN Data Buffer Selection Register
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LINDX0 = $00; // FIFO LIN Data Buffer Index bits
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LINDX1 = $01; // FIFO LIN Data Buffer Index bits
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LINDX2 = $02; // FIFO LIN Data Buffer Index bits
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LAINC = $03;
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// LIN Data Register
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LDATA0 = $00;
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LDATA1 = $01;
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LDATA2 = $02;
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LDATA3 = $03;
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LDATA4 = $04;
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LDATA5 = $05;
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LDATA6 = $06;
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LDATA7 = $07;
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// Bandgap Control and Status Register A
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BGSC0 = $00; // Band Gap Sample Configuration
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BGSC1 = $01; // Band Gap Sample Configuration
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BGSC2 = $02; // Band Gap Sample Configuration
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// Band Gap Calibration Register B
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BGCL0 = $00; // Band Gap Calibration Linear
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BGCL1 = $01; // Band Gap Calibration Linear
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BGCL2 = $02; // Band Gap Calibration Linear
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BGCL3 = $03; // Band Gap Calibration Linear
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BGCL4 = $04; // Band Gap Calibration Linear
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BGCL5 = $05; // Band Gap Calibration Linear
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BGCL6 = $06; // Band Gap Calibration Linear
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BGCL7 = $07; // Band Gap Calibration Linear
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// Band Gap Calibration Register A
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BGCN0 = $00; // Band Gap Calibration Nominal
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BGCN1 = $01; // Band Gap Calibration Nominal
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BGCN2 = $02; // Band Gap Calibration Nominal
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BGCN3 = $03; // Band Gap Calibration Nominal
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BGCN4 = $04; // Band Gap Calibration Nominal
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BGCN5 = $05; // Band Gap Calibration Nominal
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BGCN6 = $06; // Band Gap Calibration Nominal
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BGCN7 = $07; // Band Gap Calibration Nominal
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// Band Gap Lock Register
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BGPL = $00;
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BGPLE = $01;
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// PLL Control and Status Register
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PLLCIE = $00;
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PLLCIF = $01;
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LOCK = $04;
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SWEN = $05;
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// Port B Override
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PBOE0 = $00;
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PBOE3 = $03;
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PBOVCE = $07;
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// ADC Synchronization Control and Status Register
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SCMD0 = $00; // Synchronization Command
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SCMD1 = $01; // Synchronization Command
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SBSY = $02;
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// ADC Synchronization Control and Status Register
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CADICRB = $00;
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CADACRB = $01;
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CADICPS = $02;
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VADICRB = $04;
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VADACRB = $05;
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VADICPS = $06;
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// ADC Control Register A
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CKSEL = $00;
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ADCMS0 = $01; // C-ADC Chopper Mode Select
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ADCMS1 = $02; // C-ADC Chopper Mode Select
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ADPSEL = $03;
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// ADC Control Register B
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ADADES0 = $00; // Accumulated Decimation Ratio Select
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ADADES1 = $01; // Accumulated Decimation Ratio Select
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ADADES2 = $02; // Accumulated Decimation Ratio Select
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ADIDES0 = $03; // Instantaneous Decimation Ratio Select
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ADIDES1 = $04; // Instantaneous Decimation Ratio Select
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// ADC Control Register B
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CADRCT0 = $00; // C-ADC Regular Current Count Threshold
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CADRCT1 = $01; // C-ADC Regular Current Count Threshold
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CADRCT2 = $02; // C-ADC Regular Current Count Threshold
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CADRCT3 = $03; // C-ADC Regular Current Count Threshold
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CADRCM0 = $04; // C-ADC Regular Current Comparator Mode
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CADRCM1 = $05; // C-ADC Regular Current Comparator Mode
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CADEN = $07;
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// ADC Control Register D
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CADDSEL = $00;
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CADPDM0 = $01; // C-ADC Pin Diagnostics Mode
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CADPDM1 = $02; // C-ADC Pin Diagnostics Mode
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CADG0 = $03; // C-ADC Gain
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CADG1 = $04; // C-ADC Gain
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CADG2 = $05; // C-ADC Gain
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// ADC Control Register E
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VADMUX0 = $00; // V-ADC Channel Select
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VADMUX1 = $01; // V-ADC Channel Select
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VADMUX2 = $02; // V-ADC Channel Select
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VADPDM0 = $03; // V-ADC Pin Diagnostics Mode
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VADPDM1 = $04; // V-ADC Pin Diagnostics Mode
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VADREFS = $05;
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VADEN = $07;
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// ADC Interrupt Flag Register
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CADICIF = $00;
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CADACIF = $01;
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CADRCIF = $02;
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VADICIF = $04;
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VADACIF = $05;
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// ADC Interrupt Mask Register
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CADICIE = $00;
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CADACIE = $01;
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CADRCIE = $02;
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VADICIE = $04;
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VADACIE = $05;
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implementation
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt 1
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 4 Watchdog Timeout Interrupt
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procedure WAKEUP_ISR; external name 'WAKEUP_ISR'; // Interrupt 5 Wakeup Timer Overflow
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procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 6 Timer 1 Input capture
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 7 Timer 1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 8 Timer 1 Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 9 Timer 1 overflow
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procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 10 Timer 0 Input Capture
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 11 Timer 0 Comapre Match A
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 12 Timer 0 Compare Match B
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 13 Timer 0 Overflow
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procedure LIN_STATUS_ISR; external name 'LIN_STATUS_ISR'; // Interrupt 14 LIN Status Interrupt
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procedure LIN_ERROR_ISR; external name 'LIN_ERROR_ISR'; // Interrupt 15 LIN Error Interrupt
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procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 16 SPI Serial transfer complete
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procedure VADC_CONV_ISR; external name 'VADC_CONV_ISR'; // Interrupt 17 Voltage ADC Instantaneous Conversion Complete
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procedure VADC_ACC_ISR; external name 'VADC_ACC_ISR'; // Interrupt 18 Voltage ADC Accumulated Conversion Complete
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procedure CADC_CONV_ISR; external name 'CADC_CONV_ISR'; // Interrupt 19 C-ADC Instantaneous Conversion Complete
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procedure CADC_REG_CUR_ISR; external name 'CADC_REG_CUR_ISR'; // Interrupt 20 C-ADC Regular Current
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procedure CADC_ACC_ISR; external name 'CADC_ACC_ISR'; // Interrupt 21 C-ADC Accumulated Conversion Complete
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 22 EEPROM Ready
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procedure SPM_ISR; external name 'SPM_ISR'; // Interrupt 23 SPM Ready
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procedure PLL_ISR; external name 'PLL_ISR'; // Interrupt 24 PLL Lock Change Interrupt
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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jmp _start
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jmp INT0_ISR
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jmp PCINT0_ISR
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jmp PCINT1_ISR
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jmp WDT_ISR
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jmp WAKEUP_ISR
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jmp TIMER1_IC_ISR
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jmp TIMER1_COMPA_ISR
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jmp TIMER1_COMPB_ISR
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jmp TIMER1_OVF_ISR
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jmp TIMER0_IC_ISR
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jmp TIMER0_COMPA_ISR
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jmp TIMER0_COMPB_ISR
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jmp TIMER0_OVF_ISR
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jmp LIN_STATUS_ISR
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jmp LIN_ERROR_ISR
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jmp SPI_STC_ISR
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jmp VADC_CONV_ISR
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jmp VADC_ACC_ISR
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jmp CADC_CONV_ISR
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jmp CADC_REG_CUR_ISR
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jmp CADC_ACC_ISR
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jmp EE_READY_ISR
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jmp SPM_ISR
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jmp PLL_ISR
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{$i start.inc}
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.weak INT0_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak WDT_ISR
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.weak WAKEUP_ISR
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.weak TIMER1_IC_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_IC_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak TIMER0_OVF_ISR
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.weak LIN_STATUS_ISR
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.weak LIN_ERROR_ISR
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.weak SPI_STC_ISR
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.weak VADC_CONV_ISR
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.weak VADC_ACC_ISR
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.weak CADC_CONV_ISR
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.weak CADC_REG_CUR_ISR
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.weak CADC_ACC_ISR
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.weak EE_READY_ISR
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.weak SPM_ISR
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.weak PLL_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set WAKEUP_ISR, Default_IRQ_handler
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.set TIMER1_IC_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_IC_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set LIN_STATUS_ISR, Default_IRQ_handler
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.set LIN_ERROR_ISR, Default_IRQ_handler
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.set SPI_STC_ISR, Default_IRQ_handler
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.set VADC_CONV_ISR, Default_IRQ_handler
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.set VADC_ACC_ISR, Default_IRQ_handler
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.set CADC_CONV_ISR, Default_IRQ_handler
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.set CADC_REG_CUR_ISR, Default_IRQ_handler
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.set CADC_ACC_ISR, Default_IRQ_handler
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.set EE_READY_ISR, Default_IRQ_handler
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.set SPM_ISR, Default_IRQ_handler
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.set PLL_ISR, Default_IRQ_handler
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end;
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end.
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