mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 04:08:04 +02:00
61c6c04f71
git-svn-id: trunk@44081 -
(cherry picked from commit 00214406bc)
# Conflicts:
# .gitattributes
358 lines
12 KiB
ObjectPascal
358 lines
12 KiB
ObjectPascal
unit ATtiny104;
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{$goto on}
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interface
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var
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PINA: byte absolute $00; // Input Pins, Port A
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DDRA: byte absolute $01; // Data Direction Register, Port A
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PORTA: byte absolute $02; // Port A Data register
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PUEA: byte absolute $03; // Pull-up Enable Control Register for PORTA
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PINB: byte absolute $04; // Input Pins, Port B
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DDRB: byte absolute $05; // Data Direction Register, Port B
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PORTB: byte absolute $06; // Port B Data register
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PUEB: byte absolute $07; // Pull-up Enable Control Register for PORTB
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UDR: byte absolute $08; // USART I/O Data Register
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UBRR: word absolute $09; // USART Baud Rate Register Bytes
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UBRRL: byte absolute $09; // USART Baud Rate Register Bytes
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UBRRH: byte absolute $0A; // USART Baud Rate Register Bytes;
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UCSRD: byte absolute $0B; // USART Control and Status Register D
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UCSRC: byte absolute $0C; // USART Control and Status Register C
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UCSRB: byte absolute $0D; // USART Control and Status Register B
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UCSRA: byte absolute $0E; // USART Control and Status Register A
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PCMSK0: byte absolute $0F; // Pin Change Mask Register 0
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PCMSK1: byte absolute $10; // Pin Change Mask Register 1
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PCIFR: byte absolute $11; // Pin Change Interrupt Flag Register
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PCICR: byte absolute $12; // Pin Change Interrupt Control Register
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EIMSK: byte absolute $13; // External Interrupt Mask register
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EIFR: byte absolute $14; // External Interrupt Flag register
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EICRA: byte absolute $15; // External Interrupt Control Register A
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PORTCR: byte absolute $16; // Port Control Register
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DIDR0: byte absolute $17;
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ADCL: byte absolute $19; // ADC Data Register Low
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ADCH: byte absolute $1A; // ADC Data Register High
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ADMUX: byte absolute $1B; // The ADC multiplexer Selection Register
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ADCSRB: byte absolute $1C; // The ADC Control and Status register B
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ADCSRA: byte absolute $1D; // The ADC Control and Status register A
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ACSRB: byte absolute $1E; // Analog Comparator Control And Status Register B
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ACSRA: byte absolute $1F; // Analog Comparator Control And Status Register A
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ICR0: word absolute $22; // Input Capture Register Bytes
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ICR0L: byte absolute $22; // Input Capture Register Bytes
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ICR0H: byte absolute $23; // Input Capture Register Bytes;
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OCR0B: word absolute $24; // Timer/Counter0 Output Compare Register B
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OCR0BL: byte absolute $24; // Timer/Counter0 Output Compare Register B
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OCR0BH: byte absolute $25; // Timer/Counter0 Output Compare Register B ;
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OCR0A: word absolute $26; // Timer/Counter 0 Output Compare Register A
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OCR0AL: byte absolute $26; // Timer/Counter 0 Output Compare Register A
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OCR0AH: byte absolute $27; // Timer/Counter 0 Output Compare Register A ;
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TCNT0: word absolute $28; // Timer/Counter0
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TCNT0L: byte absolute $28; // Timer/Counter0
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TCNT0H: byte absolute $29; // Timer/Counter0 ;
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TIFR0: byte absolute $2A; // Overflow Interrupt Enable
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TIMSK0: byte absolute $2B; // Timer Interrupt Mask Register 0
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TCCR0C: byte absolute $2C; // Timer/Counter 0 Control Register C
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TCCR0B: byte absolute $2D; // Timer/Counter 0 Control Register B
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TCCR0A: byte absolute $2E; // Timer/Counter 0 Control Register A
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GTCCR: byte absolute $2F; // General Timer/Counter Control Register
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WDTCSR: byte absolute $31; // Watchdog Timer Control and Status Register
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NVMCSR: byte absolute $32; // Non-Volatile Memory Control and Status Register
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NVMCMD: byte absolute $33; // Non-Volatile Memory Command
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VLMCSR: byte absolute $34; // Vcc Level Monitoring Control and Status Register
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PRR: byte absolute $35; // Power Reduction Register
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CLKPSR: byte absolute $36; // Clock Prescale Register
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CLKMSR: byte absolute $37; // Clock Main Settings Register
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OSCCAL: byte absolute $39; // Oscillator Calibration Value
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SMCR: byte absolute $3A; // Sleep Mode Control Register
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RSTFLR: byte absolute $3B; // Reset Flag Register
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CCP: byte absolute $3C; // Configuration Change Protection
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SP: word absolute $3D; // Stack Pointer
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SPL: byte absolute $3D; // Stack Pointer
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SPH: byte absolute $3E; // Stack Pointer ;
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SREG: byte absolute $3F; // Status Register
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const
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// Port A Data register
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PA0 = $00;
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PA1 = $01;
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PA2 = $02;
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PA3 = $03;
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PA4 = $04;
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PA5 = $05;
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PA6 = $06;
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PA7 = $07;
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// Port B Data register
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PB0 = $00;
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PB1 = $01;
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PB2 = $02;
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PB3 = $03;
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// USART Control and Status Register D
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SFDE = $05;
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RXS = $06;
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RXSIE = $07;
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// USART Control and Status Register C
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UCPOL = $00;
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UCSZ0 = $01; // Character Size
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UCSZ1 = $02; // Character Size
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USBS = $03;
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UPM0 = $04; // Parity Mode Bits
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UPM1 = $05; // Parity Mode Bits
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UMSEL0 = $06; // USART Mode Select
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UMSEL1 = $07; // USART Mode Select
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// USART Control and Status Register B
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TXB8 = $00;
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RXB8 = $01;
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UCSZ2 = $02;
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TXEN = $03;
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RXEN = $04;
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UDRIE = $05;
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TXCIE = $06;
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RXCIE = $07;
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// USART Control and Status Register A
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MPCM = $00;
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U2X = $01;
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UPE = $02;
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DOR = $03;
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FE = $04;
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UDRE = $05;
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TXC = $06;
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RXC = $07;
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// Pin Change Mask Register 0
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PCINT0 = $00;
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PCINT1 = $01;
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PCINT2 = $02;
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PCINT3 = $03;
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PCINT4 = $04;
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PCINT5 = $05;
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PCINT6 = $06;
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PCINT7 = $07;
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// Pin Change Mask Register 1
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PCINT8 = $00;
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PCINT9 = $01;
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PCINT10 = $02;
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PCINT11 = $03;
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// Pin Change Interrupt Flag Register
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PCIF0 = $00;
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PCIF1 = $01;
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// Pin Change Interrupt Control Register
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PCIE0 = $00;
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PCIE1 = $01;
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// External Interrupt Mask register
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INT0 = $00;
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// External Interrupt Flag register
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INTF0 = $00;
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// External Interrupt Control Register A
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ISC00 = $00;
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ISC01 = $01;
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// Port Control Register
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BBMA = $00;
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BBMB = $01;
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ADC0D = $00;
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AIN0D = $00;
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ADC1D = $01;
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AIN1D = $01;
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ADC2D = $02;
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ADC3D = $03;
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ADC4D = $04;
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ADC5D = $05;
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ADC6D = $06;
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ADC7D = $07;
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// The ADC multiplexer Selection Register
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MUX0 = $00; // Analog Channel Selection Bits
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MUX1 = $01; // Analog Channel Selection Bits
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MUX2 = $02; // Analog Channel Selection Bits
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REFS0 = $06; // Analog Reference voltage Selection Bits
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REFS1 = $07; // Analog Reference voltage Selection Bits
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// The ADC Control and Status register B
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ADTS0 = $00; // ADC Auto Trigger Source bits
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ADTS1 = $01; // ADC Auto Trigger Source bits
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ADTS2 = $02; // ADC Auto Trigger Source bits
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ADLAR = $07;
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// The ADC Control and Status register A
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ADPS0 = $00; // ADC Prescaler Select Bits
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ADPS1 = $01; // ADC Prescaler Select Bits
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ADPS2 = $02; // ADC Prescaler Select Bits
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ADIE = $03;
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ADIF = $04;
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ADATE = $05;
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ADSC = $06;
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ADEN = $07;
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// Analog Comparator Control And Status Register B
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ACPMUX = $00;
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ACOE = $01;
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// Analog Comparator Control And Status Register A
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ACIS0 = $00; // Analog Comparator Interrupt Mode Select bits
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ACIS1 = $01; // Analog Comparator Interrupt Mode Select bits
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ACIC = $02;
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ACIE = $03;
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ACI = $04;
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ACO = $05;
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ACBG = $06;
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ACD = $07;
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// Overflow Interrupt Enable
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TOV0 = $00;
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OCF0A = $01;
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OCF0B = $02;
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ICF0 = $05;
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// Timer Interrupt Mask Register 0
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TOIE0 = $00;
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OCIE0A = $01;
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OCIE0B = $02;
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ICIE0 = $05;
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// Timer/Counter 0 Control Register C
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FOC0B = $06;
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FOC0A = $07;
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// Timer/Counter 0 Control Register B
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CS00 = $00; // Clock Select
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CS01 = $01; // Clock Select
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CS02 = $02; // Clock Select
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ICES0 = $06;
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ICNC0 = $07;
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// Timer/Counter 0 Control Register A
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WGM00 = $00; // Waveform Generation Mode
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WGM01 = $01; // Waveform Generation Mode
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COM0B0 = $04; // Compare Output Mode for Channel B bits
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COM0B1 = $05; // Compare Output Mode for Channel B bits
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COM0A0 = $06; // Compare Output Mode for Channel A bits
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COM0A1 = $07; // Compare Output Mode for Channel A bits
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// General Timer/Counter Control Register
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PSR = $00;
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REMAP = $01;
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TSM = $07;
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// Watchdog Timer Control and Status Register
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WDE = $03;
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WDP0 = $00; // Watchdog Timer Prescaler Bits
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WDP1 = $01; // Watchdog Timer Prescaler Bits
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WDP2 = $02; // Watchdog Timer Prescaler Bits
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WDP3 = $05; // Watchdog Timer Prescaler Bits
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WDIE = $06;
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WDIF = $07;
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// Non-Volatile Memory Control and Status Register
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NVMBSY = $07;
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// Vcc Level Monitoring Control and Status Register
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VLM0 = $00; // Trigger Level of Voltage Level Monitor bits
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VLM1 = $01; // Trigger Level of Voltage Level Monitor bits
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VLM2 = $02; // Trigger Level of Voltage Level Monitor bits
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VLMIE = $06;
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VLMF = $07;
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// Power Reduction Register
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PRTIM0 = $00;
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PRADC = $01;
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PRUSART = $02;
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// Clock Prescale Register
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CLKPS0 = $00; // Clock Prescaler Select Bits
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CLKPS1 = $01; // Clock Prescaler Select Bits
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CLKPS2 = $02; // Clock Prescaler Select Bits
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CLKPS3 = $03; // Clock Prescaler Select Bits
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// Clock Main Settings Register
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CLKMS0 = $00; // Clock Main Select Bits
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CLKMS1 = $01; // Clock Main Select Bits
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// Sleep Mode Control Register
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SE = $00;
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SM0 = $01; // Sleep Mode Select Bits
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SM1 = $02; // Sleep Mode Select Bits
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SM2 = $03; // Sleep Mode Select Bits
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// Reset Flag Register
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PORF = $00;
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EXTRF = $01;
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WDRF = $03;
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// Configuration Change Protection
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CCP0 = $00; // CCP signature
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CCP1 = $01; // CCP signature
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CCP2 = $02; // CCP signature
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CCP3 = $03; // CCP signature
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CCP4 = $04; // CCP signature
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CCP5 = $05; // CCP signature
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CCP6 = $06; // CCP signature
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CCP7 = $07; // CCP signature
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// Status Register
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C = $00;
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Z = $01;
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N = $02;
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V = $03;
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S = $04;
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H = $05;
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T = $06;
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I = $07;
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
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procedure TIM0_CAPT_ISR; external name 'TIM0_CAPT_ISR'; // Interrupt 4 Timer/Counter0 Input Capture
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procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 5 Timer/Counter0 Overflow
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procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 6 Timer/Counter Compare Match A
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procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 7 Timer/Counter Compare Match B
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 8 Analog Comparator
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 9 Watchdog Time-out
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procedure VLM_ISR; external name 'VLM_ISR'; // Interrupt 10 Vcc Voltage Level Monitor
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 11 ADC Conversion complete
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procedure USART_RXS_ISR; external name 'USART_RXS_ISR'; // Interrupt 12 USART RX Start
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procedure USART_RXC_ISR; external name 'USART_RXC_ISR'; // Interrupt 13 USART RX Complete
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procedure USART_DRE_ISR; external name 'USART_DRE_ISR'; // Interrupt 14 USART Data register empty
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procedure USART_TXC_ISR; external name 'USART_TXC_ISR'; // Interrupt 15 USART Tx Complete
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp INT0_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp TIM0_CAPT_ISR
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rjmp TIM0_OVF_ISR
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rjmp TIM0_COMPA_ISR
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rjmp TIM0_COMPB_ISR
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rjmp ANA_COMP_ISR
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rjmp WDT_ISR
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rjmp VLM_ISR
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rjmp ADC_ISR
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rjmp USART_RXS_ISR
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rjmp USART_RXC_ISR
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rjmp USART_DRE_ISR
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rjmp USART_TXC_ISR
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{$i start.inc}
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.weak INT0_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak TIM0_CAPT_ISR
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.weak TIM0_OVF_ISR
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.weak TIM0_COMPA_ISR
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.weak TIM0_COMPB_ISR
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.weak ANA_COMP_ISR
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.weak WDT_ISR
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.weak VLM_ISR
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.weak ADC_ISR
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.weak USART_RXS_ISR
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.weak USART_RXC_ISR
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.weak USART_DRE_ISR
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.weak USART_TXC_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set TIM0_CAPT_ISR, Default_IRQ_handler
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.set TIM0_OVF_ISR, Default_IRQ_handler
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.set TIM0_COMPA_ISR, Default_IRQ_handler
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.set TIM0_COMPB_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set VLM_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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.set USART_RXS_ISR, Default_IRQ_handler
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.set USART_RXC_ISR, Default_IRQ_handler
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.set USART_DRE_ISR, Default_IRQ_handler
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.set USART_TXC_ISR, Default_IRQ_handler
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end;
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end.
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