mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 06:48:10 +02:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
306 lines
12 KiB
ObjectPascal
306 lines
12 KiB
ObjectPascal
unit ATtiny84;
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{$goto on}
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interface
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var
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// PORTA
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PORTA : byte absolute $00+$3B; // Port A Data Register
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DDRA : byte absolute $00+$3A; // Port A Data Direction Register
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PINA : byte absolute $00+$39; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$38; // Data Register, Port B
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DDRB : byte absolute $00+$37; // Data Direction Register, Port B
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PINB : byte absolute $00+$36; // Input Pins, Port B
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// ANALOG_COMPARATOR
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ADCSRB : byte absolute $00+$23; // ADC Control and Status Register B
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ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
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DIDR0 : byte absolute $00+$21; //
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// AD_CONVERTER
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ADMUX : byte absolute $00+$27; // ADC Multiplexer Selection Register
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ADCSRA : byte absolute $00+$26; // ADC Control and Status Register A
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ADC : word absolute $00+$24; // ADC Data Register Bytes
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ADCL : byte absolute $00+$24; // ADC Data Register Bytes
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ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes
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// USI
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USIBR : byte absolute $00+$30; // USI Buffer Register
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USIDR : byte absolute $00+$2F; // USI Data Register
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USISR : byte absolute $00+$2E; // USI Status Register
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USICR : byte absolute $00+$2D; // USI Control Register
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// EXTERNAL_INTERRUPT
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MCUCR : byte absolute $00+$55; // MCU Control Register
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GIMSK : byte absolute $00+$5B; // General Interrupt Mask Register
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GIFR : byte absolute $00+$5A; // General Interrupt Flag register
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PCMSK1 : byte absolute $00+$40; // Pin Change Enable Mask 1
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PCMSK0 : byte absolute $00+$32; // Pin Change Enable Mask 0
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// EEPROM
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EEAR : word absolute $00+$3E; // EEPROM Address Register Bytes
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EEARL : byte absolute $00+$3E; // EEPROM Address Register Bytes
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EEARH : byte absolute $00+$3E+1; // EEPROM Address Register Bytes
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// WATCHDOG
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WDTCSR : byte absolute $00+$41; // Watchdog Timer Control Register
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// TIMER_COUNTER_0
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TIMSK0 : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register
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TIFR0 : byte absolute $00+$58; // Timer/Counter0 Interrupt Flag Register
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TCCR0A : byte absolute $00+$50; // Timer/Counter Control Register A
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TCCR0B : byte absolute $00+$53; // Timer/Counter Control Register B
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TCNT0 : byte absolute $00+$52; // Timer/Counter0
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OCR0A : byte absolute $00+$56; // Timer/Counter0 Output Compare Register A
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OCR0B : byte absolute $00+$5C; // Timer/Counter0 Output Compare Register B
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GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register
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// TIMER_COUNTER_1
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TIMSK1 : byte absolute $00+$2C; // Timer/Counter1 Interrupt Mask Register
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TIFR1 : byte absolute $00+$2B; // Timer/Counter Interrupt Flag register
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TCCR1A : byte absolute $00+$4F; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$4E; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$42; // Timer/Counter1 Control Register C
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TCNT1 : word absolute $00+$4C; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$4C; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$4C+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$4A; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AL : byte absolute $00+$4A; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AH : byte absolute $00+$4A+1; // Timer/Counter1 Output Compare Register A Bytes
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OCR1B : word absolute $00+$48; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BL : byte absolute $00+$48; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BH : byte absolute $00+$48+1; // Timer/Counter1 Output Compare Register B Bytes
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ICR1 : word absolute $00+$44; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$44; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$44+1; // Timer/Counter1 Input Capture Register Bytes
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// BOOT_LOAD
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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// CPU
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PRR : byte absolute $00+$20; // Power Reduction Register
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OSCCAL : byte absolute $00+$51; // Oscillator Calibration Value
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CLKPR : byte absolute $00+$46; // Clock Prescale Register
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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MCUSR : byte absolute $00+$54; // MCU Status Register
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GPIOR2 : byte absolute $00+$35; // General Purpose I/O Register 2
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GPIOR1 : byte absolute $00+$34; // General Purpose I/O Register 1
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GPIOR0 : byte absolute $00+$33; // General Purpose I/O Register 0
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const
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// ADCSRB
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ACME = 6; // Analog Comparator Multiplexer Enable
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// DIDR0
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ADC1D = 1; // ADC 1 Digital input buffer disable
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ADC0D = 0; // ADC 0 Digital input buffer disable
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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BIN = 7; // Bipolar Input Mode
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ADLAR = 4; // ADC Left Adjust Result
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ADTS = 0; // ADC Auto Trigger Source bits
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// USISR
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USISIF = 7; // Start Condition Interrupt Flag
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USIOIF = 6; // Counter Overflow Interrupt Flag
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USIPF = 5; // Stop Condition Flag
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USIDC = 4; // Data Output Collision
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USICNT = 0; // USI Counter Value Bits
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// USICR
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USISIE = 7; // Start Condition Interrupt Enable
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USIOIE = 6; // Counter Overflow Interrupt Enable
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USIWM = 4; // USI Wire Mode Bits
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USICS = 2; // USI Clock Source Select Bits
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USICLK = 1; // Clock Strobe
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USITC = 0; // Toggle Clock Port Pin
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// MCUCR
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ISC01 = 1; // Interrupt Sense Control 0 Bit 1
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ISC00 = 0; // Interrupt Sense Control 0 Bit 0
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// GIMSK
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INT0 = 6; // External Interrupt Request 0 Enable
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PCIE = 4; // Pin Change Interrupt Enables
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// GIFR
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INTF0 = 6; // External Interrupt Flag 0
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PCIF = 4; // Pin Change Interrupt Flags
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// EECR
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EEPM = 4; // EEPROM Programming Mode Bits
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMPE = 2; // EEPROM Master Write Enable
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EEPE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// WDTCSR
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WDIF = 7; // Watchdog Timeout Interrupt Flag
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WDIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// TIMSK0
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OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable
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OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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OCF0B = 2; // Timer/Counter0 Output Compare Flag B
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OCF0A = 1; // Timer/Counter0 Output Compare Flag A
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// TCCR0A
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COM0A = 6; // Compare Match Output A Mode bits
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COM0B = 4; // Compare Match Output B Mode bits
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WGM0 = 0; // Waveform Generation Mode bits
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// TCCR0B
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FOC0A = 7; // Force Output Compare A
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FOC0B = 6; // Force Output Compare B
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WGM02 = 3; // Waveform Generation Mode bit 2
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CS0 = 0; // Clock Select bits
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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PSR10 = 0; // Prescaler Reset Timer/CounterN
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// TIMSK1
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ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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OCIE1B = 2; // Timer/Counter1 Output Compare B Match Interrupt Enable
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OCIE1A = 1; // Timer/Counter1 Output Compare A Match Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 5; // Timer/Counter1 Input Capture Flag
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OCF1B = 2; // Timer/Counter1 Output Compare B Match Flag
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OCF1A = 1; // Timer/Counter1 Output Compare A Match Flag
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Pulse Width Modulator Select Bits
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Clock Select1 bits
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// TCCR1C
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FOC1A = 7; // Force Output Compare for Channel A
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FOC1B = 6; // Force Output Compare for Channel B
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// SPMCSR
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CTPB = 4; // Clear temporary page buffer
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RFLB = 3; // Read fuse and lock bits
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// PRR
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PRTIM1 = 3; // Power Reduction Timer/Counter1
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PRTIM0 = 2; // Power Reduction Timer/Counter0
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PRUSI = 1; // Power Reduction USI
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PRADC = 0; // Power Reduction ADC
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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PUD = 6; //
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SE = 5; // Sleep Enable
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SM = 3; // Sleep Mode Select Bits
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure EXT_INT0_ISR; external name 'EXT_INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
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procedure WATCHDOG_ISR; external name 'WATCHDOG_ISR'; // Interrupt 4 Watchdog Time-out
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procedure TIM1_CAPT_ISR; external name 'TIM1_CAPT_ISR'; // Interrupt 5 Timer/Counter1 Capture Event
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procedure TIM1_COMPA_ISR; external name 'TIM1_COMPA_ISR'; // Interrupt 6 Timer/Counter1 Compare Match A
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procedure TIM1_COMPB_ISR; external name 'TIM1_COMPB_ISR'; // Interrupt 7 Timer/Counter1 Compare Match B
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procedure TIM1_OVF_ISR; external name 'TIM1_OVF_ISR'; // Interrupt 8 Timer/Counter1 Overflow
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procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 9 Timer/Counter0 Compare Match A
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procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 10 Timer/Counter0 Compare Match B
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procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 11 Timer/Counter0 Overflow
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 12 Analog Comparator
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 13 ADC Conversion Complete
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procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 14 EEPROM Ready
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procedure USI_STR_ISR; external name 'USI_STR_ISR'; // Interrupt 15 USI START
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procedure USI_OVF_ISR; external name 'USI_OVF_ISR'; // Interrupt 16 USI Overflow
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp EXT_INT0_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp WATCHDOG_ISR
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rjmp TIM1_CAPT_ISR
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rjmp TIM1_COMPA_ISR
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rjmp TIM1_COMPB_ISR
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rjmp TIM1_OVF_ISR
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rjmp TIM0_COMPA_ISR
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rjmp TIM0_COMPB_ISR
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rjmp TIM0_OVF_ISR
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rjmp ANA_COMP_ISR
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rjmp ADC_ISR
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rjmp EE_RDY_ISR
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rjmp USI_STR_ISR
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rjmp USI_OVF_ISR
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{$i start.inc}
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.weak EXT_INT0_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak WATCHDOG_ISR
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.weak TIM1_CAPT_ISR
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.weak TIM1_COMPA_ISR
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.weak TIM1_COMPB_ISR
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.weak TIM1_OVF_ISR
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.weak TIM0_COMPA_ISR
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.weak TIM0_COMPB_ISR
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.weak TIM0_OVF_ISR
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.weak ANA_COMP_ISR
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.weak ADC_ISR
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.weak EE_RDY_ISR
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.weak USI_STR_ISR
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.weak USI_OVF_ISR
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.set EXT_INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set WATCHDOG_ISR, Default_IRQ_handler
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.set TIM1_CAPT_ISR, Default_IRQ_handler
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.set TIM1_COMPA_ISR, Default_IRQ_handler
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.set TIM1_COMPB_ISR, Default_IRQ_handler
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.set TIM1_OVF_ISR, Default_IRQ_handler
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.set TIM0_COMPA_ISR, Default_IRQ_handler
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.set TIM0_COMPB_ISR, Default_IRQ_handler
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.set TIM0_OVF_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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.set EE_RDY_ISR, Default_IRQ_handler
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.set USI_STR_ISR, Default_IRQ_handler
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.set USI_OVF_ISR, Default_IRQ_handler
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end;
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end.
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