mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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951 lines
30 KiB
ObjectPascal
951 lines
30 KiB
ObjectPascal
unit stm32f103xe;
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(**
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******************************************************************************
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* @file stm32f103xe.h
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* @author MCD Application Team
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F1xx devices.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral<92>s registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*)
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interface
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{$PACKRECORDS C}
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{$GOTO ON}
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{$SCOPEDENUMS ON}
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type
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TIRQn_Enum = (
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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MemoryManagement_IRQn = -12,
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BusFault_IRQn = -11,
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UsageFault_IRQn = -10,
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SVCall_IRQn = -5,
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DebugMonitor_IRQn = -4,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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WWDG_IRQn = 0,
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PVD_IRQn = 1,
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TAMPER_IRQn = 2,
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RTC_IRQn = 3,
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FLASH_IRQn = 4,
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RCC_IRQn = 5,
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EXTI0_IRQn = 6,
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EXTI1_IRQn = 7,
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EXTI2_IRQn = 8,
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EXTI3_IRQn = 9,
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EXTI4_IRQn = 10,
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DMA1_Channel1_IRQn = 11,
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DMA1_Channel2_IRQn = 12,
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DMA1_Channel3_IRQn = 13,
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DMA1_Channel4_IRQn = 14,
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DMA1_Channel5_IRQn = 15,
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DMA1_Channel6_IRQn = 16,
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DMA1_Channel7_IRQn = 17,
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ADC1_2_IRQn = 18,
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USB_HP_CAN1_TX_IRQn = 19,
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USB_LP_CAN1_RX0_IRQn = 20,
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CAN1_RX1_IRQn = 21,
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CAN1_SCE_IRQn = 22,
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EXTI9_5_IRQn = 23,
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TIM1_BRK_IRQn = 24,
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TIM1_UP_IRQn = 25,
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TIM1_TRG_COM_IRQn = 26,
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TIM1_CC_IRQn = 27,
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TIM2_IRQn = 28,
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TIM3_IRQn = 29,
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TIM4_IRQn = 30,
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I2C1_EV_IRQn = 31,
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I2C1_ER_IRQn = 32,
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I2C2_EV_IRQn = 33,
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I2C2_ER_IRQn = 34,
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SPI1_IRQn = 35,
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SPI2_IRQn = 36,
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USART1_IRQn = 37,
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USART2_IRQn = 38,
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USART3_IRQn = 39,
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EXTI15_10_IRQn = 40,
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RTC_Alarm_IRQn = 41,
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USBWakeUp_IRQn = 42,
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TIM8_BRK_IRQn = 43,
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TIM8_UP_IRQn = 44,
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TIM8_TRG_COM_IRQn = 45,
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TIM8_CC_IRQn = 46,
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ADC3_IRQn = 47,
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FSMC_IRQn = 48,
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SDIO_IRQn = 49,
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TIM5_IRQn = 50,
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SPI3_IRQn = 51,
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UART4_IRQn = 52,
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UART5_IRQn = 53,
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TIM6_IRQn = 54,
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TIM7_IRQn = 55,
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DMA2_Channel1_IRQn = 56,
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DMA2_Channel2_IRQn = 57,
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DMA2_Channel3_IRQn = 58,
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DMA2_Channel4_5_IRQn = 59
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);
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TADC_Registers = record
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SR : longword;
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CR1 : longword;
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CR2 : longword;
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SMPR1 : longword;
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SMPR2 : longword;
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JOFR1 : longword;
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JOFR2 : longword;
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JOFR3 : longword;
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JOFR4 : longword;
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HTR : longword;
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LTR : longword;
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SQR1 : longword;
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SQR2 : longword;
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SQR3 : longword;
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JSQR : longword;
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JDR1 : longword;
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JDR2 : longword;
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JDR3 : longword;
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JDR4 : longword;
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DR : longword;
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end;
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TADC_Common_Registers = record
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SR : longword;
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CR1 : longword;
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CR2 : longword;
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RESERVED : array[0..15] of longword;
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DR : longword;
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end;
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TBKP_Registers = record
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RESERVED0 : longword;
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DR1 : longword;
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DR2 : longword;
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DR3 : longword;
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DR4 : longword;
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DR5 : longword;
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DR6 : longword;
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DR7 : longword;
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DR8 : longword;
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DR9 : longword;
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DR10 : longword;
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RTCCR : longword;
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CR : longword;
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CSR : longword;
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RESERVED13 : array[0..1] of longword;
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DR11 : longword;
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DR12 : longword;
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DR13 : longword;
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DR14 : longword;
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DR15 : longword;
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DR16 : longword;
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DR17 : longword;
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DR18 : longword;
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DR19 : longword;
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DR20 : longword;
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DR21 : longword;
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DR22 : longword;
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DR23 : longword;
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DR24 : longword;
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DR25 : longword;
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DR26 : longword;
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DR27 : longword;
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DR28 : longword;
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DR29 : longword;
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DR30 : longword;
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DR31 : longword;
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DR32 : longword;
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DR33 : longword;
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DR34 : longword;
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DR35 : longword;
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DR36 : longword;
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DR37 : longword;
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DR38 : longword;
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DR39 : longword;
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DR40 : longword;
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DR41 : longword;
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DR42 : longword;
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end;
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TCAN_TxMailBox_Registers = record
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TIR : longword;
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TDTR : longword;
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TDLR : longword;
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TDHR : longword;
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end;
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TCAN_FIFOMailBox_Registers = record
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RIR : longword;
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RDTR : longword;
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RDLR : longword;
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RDHR : longword;
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end;
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TCAN_FilterRegister_Registers = record
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FR1 : longword;
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FR2 : longword;
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end;
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TCAN_Registers = record
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MCR : longword;
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MSR : longword;
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TSR : longword;
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RF0R : longword;
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RF1R : longword;
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IER : longword;
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ESR : longword;
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BTR : longword;
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RESERVED0 : array[0..87] of longword;
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sTxMailBox : array[0..2] of TCAN_TxMailBox_Registers;
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sFIFOMailBox : array[0..1] of TCAN_FIFOMailBox_Registers;
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RESERVED1 : array[0..11] of longword;
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FMR : longword;
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FM1R : longword;
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RESERVED2 : longword;
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FS1R : longword;
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RESERVED3 : longword;
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FFA1R : longword;
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RESERVED4 : longword;
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FA1R : longword;
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RESERVED5 : array[0..7] of longword;
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sFilterRegister : array[0..13] of TCAN_FilterRegister_Registers;
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end;
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TCRC_Registers = record
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DR : longword;
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IDR : byte;
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RESERVED0 : byte;
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RESERVED1 : word;
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CR : longword;
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end;
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TDAC_Registers = record
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CR : longword;
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SWTRIGR : longword;
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DHR12R1 : longword;
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DHR12L1 : longword;
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DHR8R1 : longword;
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DHR12R2 : longword;
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DHR12L2 : longword;
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DHR8R2 : longword;
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DHR12RD : longword;
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DHR12LD : longword;
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DHR8RD : longword;
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DOR1 : longword;
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DOR2 : longword;
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end;
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TDBGMCU_Registers = record
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IDCODE : longword;
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CR : longword;
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end;
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TDMA_Channel_Registers = record
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CCR : longword;
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CNDTR : longword;
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CPAR : longword;
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CMAR : longword;
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end;
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TDMA_Registers = record
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ISR : longword;
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IFCR : longword;
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end;
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TEXTI_Registers = record
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IMR : longword;
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EMR : longword;
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RTSR : longword;
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FTSR : longword;
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SWIER : longword;
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PR : longword;
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end;
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TFLASH_Registers = record
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ACR : longword;
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KEYR : longword;
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OPTKEYR : longword;
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SR : longword;
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CR : longword;
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AR : longword;
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RESERVED : longword;
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OBR : longword;
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WRPR : longword;
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end;
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TOB_Registers = record
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RDP : word;
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USER : word;
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Data0 : word;
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Data1 : word;
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WRP0 : word;
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WRP1 : word;
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WRP2 : word;
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WRP3 : word;
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end;
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TFSMC_Bank1_Registers = record
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BTCR : array[0..7] of longword;
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end;
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TFSMC_Bank1E_Registers = record
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BWTR : array[0..6] of longword;
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end;
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TFSMC_Bank2_3_Registers = record
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PCR2 : longword;
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SR2 : longword;
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PMEM2 : longword;
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PATT2 : longword;
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RESERVED0 : longword;
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ECCR2 : longword;
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RESERVED1 : longword;
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RESERVED2 : longword;
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PCR3 : longword;
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SR3 : longword;
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PMEM3 : longword;
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PATT3 : longword;
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RESERVED3 : longword;
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ECCR3 : longword;
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end;
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TFSMC_Bank4_Registers = record
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PCR4 : longword;
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SR4 : longword;
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PMEM4 : longword;
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PATT4 : longword;
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PIO4 : longword;
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end;
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TGPIO_Registers = record
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CRL : longword;
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CRH : longword;
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IDR : longword;
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ODR : longword;
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BSRR : longword;
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BRR : longword;
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LCKR : longword;
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end;
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TAFIO_Registers = record
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EVCR : longword;
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MAPR : longword;
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EXTICR : array[0..3] of longword;
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RESERVED0 : longword;
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MAPR2 : longword;
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end;
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TI2C_Registers = record
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CR1 : longword;
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CR2 : longword;
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OAR1 : longword;
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OAR2 : longword;
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DR : longword;
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SR1 : longword;
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SR2 : longword;
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CCR : longword;
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TRISE : longword;
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end;
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TIWDG_Registers = record
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KR : longword;
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PR : longword;
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RLR : longword;
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SR : longword;
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end;
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TPWR_Registers = record
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CR : longword;
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CSR : longword;
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end;
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TRCC_Registers = record
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CR : longword;
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CFGR : longword;
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CIR : longword;
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APB2RSTR : longword;
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APB1RSTR : longword;
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AHBENR : longword;
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APB2ENR : longword;
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APB1ENR : longword;
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BDCR : longword;
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CSR : longword;
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end;
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TRTC_Registers = record
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CRH : longword;
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CRL : longword;
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PRLH : longword;
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PRLL : longword;
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DIVH : longword;
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DIVL : longword;
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CNTH : longword;
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CNTL : longword;
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ALRH : longword;
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ALRL : longword;
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end;
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TSDIO_Registers = record
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POWER : longword;
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CLKCR : longword;
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ARG : longword;
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CMD : longword;
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RESPCMD : longword;
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RESP1 : longword;
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RESP2 : longword;
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RESP3 : longword;
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RESP4 : longword;
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DTIMER : longword;
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DLEN : longword;
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DCTRL : longword;
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DCOUNT : longword;
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STA : longword;
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ICR : longword;
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MASK : longword;
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RESERVED0 : array[0..1] of longword;
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FIFOCNT : longword;
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RESERVED1 : array[0..12] of longword;
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FIFO : longword;
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end;
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TSPI_Registers = record
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CR1 : longword;
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CR2 : longword;
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SR : longword;
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DR : longword;
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CRCPR : longword;
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RXCRCR : longword;
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TXCRCR : longword;
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I2SCFGR : longword;
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I2SPR : longword;
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end;
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TTIM_Registers = record
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CR1 : longword;
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CR2 : longword;
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SMCR : longword;
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DIER : longword;
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SR : longword;
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EGR : longword;
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CCMR1 : longword;
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CCMR2 : longword;
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CCER : longword;
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CNT : longword;
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PSC : longword;
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ARR : longword;
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RCR : longword;
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CCR1 : longword;
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CCR2 : longword;
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CCR3 : longword;
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CCR4 : longword;
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BDTR : longword;
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DCR : longword;
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DMAR : longword;
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&OR : longword;
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end;
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TUSART_Registers = record
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SR : longword;
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DR : longword;
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BRR : longword;
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CR1 : longword;
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CR2 : longword;
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CR3 : longword;
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GTPR : longword;
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end;
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TUSB_Registers = record
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EP0R : word;
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RESERVED0 : word;
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EP1R : word;
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RESERVED1 : word;
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EP2R : word;
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RESERVED2 : word;
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EP3R : word;
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RESERVED3 : word;
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EP4R : word;
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RESERVED4 : word;
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EP5R : word;
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RESERVED5 : word;
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EP6R : word;
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RESERVED6 : word;
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EP7R : word;
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RESERVED7 : array[0..16] of word;
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CNTR : word;
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RESERVED8 : word;
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ISTR : word;
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RESERVED9 : word;
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FNR : word;
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RESERVEDA : word;
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DADDR : word;
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RESERVEDB : word;
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BTABLE : word;
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RESERVEDC : word;
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end;
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TWWDG_Registers = record
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CR : longword;
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CFR : longword;
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SR : longword;
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end;
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const
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FLASH_BASE = $08000000;
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SRAM_BASE = $20000000;
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PERIPH_BASE = $40000000;
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SRAM_BB_BASE = $22000000;
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PERIPH_BB_BASE= $42000000;
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FSMC_BASE = $60000000;
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FSMC_R_BASE = $A0000000;
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APB1PERIPH_BASE= PERIPH_BASE;
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APB2PERIPH_BASE= PERIPH_BASE + $00010000;
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AHBPERIPH_BASE= PERIPH_BASE + $00020000;
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TIM2_BASE = APB1PERIPH_BASE + $00000000;
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TIM3_BASE = APB1PERIPH_BASE + $00000400;
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TIM4_BASE = APB1PERIPH_BASE + $00000800;
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TIM5_BASE = APB1PERIPH_BASE + $00000C00;
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TIM6_BASE = APB1PERIPH_BASE + $00001000;
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TIM7_BASE = APB1PERIPH_BASE + $00001400;
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RTC_BASE = APB1PERIPH_BASE + $00002800;
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WWDG_BASE = APB1PERIPH_BASE + $00002C00;
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IWDG_BASE = APB1PERIPH_BASE + $00003000;
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SPI2_BASE = APB1PERIPH_BASE + $00003800;
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SPI3_BASE = APB1PERIPH_BASE + $00003C00;
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USART2_BASE = APB1PERIPH_BASE + $00004400;
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USART3_BASE = APB1PERIPH_BASE + $00004800;
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UART4_BASE = APB1PERIPH_BASE + $00004C00;
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UART5_BASE = APB1PERIPH_BASE + $00005000;
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I2C1_BASE = APB1PERIPH_BASE + $00005400;
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I2C2_BASE = APB1PERIPH_BASE + $00005800;
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CAN1_BASE = APB1PERIPH_BASE + $00006400;
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BKP_BASE = APB1PERIPH_BASE + $00006C00;
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PWR_BASE = APB1PERIPH_BASE + $00007000;
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DAC_BASE = APB1PERIPH_BASE + $00007400;
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AFIO_BASE = APB2PERIPH_BASE + $00000000;
|
|
EXTI_BASE = APB2PERIPH_BASE + $00000400;
|
|
GPIOA_BASE = APB2PERIPH_BASE + $00000800;
|
|
GPIOB_BASE = APB2PERIPH_BASE + $00000C00;
|
|
GPIOC_BASE = APB2PERIPH_BASE + $00001000;
|
|
GPIOD_BASE = APB2PERIPH_BASE + $00001400;
|
|
GPIOE_BASE = APB2PERIPH_BASE + $00001800;
|
|
GPIOF_BASE = APB2PERIPH_BASE + $00001C00;
|
|
GPIOG_BASE = APB2PERIPH_BASE + $00002000;
|
|
ADC1_BASE = APB2PERIPH_BASE + $00002400;
|
|
ADC2_BASE = APB2PERIPH_BASE + $00002800;
|
|
TIM1_BASE = APB2PERIPH_BASE + $00002C00;
|
|
SPI1_BASE = APB2PERIPH_BASE + $00003000;
|
|
TIM8_BASE = APB2PERIPH_BASE + $00003400;
|
|
USART1_BASE = APB2PERIPH_BASE + $00003800;
|
|
ADC3_BASE = APB2PERIPH_BASE + $00003C00;
|
|
SDIO_BASE = PERIPH_BASE + $00018000;
|
|
DMA1_BASE = AHBPERIPH_BASE + $00000000;
|
|
DMA1_Channel1_BASE= AHBPERIPH_BASE + $00000008;
|
|
DMA1_Channel2_BASE= AHBPERIPH_BASE + $0000001C;
|
|
DMA1_Channel3_BASE= AHBPERIPH_BASE + $00000030;
|
|
DMA1_Channel4_BASE= AHBPERIPH_BASE + $00000044;
|
|
DMA1_Channel5_BASE= AHBPERIPH_BASE + $00000058;
|
|
DMA1_Channel6_BASE= AHBPERIPH_BASE + $0000006C;
|
|
DMA1_Channel7_BASE= AHBPERIPH_BASE + $00000080;
|
|
DMA2_BASE = AHBPERIPH_BASE + $00000400;
|
|
DMA2_Channel1_BASE= AHBPERIPH_BASE + $00000408;
|
|
DMA2_Channel2_BASE= AHBPERIPH_BASE + $0000041C;
|
|
DMA2_Channel3_BASE= AHBPERIPH_BASE + $00000430;
|
|
DMA2_Channel4_BASE= AHBPERIPH_BASE + $00000444;
|
|
DMA2_Channel5_BASE= AHBPERIPH_BASE + $00000458;
|
|
RCC_BASE = AHBPERIPH_BASE + $00001000;
|
|
CRC_BASE = AHBPERIPH_BASE + $00003000;
|
|
FLASH_R_BASE = AHBPERIPH_BASE + $00002000;
|
|
FLASHSIZE_BASE= $1FFFF7E0;
|
|
UID_BASE = $1FFFF7E8;
|
|
OB_BASE = $1FFFF800;
|
|
FSMC_BANK1_R_BASE= FSMC_R_BASE + $00000000;
|
|
FSMC_BANK1E_R_BASE= FSMC_R_BASE + $00000104;
|
|
FSMC_BANK2_3_R_BASE= FSMC_R_BASE + $00000060;
|
|
FSMC_BANK4_R_BASE= FSMC_R_BASE + $000000A0;
|
|
DBGMCU_BASE = $E0042000;
|
|
USB_BASE = APB1PERIPH_BASE + $00005C00;
|
|
|
|
var
|
|
TIM2 : TTIM_Registers absolute TIM2_BASE;
|
|
TIM3 : TTIM_Registers absolute TIM3_BASE;
|
|
TIM4 : TTIM_Registers absolute TIM4_BASE;
|
|
TIM5 : TTIM_Registers absolute TIM5_BASE;
|
|
TIM6 : TTIM_Registers absolute TIM6_BASE;
|
|
TIM7 : TTIM_Registers absolute TIM7_BASE;
|
|
RTC : TRTC_Registers absolute RTC_BASE;
|
|
WWDG : TWWDG_Registers absolute WWDG_BASE;
|
|
IWDG : TIWDG_Registers absolute IWDG_BASE;
|
|
SPI2 : TSPI_Registers absolute SPI2_BASE;
|
|
SPI3 : TSPI_Registers absolute SPI3_BASE;
|
|
USART2 : TUSART_Registers absolute USART2_BASE;
|
|
USART3 : TUSART_Registers absolute USART3_BASE;
|
|
UART4 : TUSART_Registers absolute UART4_BASE;
|
|
UART5 : TUSART_Registers absolute UART5_BASE;
|
|
I2C1 : TI2C_Registers absolute I2C1_BASE;
|
|
I2C2 : TI2C_Registers absolute I2C2_BASE;
|
|
USB : TUSB_Registers absolute USB_BASE;
|
|
CAN1 : TCAN_Registers absolute CAN1_BASE;
|
|
BKP : TBKP_Registers absolute BKP_BASE;
|
|
PWR : TPWR_Registers absolute PWR_BASE;
|
|
DAC1 : TDAC_Registers absolute DAC_BASE;
|
|
DAC : TDAC_Registers absolute DAC_BASE;
|
|
AFIO : TAFIO_Registers absolute AFIO_BASE;
|
|
EXTI : TEXTI_Registers absolute EXTI_BASE;
|
|
GPIOA : TGPIO_Registers absolute GPIOA_BASE;
|
|
GPIOB : TGPIO_Registers absolute GPIOB_BASE;
|
|
GPIOC : TGPIO_Registers absolute GPIOC_BASE;
|
|
GPIOD : TGPIO_Registers absolute GPIOD_BASE;
|
|
GPIOE : TGPIO_Registers absolute GPIOE_BASE;
|
|
GPIOF : TGPIO_Registers absolute GPIOF_BASE;
|
|
GPIOG : TGPIO_Registers absolute GPIOG_BASE;
|
|
ADC1 : TADC_Registers absolute ADC1_BASE;
|
|
ADC2 : TADC_Registers absolute ADC2_BASE;
|
|
ADC3 : TADC_Registers absolute ADC3_BASE;
|
|
ADC12_COMMON : TADC_Common_Registers absolute ADC1_BASE;
|
|
TIM1 : TTIM_Registers absolute TIM1_BASE;
|
|
SPI1 : TSPI_Registers absolute SPI1_BASE;
|
|
TIM8 : TTIM_Registers absolute TIM8_BASE;
|
|
USART1 : TUSART_Registers absolute USART1_BASE;
|
|
SDIO : TSDIO_Registers absolute SDIO_BASE;
|
|
DMA1 : TDMA_Registers absolute DMA1_BASE;
|
|
DMA2 : TDMA_Registers absolute DMA2_BASE;
|
|
DMA1_Channel1 : TDMA_Channel_Registers absolute DMA1_Channel1_BASE;
|
|
DMA1_Channel2 : TDMA_Channel_Registers absolute DMA1_Channel2_BASE;
|
|
DMA1_Channel3 : TDMA_Channel_Registers absolute DMA1_Channel3_BASE;
|
|
DMA1_Channel4 : TDMA_Channel_Registers absolute DMA1_Channel4_BASE;
|
|
DMA1_Channel5 : TDMA_Channel_Registers absolute DMA1_Channel5_BASE;
|
|
DMA1_Channel6 : TDMA_Channel_Registers absolute DMA1_Channel6_BASE;
|
|
DMA1_Channel7 : TDMA_Channel_Registers absolute DMA1_Channel7_BASE;
|
|
DMA2_Channel1 : TDMA_Channel_Registers absolute DMA2_Channel1_BASE;
|
|
DMA2_Channel2 : TDMA_Channel_Registers absolute DMA2_Channel2_BASE;
|
|
DMA2_Channel3 : TDMA_Channel_Registers absolute DMA2_Channel3_BASE;
|
|
DMA2_Channel4 : TDMA_Channel_Registers absolute DMA2_Channel4_BASE;
|
|
DMA2_Channel5 : TDMA_Channel_Registers absolute DMA2_Channel5_BASE;
|
|
RCC : TRCC_Registers absolute RCC_BASE;
|
|
CRC : TCRC_Registers absolute CRC_BASE;
|
|
FLASH : TFLASH_Registers absolute FLASH_R_BASE;
|
|
OB : TOB_Registers absolute OB_BASE;
|
|
FSMC_Bank1 : TFSMC_Bank1_Registers absolute FSMC_BANK1_R_BASE;
|
|
FSMC_Bank1E : TFSMC_Bank1E_Registers absolute FSMC_BANK1E_R_BASE;
|
|
FSMC_Bank2_3 : TFSMC_Bank2_3_Registers absolute FSMC_BANK2_3_R_BASE;
|
|
FSMC_Bank4 : TFSMC_Bank4_Registers absolute FSMC_BANK4_R_BASE;
|
|
DBGMCU : TDBGMCU_Registers absolute DBGMCU_BASE;
|
|
|
|
implementation
|
|
|
|
procedure NonMaskableInt_Handler; external name 'NonMaskableInt_Handler';
|
|
procedure HardFault_Handler; external name 'HardFault_Handler';
|
|
procedure MemoryManagement_Handler; external name 'MemoryManagement_Handler';
|
|
procedure BusFault_Handler; external name 'BusFault_Handler';
|
|
procedure UsageFault_Handler; external name 'UsageFault_Handler';
|
|
procedure SVCall_Handler; external name 'SVCall_Handler';
|
|
procedure DebugMonitor_Handler; external name 'DebugMonitor_Handler';
|
|
procedure PendSV_Handler; external name 'PendSV_Handler';
|
|
procedure SysTick_Handler; external name 'SysTick_Handler';
|
|
procedure WWDG_Handler; external name 'WWDG_Handler';
|
|
procedure PVD_Handler; external name 'PVD_Handler';
|
|
procedure TAMPER_Handler; external name 'TAMPER_Handler';
|
|
procedure RTC_Handler; external name 'RTC_Handler';
|
|
procedure FLASH_Handler; external name 'FLASH_Handler';
|
|
procedure RCC_Handler; external name 'RCC_Handler';
|
|
procedure EXTI0_Handler; external name 'EXTI0_Handler';
|
|
procedure EXTI1_Handler; external name 'EXTI1_Handler';
|
|
procedure EXTI2_Handler; external name 'EXTI2_Handler';
|
|
procedure EXTI3_Handler; external name 'EXTI3_Handler';
|
|
procedure EXTI4_Handler; external name 'EXTI4_Handler';
|
|
procedure DMA1_Channel1_Handler; external name 'DMA1_Channel1_Handler';
|
|
procedure DMA1_Channel2_Handler; external name 'DMA1_Channel2_Handler';
|
|
procedure DMA1_Channel3_Handler; external name 'DMA1_Channel3_Handler';
|
|
procedure DMA1_Channel4_Handler; external name 'DMA1_Channel4_Handler';
|
|
procedure DMA1_Channel5_Handler; external name 'DMA1_Channel5_Handler';
|
|
procedure DMA1_Channel6_Handler; external name 'DMA1_Channel6_Handler';
|
|
procedure DMA1_Channel7_Handler; external name 'DMA1_Channel7_Handler';
|
|
procedure ADC1_2_Handler; external name 'ADC1_2_Handler';
|
|
procedure USB_HP_CAN1_TX_Handler; external name 'USB_HP_CAN1_TX_Handler';
|
|
procedure USB_LP_CAN1_RX0_Handler; external name 'USB_LP_CAN1_RX0_Handler';
|
|
procedure CAN1_RX1_Handler; external name 'CAN1_RX1_Handler';
|
|
procedure CAN1_SCE_Handler; external name 'CAN1_SCE_Handler';
|
|
procedure EXTI9_5_Handler; external name 'EXTI9_5_Handler';
|
|
procedure TIM1_BRK_Handler; external name 'TIM1_BRK_Handler';
|
|
procedure TIM1_UP_Handler; external name 'TIM1_UP_Handler';
|
|
procedure TIM1_TRG_COM_Handler; external name 'TIM1_TRG_COM_Handler';
|
|
procedure TIM1_CC_Handler; external name 'TIM1_CC_Handler';
|
|
procedure TIM2_Handler; external name 'TIM2_Handler';
|
|
procedure TIM3_Handler; external name 'TIM3_Handler';
|
|
procedure TIM4_Handler; external name 'TIM4_Handler';
|
|
procedure I2C1_EV_Handler; external name 'I2C1_EV_Handler';
|
|
procedure I2C1_ER_Handler; external name 'I2C1_ER_Handler';
|
|
procedure I2C2_EV_Handler; external name 'I2C2_EV_Handler';
|
|
procedure I2C2_ER_Handler; external name 'I2C2_ER_Handler';
|
|
procedure SPI1_Handler; external name 'SPI1_Handler';
|
|
procedure SPI2_Handler; external name 'SPI2_Handler';
|
|
procedure USART1_Handler; external name 'USART1_Handler';
|
|
procedure USART2_Handler; external name 'USART2_Handler';
|
|
procedure USART3_Handler; external name 'USART3_Handler';
|
|
procedure EXTI15_10_Handler; external name 'EXTI15_10_Handler';
|
|
procedure RTC_Alarm_Handler; external name 'RTC_Alarm_Handler';
|
|
procedure USBWakeUp_Handler; external name 'USBWakeUp_Handler';
|
|
procedure TIM8_BRK_Handler; external name 'TIM8_BRK_Handler';
|
|
procedure TIM8_UP_Handler; external name 'TIM8_UP_Handler';
|
|
procedure TIM8_TRG_COM_Handler; external name 'TIM8_TRG_COM_Handler';
|
|
procedure TIM8_CC_Handler; external name 'TIM8_CC_Handler';
|
|
procedure ADC3_Handler; external name 'ADC3_Handler';
|
|
procedure FSMC_Handler; external name 'FSMC_Handler';
|
|
procedure SDIO_Handler; external name 'SDIO_Handler';
|
|
procedure TIM5_Handler; external name 'TIM5_Handler';
|
|
procedure SPI3_Handler; external name 'SPI3_Handler';
|
|
procedure UART4_Handler; external name 'UART4_Handler';
|
|
procedure UART5_Handler; external name 'UART5_Handler';
|
|
procedure TIM6_Handler; external name 'TIM6_Handler';
|
|
procedure TIM7_Handler; external name 'TIM7_Handler';
|
|
procedure DMA2_Channel1_Handler; external name 'DMA2_Channel1_Handler';
|
|
procedure DMA2_Channel2_Handler; external name 'DMA2_Channel2_Handler';
|
|
procedure DMA2_Channel3_Handler; external name 'DMA2_Channel3_Handler';
|
|
procedure DMA2_Channel4_5_Handler; external name 'DMA2_Channel4_5_Handler';
|
|
|
|
|
|
{$i cortexm3_start.inc}
|
|
|
|
procedure Vectors; assembler; nostackframe;
|
|
label interrupt_vectors;
|
|
asm
|
|
.section ".init.interrupt_vectors"
|
|
interrupt_vectors:
|
|
.long _stack_top
|
|
.long Startup
|
|
.long NonMaskableInt_Handler
|
|
.long HardFault_Handler
|
|
.long MemoryManagement_Handler
|
|
.long BusFault_Handler
|
|
.long UsageFault_Handler
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long SVCall_Handler
|
|
.long DebugMonitor_Handler
|
|
.long 0
|
|
.long PendSV_Handler
|
|
.long SysTick_Handler
|
|
.long WWDG_Handler
|
|
.long PVD_Handler
|
|
.long TAMPER_Handler
|
|
.long RTC_Handler
|
|
.long FLASH_Handler
|
|
.long RCC_Handler
|
|
.long EXTI0_Handler
|
|
.long EXTI1_Handler
|
|
.long EXTI2_Handler
|
|
.long EXTI3_Handler
|
|
.long EXTI4_Handler
|
|
.long DMA1_Channel1_Handler
|
|
.long DMA1_Channel2_Handler
|
|
.long DMA1_Channel3_Handler
|
|
.long DMA1_Channel4_Handler
|
|
.long DMA1_Channel5_Handler
|
|
.long DMA1_Channel6_Handler
|
|
.long DMA1_Channel7_Handler
|
|
.long ADC1_2_Handler
|
|
.long USB_HP_CAN1_TX_Handler
|
|
.long USB_LP_CAN1_RX0_Handler
|
|
.long CAN1_RX1_Handler
|
|
.long CAN1_SCE_Handler
|
|
.long EXTI9_5_Handler
|
|
.long TIM1_BRK_Handler
|
|
.long TIM1_UP_Handler
|
|
.long TIM1_TRG_COM_Handler
|
|
.long TIM1_CC_Handler
|
|
.long TIM2_Handler
|
|
.long TIM3_Handler
|
|
.long TIM4_Handler
|
|
.long I2C1_EV_Handler
|
|
.long I2C1_ER_Handler
|
|
.long I2C2_EV_Handler
|
|
.long I2C2_ER_Handler
|
|
.long SPI1_Handler
|
|
.long SPI2_Handler
|
|
.long USART1_Handler
|
|
.long USART2_Handler
|
|
.long USART3_Handler
|
|
.long EXTI15_10_Handler
|
|
.long RTC_Alarm_Handler
|
|
.long USBWakeUp_Handler
|
|
.long TIM8_BRK_Handler
|
|
.long TIM8_UP_Handler
|
|
.long TIM8_TRG_COM_Handler
|
|
.long TIM8_CC_Handler
|
|
.long ADC3_Handler
|
|
.long FSMC_Handler
|
|
.long SDIO_Handler
|
|
.long TIM5_Handler
|
|
.long SPI3_Handler
|
|
.long UART4_Handler
|
|
.long UART5_Handler
|
|
.long TIM6_Handler
|
|
.long TIM7_Handler
|
|
.long DMA2_Channel1_Handler
|
|
.long DMA2_Channel2_Handler
|
|
.long DMA2_Channel3_Handler
|
|
.long DMA2_Channel4_5_Handler
|
|
|
|
.weak NonMaskableInt_Handler
|
|
.weak HardFault_Handler
|
|
.weak MemoryManagement_Handler
|
|
.weak BusFault_Handler
|
|
.weak UsageFault_Handler
|
|
.weak SVCall_Handler
|
|
.weak DebugMonitor_Handler
|
|
.weak PendSV_Handler
|
|
.weak SysTick_Handler
|
|
.weak WWDG_Handler
|
|
.weak PVD_Handler
|
|
.weak TAMPER_Handler
|
|
.weak RTC_Handler
|
|
.weak FLASH_Handler
|
|
.weak RCC_Handler
|
|
.weak EXTI0_Handler
|
|
.weak EXTI1_Handler
|
|
.weak EXTI2_Handler
|
|
.weak EXTI3_Handler
|
|
.weak EXTI4_Handler
|
|
.weak DMA1_Channel1_Handler
|
|
.weak DMA1_Channel2_Handler
|
|
.weak DMA1_Channel3_Handler
|
|
.weak DMA1_Channel4_Handler
|
|
.weak DMA1_Channel5_Handler
|
|
.weak DMA1_Channel6_Handler
|
|
.weak DMA1_Channel7_Handler
|
|
.weak ADC1_2_Handler
|
|
.weak USB_HP_CAN1_TX_Handler
|
|
.weak USB_LP_CAN1_RX0_Handler
|
|
.weak CAN1_RX1_Handler
|
|
.weak CAN1_SCE_Handler
|
|
.weak EXTI9_5_Handler
|
|
.weak TIM1_BRK_Handler
|
|
.weak TIM1_UP_Handler
|
|
.weak TIM1_TRG_COM_Handler
|
|
.weak TIM1_CC_Handler
|
|
.weak TIM2_Handler
|
|
.weak TIM3_Handler
|
|
.weak TIM4_Handler
|
|
.weak I2C1_EV_Handler
|
|
.weak I2C1_ER_Handler
|
|
.weak I2C2_EV_Handler
|
|
.weak I2C2_ER_Handler
|
|
.weak SPI1_Handler
|
|
.weak SPI2_Handler
|
|
.weak USART1_Handler
|
|
.weak USART2_Handler
|
|
.weak USART3_Handler
|
|
.weak EXTI15_10_Handler
|
|
.weak RTC_Alarm_Handler
|
|
.weak USBWakeUp_Handler
|
|
.weak TIM8_BRK_Handler
|
|
.weak TIM8_UP_Handler
|
|
.weak TIM8_TRG_COM_Handler
|
|
.weak TIM8_CC_Handler
|
|
.weak ADC3_Handler
|
|
.weak FSMC_Handler
|
|
.weak SDIO_Handler
|
|
.weak TIM5_Handler
|
|
.weak SPI3_Handler
|
|
.weak UART4_Handler
|
|
.weak UART5_Handler
|
|
.weak TIM6_Handler
|
|
.weak TIM7_Handler
|
|
.weak DMA2_Channel1_Handler
|
|
.weak DMA2_Channel2_Handler
|
|
.weak DMA2_Channel3_Handler
|
|
.weak DMA2_Channel4_5_Handler
|
|
|
|
.set NonMaskableInt_Handler, Haltproc
|
|
.set HardFault_Handler, Haltproc
|
|
.set MemoryManagement_Handler, Haltproc
|
|
.set BusFault_Handler, Haltproc
|
|
.set UsageFault_Handler, Haltproc
|
|
.set SVCall_Handler, Haltproc
|
|
.set DebugMonitor_Handler, Haltproc
|
|
.set PendSV_Handler, Haltproc
|
|
.set SysTick_Handler, Haltproc
|
|
.set WWDG_Handler, Haltproc
|
|
.set PVD_Handler, Haltproc
|
|
.set TAMPER_Handler, Haltproc
|
|
.set RTC_Handler, Haltproc
|
|
.set FLASH_Handler, Haltproc
|
|
.set RCC_Handler, Haltproc
|
|
.set EXTI0_Handler, Haltproc
|
|
.set EXTI1_Handler, Haltproc
|
|
.set EXTI2_Handler, Haltproc
|
|
.set EXTI3_Handler, Haltproc
|
|
.set EXTI4_Handler, Haltproc
|
|
.set DMA1_Channel1_Handler, Haltproc
|
|
.set DMA1_Channel2_Handler, Haltproc
|
|
.set DMA1_Channel3_Handler, Haltproc
|
|
.set DMA1_Channel4_Handler, Haltproc
|
|
.set DMA1_Channel5_Handler, Haltproc
|
|
.set DMA1_Channel6_Handler, Haltproc
|
|
.set DMA1_Channel7_Handler, Haltproc
|
|
.set ADC1_2_Handler, Haltproc
|
|
.set USB_HP_CAN1_TX_Handler, Haltproc
|
|
.set USB_LP_CAN1_RX0_Handler, Haltproc
|
|
.set CAN1_RX1_Handler, Haltproc
|
|
.set CAN1_SCE_Handler, Haltproc
|
|
.set EXTI9_5_Handler, Haltproc
|
|
.set TIM1_BRK_Handler, Haltproc
|
|
.set TIM1_UP_Handler, Haltproc
|
|
.set TIM1_TRG_COM_Handler, Haltproc
|
|
.set TIM1_CC_Handler, Haltproc
|
|
.set TIM2_Handler, Haltproc
|
|
.set TIM3_Handler, Haltproc
|
|
.set TIM4_Handler, Haltproc
|
|
.set I2C1_EV_Handler, Haltproc
|
|
.set I2C1_ER_Handler, Haltproc
|
|
.set I2C2_EV_Handler, Haltproc
|
|
.set I2C2_ER_Handler, Haltproc
|
|
.set SPI1_Handler, Haltproc
|
|
.set SPI2_Handler, Haltproc
|
|
.set USART1_Handler, Haltproc
|
|
.set USART2_Handler, Haltproc
|
|
.set USART3_Handler, Haltproc
|
|
.set EXTI15_10_Handler, Haltproc
|
|
.set RTC_Alarm_Handler, Haltproc
|
|
.set USBWakeUp_Handler, Haltproc
|
|
.set TIM8_BRK_Handler, Haltproc
|
|
.set TIM8_UP_Handler, Haltproc
|
|
.set TIM8_TRG_COM_Handler, Haltproc
|
|
.set TIM8_CC_Handler, Haltproc
|
|
.set ADC3_Handler, Haltproc
|
|
.set FSMC_Handler, Haltproc
|
|
.set SDIO_Handler, Haltproc
|
|
.set TIM5_Handler, Haltproc
|
|
.set SPI3_Handler, Haltproc
|
|
.set UART4_Handler, Haltproc
|
|
.set UART5_Handler, Haltproc
|
|
.set TIM6_Handler, Haltproc
|
|
.set TIM7_Handler, Haltproc
|
|
.set DMA2_Channel1_Handler, Haltproc
|
|
.set DMA2_Channel2_Handler, Haltproc
|
|
.set DMA2_Channel3_Handler, Haltproc
|
|
.set DMA2_Channel4_5_Handler, Haltproc
|
|
|
|
.text
|
|
end;
|
|
end.
|