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https://gitlab.com/freepascal.org/fpc/source.git
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787 lines
25 KiB
ObjectPascal
787 lines
25 KiB
ObjectPascal
unit stm32g071xx;
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(**
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******************************************************************************
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* @file stm32g071xx.h
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for stm32g071xx devices.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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* - Peripheral's registers declarations and bits definition
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* - Macros to access peripheral's registers hardware
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*)
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interface
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{$PACKRECORDS C}
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{$GOTO ON}
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{$SCOPEDENUMS ON}
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type
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TIRQn_Enum = (
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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SVC_IRQn = -5,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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WWDG_IRQn = 0,
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PVD_IRQn = 1,
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RTC_TAMP_IRQn = 2,
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FLASH_IRQn = 3,
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RCC_IRQn = 4,
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EXTI0_1_IRQn = 5,
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EXTI2_3_IRQn = 6,
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EXTI4_15_IRQn = 7,
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UCPD1_2_IRQn = 8,
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DMA1_Channel1_IRQn = 9,
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DMA1_Channel2_3_IRQn = 10,
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DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11,
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ADC1_COMP_IRQn = 12,
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TIM1_BRK_UP_TRG_COM_IRQn = 13,
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TIM1_CC_IRQn = 14,
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TIM2_IRQn = 15,
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TIM3_IRQn = 16,
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TIM6_DAC_LPTIM1_IRQn = 17,
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TIM7_LPTIM2_IRQn = 18,
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TIM14_IRQn = 19,
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TIM15_IRQn = 20,
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TIM16_IRQn = 21,
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TIM17_IRQn = 22,
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I2C1_IRQn = 23,
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I2C2_IRQn = 24,
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SPI1_IRQn = 25,
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SPI2_IRQn = 26,
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USART1_IRQn = 27,
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USART2_IRQn = 28,
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USART3_4_LPUART1_IRQn = 29,
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CEC_IRQn = 30
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);
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TADC_Registers = record
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ISR : longword;
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IER : longword;
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CR : longword;
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CFGR1 : longword;
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CFGR2 : longword;
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SMPR : longword;
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RESERVED1 : longword;
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RESERVED2 : longword;
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TR1 : longword;
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TR2 : longword;
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CHSELR : longword;
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TR3 : longword;
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RESERVED3 : array[0..3] of longword;
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DR : longword;
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RESERVED4 : array[0..22] of longword;
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AWD2CR : longword;
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AWD3CR : longword;
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RESERVED5 : array[0..2] of longword;
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CALFACT : longword;
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end;
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TADC_Common_Registers = record
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CCR : longword;
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end;
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TCEC_Registers = record
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CR : longword;
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CFGR : longword;
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TXDR : longword;
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RXDR : longword;
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ISR : longword;
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IER : longword;
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end;
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TCOMP_Registers = record
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CSR : longword;
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end;
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TCOMP_Common_Registers = record
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CSR_ODD : longword;
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CSR_EVEN : longword;
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end;
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TCRC_Registers = record
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DR : longword;
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IDR : longword;
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CR : longword;
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RESERVED1 : longword;
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INIT : longword;
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POL : longword;
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end;
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TDAC_Registers = record
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CR : longword;
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SWTRIGR : longword;
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DHR12R1 : longword;
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DHR12L1 : longword;
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DHR8R1 : longword;
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DHR12R2 : longword;
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DHR12L2 : longword;
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DHR8R2 : longword;
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DHR12RD : longword;
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DHR12LD : longword;
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DHR8RD : longword;
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DOR1 : longword;
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DOR2 : longword;
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SR : longword;
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CCR : longword;
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MCR : longword;
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SHSR1 : longword;
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SHSR2 : longword;
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SHHR : longword;
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SHRR : longword;
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end;
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TDBG_Registers = record
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IDCODE : longword;
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CR : longword;
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APBFZ1 : longword;
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APBFZ2 : longword;
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end;
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TDMA_Channel_Registers = record
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CCR : longword;
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CNDTR : longword;
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CPAR : longword;
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CMAR : longword;
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end;
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TDMA_Registers = record
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ISR : longword;
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IFCR : longword;
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end;
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TDMAMUX_Channel_Registers = record
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CCR : longword;
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end;
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TDMAMUX_ChannelStatus_Registers = record
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CSR : longword;
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CFR : longword;
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end;
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TDMAMUX_RequestGen_Registers = record
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RGCR : longword;
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end;
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TDMAMUX_RequestGenStatus_Registers = record
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RGSR : longword;
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RGCFR : longword;
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end;
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TEXTI_Registers = record
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RTSR1 : longword;
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FTSR1 : longword;
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SWIER1 : longword;
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RPR1 : longword;
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FPR1 : longword;
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RESERVED1 : array[0..2] of longword;
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RESERVED2 : array[0..4] of longword;
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RESERVED3 : array[0..10] of longword;
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EXTICR : array[0..3] of longword;
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RESERVED4 : array[0..3] of longword;
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IMR1 : longword;
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EMR1 : longword;
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RESERVED5 : array[0..1] of longword;
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IMR2 : longword;
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EMR2 : longword;
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end;
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TFLASH_Registers = record
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ACR : longword;
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RESERVED1 : longword;
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KEYR : longword;
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OPTKEYR : longword;
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SR : longword;
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CR : longword;
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ECCR : longword;
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RESERVED2 : longword;
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OPTR : longword;
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PCROP1ASR : longword;
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PCROP1AER : longword;
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WRP1AR : longword;
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WRP1BR : longword;
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PCROP1BSR : longword;
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PCROP1BER : longword;
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RESERVED3 : array[0..16] of longword;
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SECR : longword;
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end;
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TGPIO_Registers = record
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MODER : longword;
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OTYPER : longword;
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OSPEEDR : longword;
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PUPDR : longword;
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IDR : longword;
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ODR : longword;
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BSRR : longword;
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LCKR : longword;
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AFR : array[0..1] of longword;
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BRR : longword;
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end;
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TI2C_Registers = record
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CR1 : longword;
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CR2 : longword;
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OAR1 : longword;
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OAR2 : longword;
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TIMINGR : longword;
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TIMEOUTR : longword;
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ISR : longword;
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ICR : longword;
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PECR : longword;
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RXDR : longword;
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TXDR : longword;
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end;
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TIWDG_Registers = record
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KR : longword;
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PR : longword;
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RLR : longword;
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SR : longword;
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WINR : longword;
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end;
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TLPTIM_Registers = record
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ISR : longword;
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ICR : longword;
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IER : longword;
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CFGR : longword;
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CR : longword;
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CMP : longword;
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ARR : longword;
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CNT : longword;
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RESERVED1 : longword;
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CFGR2 : longword;
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end;
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TPWR_Registers = record
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CR1 : longword;
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CR2 : longword;
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CR3 : longword;
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CR4 : longword;
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SR1 : longword;
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SR2 : longword;
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SCR : longword;
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RESERVED1 : longword;
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PUCRA : longword;
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PDCRA : longword;
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PUCRB : longword;
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PDCRB : longword;
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PUCRC : longword;
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PDCRC : longword;
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PUCRD : longword;
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PDCRD : longword;
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RESERVED2 : longword;
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RESERVED3 : longword;
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PUCRF : longword;
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PDCRF : longword;
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end;
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TRCC_Registers = record
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CR : longword;
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ICSCR : longword;
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CFGR : longword;
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PLLCFGR : longword;
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RESERVED0 : longword;
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RESERVED1 : longword;
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CIER : longword;
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CIFR : longword;
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CICR : longword;
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IOPRSTR : longword;
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AHBRSTR : longword;
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APBRSTR1 : longword;
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APBRSTR2 : longword;
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IOPENR : longword;
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AHBENR : longword;
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APBENR1 : longword;
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APBENR2 : longword;
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IOPSMENR : longword;
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AHBSMENR : longword;
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APBSMENR1 : longword;
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APBSMENR2 : longword;
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CCIPR : longword;
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RESERVED2 : longword;
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BDCR : longword;
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CSR : longword;
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end;
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TRTC_Registers = record
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TR : longword;
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DR : longword;
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SSR : longword;
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ICSR : longword;
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PRER : longword;
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WUTR : longword;
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CR : longword;
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RESERVED0 : longword;
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RESERVED1 : longword;
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WPR : longword;
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CALR : longword;
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SHIFTR : longword;
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TSTR : longword;
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TSDR : longword;
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TSSSR : longword;
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RESERVED2 : longword;
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ALRMAR : longword;
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ALRMASSR : longword;
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ALRMBR : longword;
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ALRMBSSR : longword;
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SR : longword;
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MISR : longword;
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RESERVED3 : longword;
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SCR : longword;
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&OR : longword;
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end;
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TTAMP_Registers = record
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CR1 : longword;
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CR2 : longword;
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RESERVED0 : longword;
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FLTCR : longword;
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RESERVED1 : array[0..6] of longword;
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IER : longword;
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SR : longword;
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MISR : longword;
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RESERVED2 : longword;
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SCR : longword;
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RESERVED3 : array[0..47] of longword;
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BKP0R : longword;
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BKP1R : longword;
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BKP2R : longword;
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BKP3R : longword;
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BKP4R : longword;
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end;
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TSPI_Registers = record
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CR1 : longword;
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CR2 : longword;
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SR : longword;
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DR : longword;
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CRCPR : longword;
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RXCRCR : longword;
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TXCRCR : longword;
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I2SCFGR : longword;
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I2SPR : longword;
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end;
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TSYSCFG_Registers = record
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CFGR1 : longword;
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RESERVED0 : array[0..4] of longword;
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CFGR2 : longword;
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RESERVED1 : array[0..24] of longword;
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IT_LINE_SR : array[0..31] of longword;
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end;
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TTIM_Registers = record
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CR1 : longword;
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CR2 : longword;
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SMCR : longword;
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DIER : longword;
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SR : longword;
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EGR : longword;
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CCMR1 : longword;
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CCMR2 : longword;
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CCER : longword;
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CNT : longword;
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PSC : longword;
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ARR : longword;
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RCR : longword;
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CCR1 : longword;
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CCR2 : longword;
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CCR3 : longword;
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CCR4 : longword;
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BDTR : longword;
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DCR : longword;
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DMAR : longword;
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OR1 : longword;
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CCMR3 : longword;
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CCR5 : longword;
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CCR6 : longword;
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AF1 : longword;
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AF2 : longword;
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TISEL : longword;
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end;
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TUSART_Registers = record
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CR1 : longword;
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CR2 : longword;
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CR3 : longword;
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BRR : longword;
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GTPR : longword;
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RTOR : longword;
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RQR : longword;
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ISR : longword;
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ICR : longword;
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RDR : longword;
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TDR : longword;
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PRESC : longword;
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end;
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TVREFBUF_Registers = record
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CSR : longword;
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CCR : longword;
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end;
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TWWDG_Registers = record
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CR : longword;
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CFR : longword;
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SR : longword;
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end;
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TUCPD_Registers = record
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CFG1 : longword;
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CFG2 : longword;
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RESERVED0 : longword;
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CR : longword;
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IMR : longword;
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SR : longword;
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ICR : longword;
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TX_ORDSET : longword;
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TX_PAYSZ : longword;
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TXDR : longword;
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RX_ORDSET : longword;
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RX_PAYSZ : longword;
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RXDR : longword;
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RX_ORDEXT1 : longword;
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RX_ORDEXT2 : longword;
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end;
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const
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FLASH_BASE = $08000000;
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SRAM_BASE = $20000000;
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PERIPH_BASE = $40000000;
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IOPORT_BASE = $50000000;
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APBPERIPH_BASE= PERIPH_BASE;
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AHBPERIPH_BASE= PERIPH_BASE + $00020000;
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TIM2_BASE = APBPERIPH_BASE + 0;
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TIM3_BASE = APBPERIPH_BASE + $00000400;
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TIM6_BASE = APBPERIPH_BASE + $00001000;
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TIM7_BASE = APBPERIPH_BASE + $00001400;
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TIM14_BASE = APBPERIPH_BASE + $00002000;
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RTC_BASE = APBPERIPH_BASE + $00002800;
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WWDG_BASE = APBPERIPH_BASE + $00002C00;
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IWDG_BASE = APBPERIPH_BASE + $00003000;
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SPI2_BASE = APBPERIPH_BASE + $00003800;
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USART2_BASE = APBPERIPH_BASE + $00004400;
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USART3_BASE = APBPERIPH_BASE + $00004800;
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USART4_BASE = APBPERIPH_BASE + $00004C00;
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I2C1_BASE = APBPERIPH_BASE + $00005400;
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I2C2_BASE = APBPERIPH_BASE + $00005800;
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PWR_BASE = APBPERIPH_BASE + $00007000;
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DAC1_BASE = APBPERIPH_BASE + $00007400;
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DAC_BASE = APBPERIPH_BASE + $00007400;
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CEC_BASE = APBPERIPH_BASE + $00007800;
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LPTIM1_BASE = APBPERIPH_BASE + $00007C00;
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LPUART1_BASE = APBPERIPH_BASE + $00008000;
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LPTIM2_BASE = APBPERIPH_BASE + $00009400;
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UCPD1_BASE = APBPERIPH_BASE + $0000A000;
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UCPD2_BASE = APBPERIPH_BASE + $0000A400;
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TAMP_BASE = APBPERIPH_BASE + $0000B000;
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SYSCFG_BASE = APBPERIPH_BASE + $00010000;
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VREFBUF_BASE = APBPERIPH_BASE + $00010030;
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COMP1_BASE = SYSCFG_BASE + $0200;
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COMP2_BASE = SYSCFG_BASE + $0204;
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ADC1_BASE = APBPERIPH_BASE + $00012400;
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ADC1_COMMON_BASE= APBPERIPH_BASE + $00012708;
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ADC_BASE = ADC1_COMMON_BASE;
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TIM1_BASE = APBPERIPH_BASE + $00012C00;
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SPI1_BASE = APBPERIPH_BASE + $00013000;
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USART1_BASE = APBPERIPH_BASE + $00013800;
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TIM15_BASE = APBPERIPH_BASE + $00014000;
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TIM16_BASE = APBPERIPH_BASE + $00014400;
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TIM17_BASE = APBPERIPH_BASE + $00014800;
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DBG_BASE = APBPERIPH_BASE + $00015800;
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DMA1_BASE = AHBPERIPH_BASE;
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DMAMUX1_BASE = AHBPERIPH_BASE + $00000800;
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RCC_BASE = AHBPERIPH_BASE + $00001000;
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EXTI_BASE = AHBPERIPH_BASE + $00001800;
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FLASH_R_BASE = AHBPERIPH_BASE + $00002000;
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CRC_BASE = AHBPERIPH_BASE + $00003000;
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DMA1_Channel1_BASE= DMA1_BASE + $00000008;
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DMA1_Channel2_BASE= DMA1_BASE + $0000001C;
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DMA1_Channel3_BASE= DMA1_BASE + $00000030;
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DMA1_Channel4_BASE= DMA1_BASE + $00000044;
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DMA1_Channel5_BASE= DMA1_BASE + $00000058;
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DMA1_Channel6_BASE= DMA1_BASE + $0000006C;
|
|
DMA1_Channel7_BASE= DMA1_BASE + $00000080;
|
|
DMAMUX1_Channel0_BASE= DMAMUX1_BASE;
|
|
DMAMUX1_Channel1_BASE= DMAMUX1_BASE + $00000004;
|
|
DMAMUX1_Channel2_BASE= DMAMUX1_BASE + $00000008;
|
|
DMAMUX1_Channel3_BASE= DMAMUX1_BASE + $0000000C;
|
|
DMAMUX1_Channel4_BASE= DMAMUX1_BASE + $00000010;
|
|
DMAMUX1_Channel5_BASE= DMAMUX1_BASE + $00000014;
|
|
DMAMUX1_Channel6_BASE= DMAMUX1_BASE + $00000018;
|
|
DMAMUX1_RequestGenerator0_BASE= DMAMUX1_BASE + $00000100;
|
|
DMAMUX1_RequestGenerator1_BASE= DMAMUX1_BASE + $00000104;
|
|
DMAMUX1_RequestGenerator2_BASE= DMAMUX1_BASE + $00000108;
|
|
DMAMUX1_RequestGenerator3_BASE= DMAMUX1_BASE + $0000010C;
|
|
DMAMUX1_ChannelStatus_BASE= DMAMUX1_BASE + $00000080;
|
|
DMAMUX1_RequestGenStatus_BASE= DMAMUX1_BASE + $00000140;
|
|
GPIOA_BASE = IOPORT_BASE + $00000000;
|
|
GPIOB_BASE = IOPORT_BASE + $00000400;
|
|
GPIOC_BASE = IOPORT_BASE + $00000800;
|
|
GPIOD_BASE = IOPORT_BASE + $00000C00;
|
|
GPIOF_BASE = IOPORT_BASE + $00001400;
|
|
PACKAGE_BASE = $1FFF7500;
|
|
UID_BASE = $1FFF7590;
|
|
FLASHSIZE_BASE= $1FFF75E0;
|
|
|
|
var
|
|
TIM2 : TTIM_Registers absolute TIM2_BASE;
|
|
TIM3 : TTIM_Registers absolute TIM3_BASE;
|
|
TIM6 : TTIM_Registers absolute TIM6_BASE;
|
|
TIM7 : TTIM_Registers absolute TIM7_BASE;
|
|
TIM14 : TTIM_Registers absolute TIM14_BASE;
|
|
RTC : TRTC_Registers absolute RTC_BASE;
|
|
TAMP : TTAMP_Registers absolute TAMP_BASE;
|
|
WWDG : TWWDG_Registers absolute WWDG_BASE;
|
|
IWDG : TIWDG_Registers absolute IWDG_BASE;
|
|
SPI2 : TSPI_Registers absolute SPI2_BASE;
|
|
USART2 : TUSART_Registers absolute USART2_BASE;
|
|
USART3 : TUSART_Registers absolute USART3_BASE;
|
|
USART4 : TUSART_Registers absolute USART4_BASE;
|
|
I2C1 : TI2C_Registers absolute I2C1_BASE;
|
|
I2C2 : TI2C_Registers absolute I2C2_BASE;
|
|
LPTIM1 : TLPTIM_Registers absolute LPTIM1_BASE;
|
|
PWR : TPWR_Registers absolute PWR_BASE;
|
|
RCC : TRCC_Registers absolute RCC_BASE;
|
|
EXTI : TEXTI_Registers absolute EXTI_BASE;
|
|
DAC1 : TDAC_Registers absolute DAC1_BASE;
|
|
DAC : TDAC_Registers absolute DAC_BASE;
|
|
LPUART1 : TUSART_Registers absolute LPUART1_BASE;
|
|
LPTIM2 : TLPTIM_Registers absolute LPTIM2_BASE;
|
|
CEC : TCEC_Registers absolute CEC_BASE;
|
|
SYSCFG : TSYSCFG_Registers absolute SYSCFG_BASE;
|
|
VREFBUF : TVREFBUF_Registers absolute VREFBUF_BASE;
|
|
COMP1 : TCOMP_Registers absolute COMP1_BASE;
|
|
COMP2 : TCOMP_Registers absolute COMP2_BASE;
|
|
COMP12_COMMON : TCOMP_Common_Registers absolute COMP1_BASE;
|
|
TIM1 : TTIM_Registers absolute TIM1_BASE;
|
|
SPI1 : TSPI_Registers absolute SPI1_BASE;
|
|
USART1 : TUSART_Registers absolute USART1_BASE;
|
|
TIM15 : TTIM_Registers absolute TIM15_BASE;
|
|
TIM16 : TTIM_Registers absolute TIM16_BASE;
|
|
TIM17 : TTIM_Registers absolute TIM17_BASE;
|
|
DMA1 : TDMA_Registers absolute DMA1_BASE;
|
|
FLASH : TFLASH_Registers absolute FLASH_R_BASE;
|
|
CRC : TCRC_Registers absolute CRC_BASE;
|
|
GPIOA : TGPIO_Registers absolute GPIOA_BASE;
|
|
GPIOB : TGPIO_Registers absolute GPIOB_BASE;
|
|
GPIOC : TGPIO_Registers absolute GPIOC_BASE;
|
|
GPIOD : TGPIO_Registers absolute GPIOD_BASE;
|
|
GPIOF : TGPIO_Registers absolute GPIOF_BASE;
|
|
ADC1 : TADC_Registers absolute ADC1_BASE;
|
|
ADC1_COMMON : TADC_Common_Registers absolute ADC1_COMMON_BASE;
|
|
UCPD1 : TUCPD_Registers absolute UCPD1_BASE;
|
|
UCPD2 : TUCPD_Registers absolute UCPD2_BASE;
|
|
DMA1_Channel1 : TDMA_Channel_Registers absolute DMA1_Channel1_BASE;
|
|
DMA1_Channel2 : TDMA_Channel_Registers absolute DMA1_Channel2_BASE;
|
|
DMA1_Channel3 : TDMA_Channel_Registers absolute DMA1_Channel3_BASE;
|
|
DMA1_Channel4 : TDMA_Channel_Registers absolute DMA1_Channel4_BASE;
|
|
DMA1_Channel5 : TDMA_Channel_Registers absolute DMA1_Channel5_BASE;
|
|
DMA1_Channel6 : TDMA_Channel_Registers absolute DMA1_Channel6_BASE;
|
|
DMA1_Channel7 : TDMA_Channel_Registers absolute DMA1_Channel7_BASE;
|
|
DMAMUX1 : TDMAMUX_Channel_Registers absolute DMAMUX1_BASE;
|
|
DMAMUX1_Channel0: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel0_BASE;
|
|
DMAMUX1_Channel1: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel1_BASE;
|
|
DMAMUX1_Channel2: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel2_BASE;
|
|
DMAMUX1_Channel3: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel3_BASE;
|
|
DMAMUX1_Channel4: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel4_BASE;
|
|
DMAMUX1_Channel5: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel5_BASE;
|
|
DMAMUX1_Channel6: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel6_BASE;
|
|
DMAMUX1_RequestGenerator0: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator0_BASE;
|
|
DMAMUX1_RequestGenerator1: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator1_BASE;
|
|
DMAMUX1_RequestGenerator2: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator2_BASE;
|
|
DMAMUX1_RequestGenerator3: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator3_BASE;
|
|
DMAMUX1_ChannelStatus: TDMAMUX_ChannelStatus_Registers absolute DMAMUX1_ChannelStatus_BASE;
|
|
DMAMUX1_RequestGenStatus: TDMAMUX_RequestGenStatus_Registers absolute DMAMUX1_RequestGenStatus_BASE;
|
|
DBG : TDBG_Registers absolute DBG_BASE;
|
|
|
|
implementation
|
|
|
|
procedure NonMaskableInt_Handler; external name 'NonMaskableInt_Handler';
|
|
procedure HardFault_Handler; external name 'HardFault_Handler';
|
|
procedure SVC_Handler; external name 'SVC_Handler';
|
|
procedure PendSV_Handler; external name 'PendSV_Handler';
|
|
procedure SysTick_Handler; external name 'SysTick_Handler';
|
|
procedure WWDG_Handler; external name 'WWDG_Handler';
|
|
procedure PVD_Handler; external name 'PVD_Handler';
|
|
procedure RTC_TAMP_Handler; external name 'RTC_TAMP_Handler';
|
|
procedure FLASH_Handler; external name 'FLASH_Handler';
|
|
procedure RCC_Handler; external name 'RCC_Handler';
|
|
procedure EXTI0_1_Handler; external name 'EXTI0_1_Handler';
|
|
procedure EXTI2_3_Handler; external name 'EXTI2_3_Handler';
|
|
procedure EXTI4_15_Handler; external name 'EXTI4_15_Handler';
|
|
procedure UCPD1_2_Handler; external name 'UCPD1_2_Handler';
|
|
procedure DMA1_Channel1_Handler; external name 'DMA1_Channel1_Handler';
|
|
procedure DMA1_Channel2_3_Handler; external name 'DMA1_Channel2_3_Handler';
|
|
procedure DMA1_Ch4_7_DMAMUX1_OVR_Handler; external name 'DMA1_Ch4_7_DMAMUX1_OVR_Handler';
|
|
procedure ADC1_COMP_Handler; external name 'ADC1_COMP_Handler';
|
|
procedure TIM1_BRK_UP_TRG_COM_Handler; external name 'TIM1_BRK_UP_TRG_COM_Handler';
|
|
procedure TIM1_CC_Handler; external name 'TIM1_CC_Handler';
|
|
procedure TIM2_Handler; external name 'TIM2_Handler';
|
|
procedure TIM3_Handler; external name 'TIM3_Handler';
|
|
procedure TIM6_DAC_LPTIM1_Handler; external name 'TIM6_DAC_LPTIM1_Handler';
|
|
procedure TIM7_LPTIM2_Handler; external name 'TIM7_LPTIM2_Handler';
|
|
procedure TIM14_Handler; external name 'TIM14_Handler';
|
|
procedure TIM15_Handler; external name 'TIM15_Handler';
|
|
procedure TIM16_Handler; external name 'TIM16_Handler';
|
|
procedure TIM17_Handler; external name 'TIM17_Handler';
|
|
procedure I2C1_Handler; external name 'I2C1_Handler';
|
|
procedure I2C2_Handler; external name 'I2C2_Handler';
|
|
procedure SPI1_Handler; external name 'SPI1_Handler';
|
|
procedure SPI2_Handler; external name 'SPI2_Handler';
|
|
procedure USART1_Handler; external name 'USART1_Handler';
|
|
procedure USART2_Handler; external name 'USART2_Handler';
|
|
procedure USART3_4_LPUART1_Handler; external name 'USART3_4_LPUART1_Handler';
|
|
procedure CEC_Handler; external name 'CEC_Handler';
|
|
|
|
|
|
{$i cortexm0_start.inc}
|
|
|
|
procedure Vectors; assembler; nostackframe;
|
|
label interrupt_vectors;
|
|
asm
|
|
.section ".init.interrupt_vectors"
|
|
interrupt_vectors:
|
|
.long _stack_top
|
|
.long Startup
|
|
.long NonMaskableInt_Handler
|
|
.long HardFault_Handler
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long SVC_Handler
|
|
.long 0
|
|
.long 0
|
|
.long PendSV_Handler
|
|
.long SysTick_Handler
|
|
.long WWDG_Handler
|
|
.long PVD_Handler
|
|
.long RTC_TAMP_Handler
|
|
.long FLASH_Handler
|
|
.long RCC_Handler
|
|
.long EXTI0_1_Handler
|
|
.long EXTI2_3_Handler
|
|
.long EXTI4_15_Handler
|
|
.long UCPD1_2_Handler
|
|
.long DMA1_Channel1_Handler
|
|
.long DMA1_Channel2_3_Handler
|
|
.long DMA1_Ch4_7_DMAMUX1_OVR_Handler
|
|
.long ADC1_COMP_Handler
|
|
.long TIM1_BRK_UP_TRG_COM_Handler
|
|
.long TIM1_CC_Handler
|
|
.long TIM2_Handler
|
|
.long TIM3_Handler
|
|
.long TIM6_DAC_LPTIM1_Handler
|
|
.long TIM7_LPTIM2_Handler
|
|
.long TIM14_Handler
|
|
.long TIM15_Handler
|
|
.long TIM16_Handler
|
|
.long TIM17_Handler
|
|
.long I2C1_Handler
|
|
.long I2C2_Handler
|
|
.long SPI1_Handler
|
|
.long SPI2_Handler
|
|
.long USART1_Handler
|
|
.long USART2_Handler
|
|
.long USART3_4_LPUART1_Handler
|
|
.long CEC_Handler
|
|
|
|
.weak NonMaskableInt_Handler
|
|
.weak HardFault_Handler
|
|
.weak SVC_Handler
|
|
.weak PendSV_Handler
|
|
.weak SysTick_Handler
|
|
.weak WWDG_Handler
|
|
.weak PVD_Handler
|
|
.weak RTC_TAMP_Handler
|
|
.weak FLASH_Handler
|
|
.weak RCC_Handler
|
|
.weak EXTI0_1_Handler
|
|
.weak EXTI2_3_Handler
|
|
.weak EXTI4_15_Handler
|
|
.weak UCPD1_2_Handler
|
|
.weak DMA1_Channel1_Handler
|
|
.weak DMA1_Channel2_3_Handler
|
|
.weak DMA1_Ch4_7_DMAMUX1_OVR_Handler
|
|
.weak ADC1_COMP_Handler
|
|
.weak TIM1_BRK_UP_TRG_COM_Handler
|
|
.weak TIM1_CC_Handler
|
|
.weak TIM2_Handler
|
|
.weak TIM3_Handler
|
|
.weak TIM6_DAC_LPTIM1_Handler
|
|
.weak TIM7_LPTIM2_Handler
|
|
.weak TIM14_Handler
|
|
.weak TIM15_Handler
|
|
.weak TIM16_Handler
|
|
.weak TIM17_Handler
|
|
.weak I2C1_Handler
|
|
.weak I2C2_Handler
|
|
.weak SPI1_Handler
|
|
.weak SPI2_Handler
|
|
.weak USART1_Handler
|
|
.weak USART2_Handler
|
|
.weak USART3_4_LPUART1_Handler
|
|
.weak CEC_Handler
|
|
|
|
.set NonMaskableInt_Handler, Haltproc
|
|
.set HardFault_Handler, Haltproc
|
|
.set SVC_Handler, Haltproc
|
|
.set PendSV_Handler, Haltproc
|
|
.set SysTick_Handler, Haltproc
|
|
.set WWDG_Handler, Haltproc
|
|
.set PVD_Handler, Haltproc
|
|
.set RTC_TAMP_Handler, Haltproc
|
|
.set FLASH_Handler, Haltproc
|
|
.set RCC_Handler, Haltproc
|
|
.set EXTI0_1_Handler, Haltproc
|
|
.set EXTI2_3_Handler, Haltproc
|
|
.set EXTI4_15_Handler, Haltproc
|
|
.set UCPD1_2_Handler, Haltproc
|
|
.set DMA1_Channel1_Handler, Haltproc
|
|
.set DMA1_Channel2_3_Handler, Haltproc
|
|
.set DMA1_Ch4_7_DMAMUX1_OVR_Handler, Haltproc
|
|
.set ADC1_COMP_Handler, Haltproc
|
|
.set TIM1_BRK_UP_TRG_COM_Handler, Haltproc
|
|
.set TIM1_CC_Handler, Haltproc
|
|
.set TIM2_Handler, Haltproc
|
|
.set TIM3_Handler, Haltproc
|
|
.set TIM6_DAC_LPTIM1_Handler, Haltproc
|
|
.set TIM7_LPTIM2_Handler, Haltproc
|
|
.set TIM14_Handler, Haltproc
|
|
.set TIM15_Handler, Haltproc
|
|
.set TIM16_Handler, Haltproc
|
|
.set TIM17_Handler, Haltproc
|
|
.set I2C1_Handler, Haltproc
|
|
.set I2C2_Handler, Haltproc
|
|
.set SPI1_Handler, Haltproc
|
|
.set SPI2_Handler, Haltproc
|
|
.set USART1_Handler, Haltproc
|
|
.set USART2_Handler, Haltproc
|
|
.set USART3_4_LPUART1_Handler, Haltproc
|
|
.set CEC_Handler, Haltproc
|
|
|
|
.text
|
|
end;
|
|
end.
|