mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-08-16 02:49:21 +02:00
833 lines
21 KiB
ObjectPascal
833 lines
21 KiB
ObjectPascal
{$IFNDEF FPC_DOTTEDUNITS}
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unit rp2040;
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{$ENDIF FPC_DOTTEDUNITS}
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interface
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{$PACKRECORDS C}
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{$GOTO ON}
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{$SCOPEDENUMS ON}
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type
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TIRQn_Enum = (
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NonMaskableInt_IRQn = -14,
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HardFault_IRQn = -13,
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SVC_IRQn = -5,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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TIMER_IRQ_0 = 0,
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TIMER_IRQ_1 = 1,
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TIMER_IRQ_2 = 2,
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TIMER_IRQ_3 = 3,
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PWM_IRQ_WRAP =4,
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USBCTRL_IRQ =5,
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XIP_IRQ =6,
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PIO0_IRQ_0 =7,
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PIO0_IRQ_1 =8,
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PIO1_IRQ_0 =9,
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PIO1_IRQ_1 =10,
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DMA_IRQ_0 =11,
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DMA_IRQ_1 =12,
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IO_IRQ_BANK0=13,
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IO_IRQ_QSPI =14,
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SIO_IRQ_PROC0=15,
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SIO_IRQ_PROC1 =16,
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CLOCKS_IRQ =17,
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SPI0_IRQ =18,
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SPI1_IRQ =19,
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UART0_IRQ =20,
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UART1_IRQ =21,
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ADC0_IRQ_FIFO=22,
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I2C0_IRQ=23,
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I2C1_IRQ=24,
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RTC_IRQ=25
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);
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type
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TADC_Registers = record
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cs : longWord;
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result : longWord;
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fcs : longWord;
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fifo : longWord;
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&div : longWord;
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intr : longWord;
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inte : longWord;
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intf : longWord;
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ints : longWord;
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end;
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TBUSCTRL_Registers = record
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priority : longWord;
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priority_ack : longWord;
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perf : array[0..3] of record
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ctr : longWord;
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sel : longWord;
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end;
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end;
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TCLOCK_Registers = record
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ctrl : longWord;
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&div : longWord;
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selected : longWord;
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end;
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TFC_Registers = record
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ref_khz : longWord;
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min_khz : longWord;
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max_khz : longWord;
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delay : longWord;
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interval : longWord;
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src : longWord;
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status : longWord;
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result : longWord;
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end;
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TCLOCKS_Registers = record
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clk_gpout : array[0..3] of TCLOCK_Registers;
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clk_ref : TCLOCK_Registers;
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clk_sys : TCLOCK_Registers;
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clk_peri : TCLOCK_Registers;
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clk_usb : TCLOCK_Registers;
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clk_adc : TCLOCK_Registers;
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clk_rtc : TCLOCK_Registers;
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clk_sys_resus : record
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ctrl : longWord;
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status : longWord;
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end;
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fc0 : TFC_Registers;
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wake_en0 : longWord;
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wake_en1 : longWord;
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sleep_en0 : longWord;
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sleep_en1 : longWord;
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enabled0 : longWord;
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enabled1 : longWord;
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intr : longWord;
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inte : longWord;
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intf : longWord;
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ints : longWord;
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end;
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TDMACHANNEL_Registers = record
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read_addr : longWord;
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write_addr : longWord;
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transfer_count : longWord;
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ctrl_trig : longWord;
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al1_ctrl : longWord;
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al1_read_addr : longWord;
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al1_write_addr : longWord;
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al1_transfer_count_trig : longWord;
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al2_ctrl : longWord;
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al2_transfer_count : longWord;
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al2_read_addr : longWord;
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al2_write_addr_trig : longWord;
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al3_ctrl : longWord;
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al3_write_addr : longWord;
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al3_transfer_count : longWord;
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al3_read_addr_trig : longWord;
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end;
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TDMA_Registers = record
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ch : array[0..11] of TDMACHANNEL_Registers;
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RESERVED0 : array[0..63] of longWord;
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intr : longWord;
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inte0 : longWord;
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intf0 : longWord;
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ints0 : longWord;
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RESERVED1 : longWord;
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inte1 : longWord;
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intf1 : longWord;
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ints1 : longWord;
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timer : array[0..1] of longWord;
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RESERVED2 : array[0..1] of longWord;
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multi_channel_trigger : longWord;
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sniff_ctrl : longWord;
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sniff_data : longWord;
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RESERVED3 : longWord;
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fifo_levels : longWord;
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abort : longWord;
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end;
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TDMADEBUG_Registers = record
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ch : array[0..11] of record
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ctrdeq : longWord;
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tcr : longWord;
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RESERVED0 : array[0..13] of longWord;
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end;
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end;
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TI2C_Registers = record
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con : longWord;
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tar : longWord;
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sar : longWord;
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RESERVED0 : longWord;
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data_cmd : longWord;
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ss_scl_hcnt : longWord;
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ss_scl_lcnt : longWord;
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fs_scl_hcnt : longWord;
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fs_scl_lcnt : longWord;
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RESERVED1 : array[0..1] of longWord;
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intr_stat : longWord;
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intr_mask : longWord;
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raw_intr_stat : longWord;
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rx_tl : longWord;
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tx_tl : longWord;
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clr_intr : longWord;
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clr_rx_under : longWord;
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clr_rx_over : longWord;
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clr_tx_over : longWord;
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clr_rd_req : longWord;
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clr_tx_abrt : longWord;
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clr_rx_done : longWord;
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clr_activity : longWord;
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clr_stop_det : longWord;
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clr_start_det : longWord;
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clr_gen_call : longWord;
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enable : longWord;
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status : longWord;
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txflr : longWord;
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rxflr : longWord;
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sda_hold : longWord;
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tx_abrt_source : longWord;
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slv_data_nack_only : longWord;
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dma_cr : longWord;
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dma_tdlr : longWord;
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dma_rdlr : longWord;
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sda_setup : longWord;
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ack_general_call : longWord;
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enable_status : longWord;
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fs_spklen : longWord;
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RESERVED2 : longWord;
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clr_restart_det : longWord;
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RESERVED3 : array[0..17] of longWord;
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comp_param_1 : longWord;
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comp_version : longWord;
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comp_type : longWord;
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end;
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TIOIRQCTRL_Registers = record
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inte : array[0..3] of longWord;
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intf : array[0..3] of longWord;
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ints : array[0..3] of longWord;
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end;
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TIOBANK0_Registers = record
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io : array[0..29] of record
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status : longWord;
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ctrl : longWord;
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end;
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intr : array[0..3] of longWord;
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proc0_irq_ctrl : TIOIRQCTRL_Registers;
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proc1_irq_ctrl : TIOIRQCTRL_Registers;
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dormant_wake_irq_ctrl : TIOIRQCTRL_Registers;
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end;
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TIOQSPI_Registers = record
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io : array[0..5] of record
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status : longWord;
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ctrl : longWord;
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end;
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end;
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TPADSQSPI_Registers = record
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voltage_select : longWord;
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io : array[0..5] of longWord;
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end;
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TPADSBANK0_Registers = record
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voltage_select : longWord;
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io : array[0..29] of longWord;
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end;
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TPIO_Registers = record
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ctrl : longWord;
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fstat : longWord;
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fdebug : longWord;
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flevel : longWord;
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txf : array[0..1] of longWord;
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rxf : array[0..1] of longWord;
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irq : longWord;
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irq_force : longWord;
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input_sync_bypass : longWord;
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dbg_padout : longWord;
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dbg_padoe : longWord;
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dbg_cfginfo : longWord;
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instr_mem : array[0..31] of longWord;
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sm : array[0..1] of record
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clkdiv : longWord;
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execctrl : longWord;
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shiftctrl : longWord;
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addr : longWord;
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instr : longWord;
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pinctrl : longWord;
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end;
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intr : longWord;
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inte0 : longWord;
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intf0 : longWord;
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ints0 : longWord;
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inte1 : longWord;
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intf1 : longWord;
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ints1 : longWord;
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end;
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TPLL_Registers = record
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cs : longWord;
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pwr : longWord;
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fbdiv_int : longWord;
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prim : longWord;
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end;
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TPSM_Registers = record
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frce_on : longWord;
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frce_off : longWord;
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wdsel : longWord;
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done : longWord;
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end;
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TPWMSLICE_Registers = record
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csr : longWord;
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&div : longWord;
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ctr : longWord;
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cc : longWord;
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top : longWord;
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end;
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TPWM_Registers = record
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slice : array[0..7] of TPWMSLICE_Registers;
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en : longWord;
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intr : longWord;
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inte : longWord;
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intf : longWord;
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ints : longWord;
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end;
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TRESETS_Registers = record
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reset : longWord;
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wdsel : longWord;
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reset_done : longWord;
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end;
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TROSC_Registers = record
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ctrl : longWord;
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freqa : longWord;
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freqb : longWord;
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dormant : longWord;
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&div : longWord;
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phase : longWord;
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status : longWord;
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randombit : longWord;
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count : longWord;
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dftx : longWord;
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end;
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TRTC_Registers = record
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clkdiv_m1 : longWord;
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setup_0 : longWord;
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setup_1 : longWord;
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ctrl : longWord;
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irq_setup_0 : longWord;
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irq_setup_1 : longWord;
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rtc_1 : longWord;
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rtc_0 : longWord;
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intr : longWord;
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inte : longWord;
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intf : longWord;
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ints : longWord;
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end;
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TINTERP_Registers = record
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accum : array[0..1] of longWord;
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base : array[0..2] of longWord;
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pop : array[0..2] of longWord;
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peek : array[0..2] of longWord;
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ctrl : array[0..1] of longWord;
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add_raw : array[0..1] of longWord;
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base01 : longWord;
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end;
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TSIO_Registers = record
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cpuid : longWord;
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gpio_in : longWord;
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gpio_hi_in : longWord;
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RESERVED0 : longWord;
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gpio_out : longWord;
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gpio_set : longWord;
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gpio_clr : longWord;
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gpio_togl : longWord;
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gpio_oe : longWord;
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gpio_oe_set : longWord;
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gpio_oe_clr : longWord;
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gpio_oe_togl : longWord;
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gpio_hi_out : longWord;
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gpio_hi_set : longWord;
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gpio_hi_clr : longWord;
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gpio_hi_togl : longWord;
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gpio_hi_oe : longWord;
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gpio_hi_oe_set : longWord;
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gpio_hi_oe_clr : longWord;
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gpio_hi_oe_togl : longWord;
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fifo_st : longWord;
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fifo_wr : longWord;
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fifo_rd : longWord;
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spinlock_st : longWord;
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div_udividend : longWord;
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div_udivisor : longWord;
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div_sdividend : longWord;
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div_sdivisor : longWord;
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div_quotient : longWord;
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div_remainder : longWord;
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div_csr : longWord;
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RESERVED1 : longWord;
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interp : array[0..1] of TINTERP_Registers;
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spinlock : array[0..31] of longWord;
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end;
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TSPI_Registers = record
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cr0 : longWord;
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cr1 : longWord;
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dr : longWord;
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sr : longWord;
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cpsr : longWord;
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imsc : longWord;
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ris : longWord;
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mis : longWord;
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icr : longWord;
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dmacr : longWord;
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end;
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TSSI_Registers = record
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ctrlr0 : longWord;
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ctrlr1 : longWord;
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ssienr : longWord;
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mwcr : longWord;
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ser : longWord;
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baudr : longWord;
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txftlr : longWord;
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rxftlr : longWord;
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txflr : longWord;
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rxflr : longWord;
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sr : longWord;
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imr : longWord;
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isr : longWord;
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risr : longWord;
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txoicr : longWord;
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rxoicr : longWord;
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rxuicr : longWord;
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msticr : longWord;
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icr : longWord;
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dmacr : longWord;
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dmatdlr : longWord;
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dmardlr : longWord;
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idr : longWord;
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ssi_version_id : longWord;
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dr0 : longWord;
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RESERVED0 : array[0..34] of longWord;
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rx_sample_dly : longWord;
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spi_ctrlr0 : longWord;
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txd_drive_edge : longWord;
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end;
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TSYSCFG_Registers = record
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proc0_nmi_mask : longWord;
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proc1_nmi_mask : longWord;
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proc_config : longWord;
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proc_in_sync_bypass : longWord;
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proc_in_sync_bypass_hi : longWord;
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dbgforce : longWord;
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mempowerdown : longWord;
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end;
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TSYSINFO_Registers = record
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chip_id : longWord;
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platform : longWord;
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reserved0 : array[0..$3F-$08] of longWord;
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gitref_rp2040 : longWord;
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end;
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TTIMER_Registers = record
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timehw : longWord;
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timelw : longWord;
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timehr : longWord;
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timelr : longWord;
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alarm : array[0..3] of longWord;
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armed : longWord;
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timerawh : longWord;
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timerawl : longWord;
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dbgpause : longWord;
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pause : longWord;
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intr : longWord;
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inte : longWord;
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intf : longWord;
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ints : longWord;
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end;
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TUART_Registers = record
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dr : longWord;
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rsr : longWord;
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RESERVED0 : array[0..3] of longWord;
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fr : longWord;
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RESERVED1 : longWord;
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ilpr : longWord;
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ibrd : longWord;
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fbrd : longWord;
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lcr_h : longWord;
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cr : longWord;
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ifls : longWord;
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imsc : longWord;
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ris : longWord;
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mis : longWord;
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icr : longWord;
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dmacr : longWord;
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end;
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TUSBDEVICEDPRAM = record
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setup_packet : array[0..7] of byte;
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ep_ctrl : array[0..14] of record
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&in : longWord;
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&out : longWord;
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end;
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ep_buf_ctrl : array[0..15] of record
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&in : longWord;
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&out : longWord;
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end;
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ep0_buf_a : array[0..63] of byte;
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ep0_buf_b : array[0..63] of byte;
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epx_data : array[0..(4096-$180)-1] of byte;
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end;
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TUSBHOSTDPRAM = record
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setup_packet : array[0..7] of byte;
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int_ep_ctrl : array[0..14] of record
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ctrl : longWord;
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spare : longWord;
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end;
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epx_buf_ctrl : longWord;
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_spare0 : longWord;
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int_ep_buffer_ctrl : array[0..14] of record
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ctrl : longWord;
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spare : longWord;
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end;
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epx_ctrl : longWord;
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_spare1 : array[0..123] of byte;
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epx_data : array[0..(4096-$180)-1] of byte;
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end;
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TUSB_Registers = record
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dev_addr_ctrl : longWord;
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int_ep_addr_ctrl : array[1..15] of longWord;
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main_ctrl : longWord;
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sof_wr : longWord;
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sof_rd : longWord;
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sie_ctrl : longWord;
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sie_status : longWord;
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int_ep_ctrl : longWord;
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buf_status : longWord;
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buf_cpu_should_handle : longWord;
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abort : longWord;
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abort_done : longWord;
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ep_stall_arm : longWord;
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nak_poll : longWord;
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ep_nak_stall_status : longWord;
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muxing : longWord;
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pwr : longWord;
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phy_direct : longWord;
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phy_direct_override : longWord;
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phy_trim : longWord;
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linestate_tuning : longWord;
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intr : longWord;
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inte : longWord;
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intf : longWord;
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ints : longWord;
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end;
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TVREGANDCHIPRESET_Registers = record
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vreg : longWord;
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bod : longWord;
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chip_reset : longWord;
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end;
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|
|
|
TWATCHDOG_Registers = record
|
|
ctrl : longWord;
|
|
load : longWord;
|
|
reason : longWord;
|
|
scratch : array[0..7] of longWord;
|
|
tick : longWord;
|
|
end;
|
|
|
|
TXIPCTRL_Registers = record
|
|
ctrl : longWord;
|
|
flush : longWord;
|
|
stat : longWord;
|
|
ctr_hit : longWord;
|
|
ctr_acc : longWord;
|
|
stream_addr : longWord;
|
|
stream_ctr : longWord;
|
|
stream_fifo : longWord;
|
|
end;
|
|
|
|
TXOSC_Registers = record
|
|
ctrl : longWord;
|
|
status : longWord;
|
|
dormant : longWord;
|
|
startup : longWord;
|
|
RESERVED0 : array[0..2] of longWord;
|
|
count : longWord;
|
|
end;
|
|
|
|
TMPU_Registers = record
|
|
_type : longWord;
|
|
ctrl : longWord;
|
|
rnr : longWord;
|
|
rbar : longWord;
|
|
rasr : longWord;
|
|
end;
|
|
|
|
TSYSTICK_Registers = record
|
|
csr : longWord;
|
|
rvr : longWord;
|
|
cvr : longWord;
|
|
calib : longWord;
|
|
end;
|
|
|
|
TSCB_Reqisters = record
|
|
cpuid : longWord;
|
|
icsr : longWord;
|
|
vtor : longWord;
|
|
aircr : longWord;
|
|
scr : longWord;
|
|
end;
|
|
|
|
const
|
|
__NVIC_PRIO_BITS= 2;
|
|
SRAM0_BASE = $21000000;
|
|
SRAM1_BASE = $21010000;
|
|
SRAM2_BASE = $21020000;
|
|
SRAM3_BASE = $21030000;
|
|
SYSINFO_BASE = $40000000;
|
|
SYSCFG_BASE = $40004000;
|
|
CLOCKS_BASE = $40008000;
|
|
RESETS_BASE = $4000c000;
|
|
PSM_BASE = $40010000;
|
|
IO_BANK0_BASE = $40014000;
|
|
IO_QSPI_BASE = $40018000;
|
|
PADS_BANK0_BASE = $4001c000;
|
|
PADS_QSPI_BASE = $40020000;
|
|
XOSC_BASE = $40024000;
|
|
PLL_SYS_BASE = $40028000;
|
|
PLL_USB_BASE = $4002c000;
|
|
BUSCTRL_BASE = $40030000;
|
|
UART0_BASE = $40034000;
|
|
UART1_BASE = $40038000;
|
|
SPI0_BASE = $4003c000;
|
|
SPI1_BASE = $40040000;
|
|
I2C0_BASE = $40044000;
|
|
I2C1_BASE = $40048000;
|
|
ADC_BASE = $4004c000;
|
|
PWM_BASE = $40050000;
|
|
TIMER_BASE = $40054000;
|
|
WATCHDOG_BASE = $40058000;
|
|
RTC_BASE = $4005c000;
|
|
ROSC_BASE = $40060000;
|
|
VREG_AND_CHIP_RESET_BASE = $40064000;
|
|
TBMAN_BASE = $4006c000;
|
|
DMA_BASE = $50000000;
|
|
USBCTRL_BASE = $50100000;
|
|
USBCTRL_DPRAM_BASE = $50100000;
|
|
USBCTRL_REGS_BASE = $50110000;
|
|
PIO0_BASE = $50200000;
|
|
PIO1_BASE = $50300000;
|
|
XIP_AUX_BASE = $50400000;
|
|
SIO_BASE = $d0000000;
|
|
PPB_BASE = $e0000000;
|
|
|
|
var
|
|
SysInfo : TSysInfo_Registers absolute SYSINFO_BASE;
|
|
SysCfg : TSYSCFG_REGISTERS absolute SYSCFG_BASE;
|
|
Clocks : TCLOCKS_Registers absolute CLOCKS_BASE;
|
|
Resets : TRESETS_Registers absolute RESETS_BASE;
|
|
PSM : TPSM_Registers absolute PSM_BASE;
|
|
IOBANK0 : TIOBANK0_Registers absolute IO_BANK0_BASE;
|
|
IOQSPI : TIOQSPI_Registers absolute IO_QSPI_BASE;
|
|
PADSBANK0 : TPADSBANK0_Registers absolute PADS_BANK0_BASE;
|
|
PADSQSPI : TPADSQSPI_Registers absolute PADS_QSPI_BASE;
|
|
XOSC : TXOSC_Registers absolute XOSC_BASE;
|
|
PLLSYS : TPLL_Registers absolute PLL_SYS_BASE;
|
|
PLLUSB : TPLL_Registers absolute PLL_USB_BASE;
|
|
BUSCTRL : TBUSCTRL_Registers absolute BUSCTRL_BASE;
|
|
UART0 : TUART_Registers absolute UART0_BASE;
|
|
UART1 : TUART_Registers absolute UART1_BASE;
|
|
SPI0 : TSPI_Registers absolute SPI0_BASE;
|
|
SPI1 : TSPI_Registers absolute SPI1_BASE;
|
|
I2C0 : TI2C_Registers absolute I2C0_BASE;
|
|
I2C1 : TI2C_Registers absolute I2C1_BASE;
|
|
ADC : TADC_Registers absolute ADC_BASE;
|
|
PWM : TPWM_Registers absolute PWM_BASE;
|
|
TIMER : TTIMER_Registers absolute TIMER_BASE;
|
|
WATCHDOG : TWATCHDOG_Registers absolute WATCHDOG_BASE;
|
|
RTC : TRTC_Registers absolute RTC_BASE;
|
|
ROSC : TROSC_Registers absolute ROSC_BASE;
|
|
VREGANDCHIPRESET : TVREGANDCHIPRESET_Registers absolute VREG_AND_CHIP_RESET_BASE;
|
|
DMA : TDMA_Registers absolute DMA_BASE;
|
|
//USBCTRL_BASE = $50100000
|
|
//USBCTRL_DPRAM_BASE = $50100000
|
|
USB : TUSB_Registers absolute USBCTRL_REGS_BASE;
|
|
PIO0 : TPIO_Registers absolute PIO0_BASE;
|
|
PIO1 : TPIO_Registers absolute PIO1_BASE;
|
|
//XIP_AUX_BASE = $50400000
|
|
SIO : TSIO_Registers absolute SIO_BASE;
|
|
|
|
implementation
|
|
|
|
procedure NMI_Handler; external name 'NMI_Handler';
|
|
procedure HardFault_Handler; external name 'HardFault_Handler';
|
|
procedure SVC_Handler; external name 'SVC_Handler';
|
|
procedure PendSV_Handler; external name 'PendSV_Handler';
|
|
procedure SysTick_Handler; external name 'SysTick_Handler';
|
|
procedure TIMER_IRQ_0_Handler; external name 'TIMER_IRQ_0_Handler';
|
|
procedure TIMER_IRQ_1_Handler; external name 'TIMER_IRQ_1_Handler';
|
|
procedure TIMER_IRQ_2_Handler; external name 'TIMER_IRQ_2_Handler';
|
|
procedure TIMER_IRQ_3_Handler; external name 'TIMER_IRQ_3_Handler';
|
|
procedure PWM_IRQ_WRAP_Handler; external name 'PWM_IRQ_WRAP_Handler';
|
|
procedure USBCTRL_IRQ_Handler; external name 'USBCTRL_IRQ_Handler';
|
|
procedure XIP_IRQ_Handler; external name 'XIP_IRQ_Handler';
|
|
procedure PIO0_IRQ_0_Handler; external name 'PIO0_IRQ_0_Handler';
|
|
procedure PIO0_IRQ_1_Handler; external name 'PIO0_IRQ_1_Handler';
|
|
procedure PIO1_IRQ_0_Handler; external name 'PIO1_IRQ_0_Handler';
|
|
procedure PIO1_IRQ_1_Handler; external name 'PIO1_IRQ_1_Handler';
|
|
procedure DMA_IRQ_0_Handler; external name 'DMA_IRQ_0_Handler';
|
|
procedure DMA_IRQ_1_Handler; external name 'DMA_IRQ_1_Handler';
|
|
procedure IO_IRQ_BANK0_Handler; external name 'IO_IRQ_BANK0_Handler';
|
|
procedure IO_IRQ_QSPI_Handler; external name 'IO_IRQ_QSPI_Handler';
|
|
procedure SIO_IRQ_PROC0_Handler; external name 'SIO_IRQ_PROC0_Handler';
|
|
procedure SIO_IRQ_PROC1_Handler; external name 'SIO_IRQ_PROC1_Handler';
|
|
procedure CLOCKS_IRQ_Handler; external name 'CLOCKS_IRQ_Handler';
|
|
procedure SPI0_IRQ_Handler; external name 'SPI0_IRQ_Handler';
|
|
procedure SPI1_IRQ_Handler; external name 'SPI1_IRQ_Handler';
|
|
procedure UART0_IRQ_Handler; external name 'UART0_IRQ_Handler';
|
|
procedure UART1_IRQ_Handler; external name 'UART1_IRQ_Handler';
|
|
procedure ADC_IRQ_FIFO_Handler; external name 'ADC_IRQ_FIFO_Handler';
|
|
procedure I2C0_IRQ_Handler; external name 'I2C0_IRQ_Handler';
|
|
procedure I2C1_IRQ_Handler; external name 'I2C1_IRQ_Handler';
|
|
procedure RTC_IRQ_Handler; external name 'RTC_IRQ_Handler';
|
|
|
|
{$i cortexm0p_start.inc}
|
|
|
|
procedure Vectors; assembler; nostackframe;
|
|
label interrupt_vectors;
|
|
asm
|
|
.section ".init.interrupt_vectors"
|
|
interrupt_vectors:
|
|
.long _stack_top
|
|
.long Startup
|
|
.long NMI_Handler
|
|
.long HardFault_Handler
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long SVC_Handler
|
|
.long 0
|
|
.long 0
|
|
.long PendSV_Handler
|
|
.long SysTick_Handler
|
|
.long TIMER_IRQ_0_Handler
|
|
.long TIMER_IRQ_1_Handler
|
|
.long TIMER_IRQ_2_Handler
|
|
.long TIMER_IRQ_3_Handler
|
|
.long PWM_IRQ_WRAP_Handler
|
|
.long USBCTRL_IRQ_Handler
|
|
.long XIP_IRQ_Handler
|
|
.long PIO0_IRQ_0_Handler
|
|
.long PIO0_IRQ_1_Handler
|
|
.long PIO1_IRQ_0_Handler
|
|
.long PIO1_IRQ_1_Handler
|
|
.long DMA_IRQ_0_Handler
|
|
.long DMA_IRQ_1_Handler
|
|
.long IO_IRQ_BANK0_Handler
|
|
.long IO_IRQ_QSPI_Handler
|
|
.long SIO_IRQ_PROC0_Handler
|
|
.long SIO_IRQ_PROC1_Handler
|
|
.long CLOCKS_IRQ_Handler
|
|
.long SPI0_IRQ_Handler
|
|
.long SPI1_IRQ_Handler
|
|
.long UART0_IRQ_Handler
|
|
.long UART1_IRQ_Handler
|
|
.long ADC_IRQ_FIFO_Handler
|
|
.long I2C0_IRQ_Handler
|
|
.long I2C1_IRQ_Handler
|
|
.long RTC_IRQ_Handler
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
.long 0
|
|
|
|
|
|
.weak NMI_Handler
|
|
.weak HardFault_Handler
|
|
.weak SVC_Handler
|
|
.weak PendSV_Handler
|
|
.weak SysTick_Handler
|
|
.weak TIMER_IRQ_0_Handler
|
|
.weak TIMER_IRQ_1_Handler
|
|
.weak TIMER_IRQ_2_Handler
|
|
.weak TIMER_IRQ_3_Handler
|
|
.weak PWM_IRQ_WRAP_Handler
|
|
.weak USBCTRL_IRQ_Handler
|
|
.weak XIP_IRQ_Handler
|
|
.weak PIO0_IRQ_0_Handler
|
|
.weak PIO0_IRQ_1_Handler
|
|
.weak PIO1_IRQ_0_Handler
|
|
.weak PIO1_IRQ_1_Handler
|
|
.weak DMA_IRQ_0_Handler
|
|
.weak DMA_IRQ_1_Handler
|
|
.weak IO_IRQ_BANK0_Handler
|
|
.weak IO_IRQ_QSPI_Handler
|
|
.weak SIO_IRQ_PROC0_Handler
|
|
.weak SIO_IRQ_PROC1_Handler
|
|
.weak CLOCKS_IRQ_Handler
|
|
.weak SPI0_IRQ_Handler
|
|
.weak SPI1_IRQ_Handler
|
|
.weak UART0_IRQ_Handler
|
|
.weak UART1_IRQ_Handler
|
|
.weak ADC_IRQ_FIFO_Handler
|
|
.weak I2C0_IRQ_Handler
|
|
.weak I2C1_IRQ_Handler
|
|
.weak RTC_IRQ_Handler
|
|
|
|
.set NMI_Handler, _NMI_Handler
|
|
.set HardFault_Handler, _HardFault_Handler
|
|
.set SVC_Handler, _SVC_Handler
|
|
.set PendSV_Handler, _PendSV_Handler
|
|
.set SysTick_Handler, _SysTick_Handler
|
|
.set TIMER_IRQ_0_Handler, Haltproc
|
|
.set TIMER_IRQ_1_Handler, Haltproc
|
|
.set TIMER_IRQ_2_Handler, Haltproc
|
|
.set TIMER_IRQ_3_Handler, Haltproc
|
|
.set PWM_IRQ_WRAP_Handler, Haltproc
|
|
.set USBCTRL_IRQ_Handler, Haltproc
|
|
.set XIP_IRQ_Handler, Haltproc
|
|
.set PIO0_IRQ_0_Handler, Haltproc
|
|
.set PIO0_IRQ_1_Handler, Haltproc
|
|
.set PIO1_IRQ_0_Handler, Haltproc
|
|
.set PIO1_IRQ_1_Handler, Haltproc
|
|
.set DMA_IRQ_0_Handler, Haltproc
|
|
.set DMA_IRQ_1_Handler, Haltproc
|
|
.set IO_IRQ_BANK0_Handler, Haltproc
|
|
.set IO_IRQ_QSPI_Handler, Haltproc
|
|
.set SIO_IRQ_PROC0_Handler, Haltproc
|
|
.set SIO_IRQ_PROC1_Handler, Haltproc
|
|
.set CLOCKS_IRQ_Handler, Haltproc
|
|
.set SPI0_IRQ_Handler, Haltproc
|
|
.set SPI1_IRQ_Handler, Haltproc
|
|
.set UART0_IRQ_Handler, Haltproc
|
|
.set UART1_IRQ_Handler, Haltproc
|
|
.set ADC_IRQ_FIFO_Handler, Haltproc
|
|
.set I2C0_IRQ_Handler, Haltproc
|
|
.set I2C1_IRQ_Handler, Haltproc
|
|
.set RTC_IRQ_Handler, Haltproc
|
|
.text
|
|
end;
|
|
end.
|