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625 lines
26 KiB
ObjectPascal
625 lines
26 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate ARM assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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tarmmoddivnode = class(tmoddivnode)
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function first_moddivint: tnode;override;
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procedure pass_generate_code;override;
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end;
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tarmnotnode = class(tcgnotnode)
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procedure second_boolean;override;
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end;
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tarmunaryminusnode = class(tcgunaryminusnode)
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function pass_1: tnode; override;
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procedure second_float;override;
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end;
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tarmshlshrnode = class(tcgshlshrnode)
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procedure second_64bit;override;
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function first_shlshr64bitint: tnode; override;
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end;
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implementation
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uses
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globtype,
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cutils,verbose,globals,constexp,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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symtype,symconst,symtable,
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cgbase,cgobj,hlcgobj,cgutils,
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pass_2,procinfo,
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ncon,ncnv,ncal,ninl,
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cpubase,cpuinfo,
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ncgutil,
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nadd,pass_1,symdef;
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{*****************************************************************************
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TARMMODDIVNODE
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*****************************************************************************}
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function tarmmoddivnode.first_moddivint: tnode;
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var
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power : longint;
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begin
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{We can handle all cases of constant division}
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if not(cs_check_overflow in current_settings.localswitches) and
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(right.nodetype=ordconstn) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) and
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{Only the ARM and thumb2-isa support umull and smull, which are required for arbitary division by const optimization}
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(GenerateArmCode or
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GenerateThumb2Code or
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(ispowerof2(tordconstnode(right).value,power) or
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(tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1))
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)
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) then
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result:=nil
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else if ((GenerateThumbCode or GenerateThumb2Code) and (CPUARM_HAS_THUMB_IDIV in cpu_capabilities[current_settings.cputype])) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) then
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result:=nil
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else if ((GenerateThumbCode or GenerateThumb2Code) and (CPUARM_HAS_THUMB_IDIV in cpu_capabilities[current_settings.cputype])) and
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(nodetype=modn) and
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not(is_64bitint(resultdef)) then
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begin
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if (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) and
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(tordconstnode(right).value<=256) and
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(tordconstnode(right).value>0) then
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result:=caddnode.create_internal(andn,left,cordconstnode.create(tordconstnode(right).value-1,sinttype,false))
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else
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begin
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result:=caddnode.create_internal(subn,left,caddnode.create_internal(muln,right,cmoddivnode.Create(divn,left.getcopy,right.getcopy)));
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right:=nil;
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end;
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left:=nil;
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firstpass(result);
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end
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else if (nodetype=modn) and
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(is_signed(left.resultdef)) and
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(right.nodetype=ordconstn) and
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(tordconstnode(right).value=2) then
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begin
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// result:=(0-(left and 1)) and (1+(sarlongint(left,31) shl 1))
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result:=caddnode.create_internal(andn,caddnode.create_internal(subn,cordconstnode.create(0,sinttype,false),caddnode.create_internal(andn,left,cordconstnode.create(1,sinttype,false))),
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caddnode.create_internal(addn,cordconstnode.create(1,sinttype,false),
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cshlshrnode.create(shln,cinlinenode.create(in_sar_x_y,false,ccallparanode.create(cordconstnode.create(31,sinttype,false),ccallparanode.Create(left.getcopy,nil))),cordconstnode.create(1,sinttype,false))));
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left:=nil;
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firstpass(result);
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end
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else
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result:=inherited first_moddivint;
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{ we may not change the result type here }
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if assigned(result) and (torddef(result.resultdef).ordtype<>torddef(resultdef).ordtype) then
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inserttypeconv(result,resultdef);
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end;
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procedure tarmmoddivnode.pass_generate_code;
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var
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power : longint;
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numerator,
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helper1,
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helper2,
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resultreg : tregister;
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size : Tcgsize;
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so : tshifterop;
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procedure genOrdConstNodeDiv;
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begin
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if tordconstnode(right).value=0 then
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internalerror(2005061701)
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else if tordconstnode(right).value=1 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, numerator, resultreg)
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else if (tordconstnode(right).value = int64(-1)) then
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begin
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// note: only in the signed case possible..., may overflow
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if cs_check_overflow in current_settings.localswitches then
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MVN,
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resultreg,numerator),toppostfix(ord(cs_check_overflow in current_settings.localswitches)*ord(PF_S))));
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end
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else if ispowerof2(tordconstnode(right).value,power) then
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begin
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if (is_signed(right.resultdef)) then
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begin
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helper1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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helper2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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if power = 1 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,numerator,helper1)
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,31,numerator,helper1);
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if GenerateThumbCode then
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begin
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,32-power,helper1);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ADD,helper2,numerator,helper1));
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end
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else
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begin
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shifterop_reset(so);
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so.shiftmode:=SM_LSR;
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so.shiftimm:=32-power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,helper2,numerator,helper1,so));
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end;
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,power,helper2,resultreg);
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end
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,power,numerator,resultreg)
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end
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else {Everything else is handled the generic code}
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cg.g_div_const_reg_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),
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tordconstnode(right).value.svalue,numerator,resultreg);
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end;
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{
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procedure genOrdConstNodeMod;
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var
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modreg, maskreg, tempreg : tregister;
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begin
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061702);
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end
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else if (abs(tordconstnode(right).value.svalue) = 1) then
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begin
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// x mod +/-1 is always zero
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, 0, resultreg);
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end
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else if (ispowerof2(tordconstnode(right).value, power)) then
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begin
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if (is_signed(right.resultdef)) then begin
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tempreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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maskreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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modreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, abs(tordconstnode(right).value.svalue)-1, modreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, 31, numerator, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, numerator, modreg, tempreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ANDC, maskreg, maskreg, modreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC, modreg, tempreg, 0));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBFE, modreg, modreg, modreg));
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, modreg, maskreg, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_INT, maskreg, tempreg, resultreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, tordconstnode(right).value.svalue-1, numerator, resultreg);
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end;
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end else begin
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genOrdConstNodeDiv();
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_MUL, OS_INT, tordconstnode(right).value.svalue, resultreg, resultreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, resultreg, numerator, resultreg);
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end;
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end;
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}
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begin
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secondpass(left);
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secondpass(right);
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if ((GenerateThumbCode or GenerateThumb2Code) and (CPUARM_HAS_THUMB_IDIV in cpu_capabilities[current_settings.cputype])) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) then
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begin
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size:=def_cgsize(left.resultdef);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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location_copy(location,left.location);
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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if (right.nodetype=ordconstn) and
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((tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1)) or
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(tordconstnode(right).value=0) or
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ispowerof2(tordconstnode(right).value,power)) then
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begin
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numerator:=left.location.register;
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genOrdConstNodeDiv;
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end
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else
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,left.resultdef,true);
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if is_signed(left.resultdef) or
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is_signed(right.resultdef) then
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_IDIV,OS_INT,right.location.register,left.location.register,location.register)
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else
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_DIV,OS_INT,right.location.register,left.location.register,location.register);
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end;
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end
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else
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begin
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resultdef);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,
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left.resultdef,left.resultdef,true);
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location_copy(location,left.location);
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numerator:=location.register;
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resultreg:=location.register;
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if location.loc=LOC_CREGISTER then
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begin
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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end
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else if (nodetype=modn) or (right.nodetype=ordconstn) then
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begin
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// for a modulus op, and for const nodes we need the result register
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// to be an extra register
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resultreg:=cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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if (right.nodetype=ordconstn) and
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(CPUARM_HAS_UMULL in cpu_capabilities[current_settings.cputype]) then
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begin
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if nodetype=divn then
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genOrdConstNodeDiv
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else
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// genOrdConstNodeMod;
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end;
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location.register:=resultreg;
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end;
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{ unsigned division/module can only overflow in case of division by zero }
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{ (but checking this overflow flag is more convoluted than performing a }
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{ simple comparison with 0) }
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if is_signed(right.resultdef) then
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cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
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end;
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{*****************************************************************************
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TARMNOTNODE
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*****************************************************************************}
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procedure tarmnotnode.second_boolean;
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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}
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if not handle_locjump then
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begin
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE,
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LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF :
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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{*****************************************************************************
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TARMUNARYMINUSNODE
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*****************************************************************************}
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function tarmunaryminusnode.pass_1: tnode;
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var
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procname: string[31];
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fdef : tdef;
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begin
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if (current_settings.fputype=fpu_soft) and
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(left.resultdef.typ=floatdef) then
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begin
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result:=nil;
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firstpass(left);
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expectloc:=LOC_REGISTER;
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exit;
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end;
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if (current_settings.fputype<>fpu_fpv4_s16) or
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(tfloatdef(resultdef).floattype=s32real) then
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exit(inherited pass_1);
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result:=nil;
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firstpass(left);
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if codegenerror then
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exit;
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if (left.resultdef.typ=floatdef) then
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begin
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case tfloatdef(resultdef).floattype of
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s64real:
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begin
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procname:='float64_sub';
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fdef:=search_system_type('FLOAT64').typedef;
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end;
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else
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internalerror(2005082801);
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end;
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result:=ctypeconvnode.create_internal(ccallnode.createintern(procname,ccallparanode.create(
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ctypeconvnode.create_internal(left,fDef),
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ccallparanode.create(ctypeconvnode.create_internal(crealconstnode.create(0,resultdef),fdef),nil))),resultdef);
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left:=nil;
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end
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else
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begin
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if (left.resultdef.typ=floatdef) then
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expectloc:=LOC_FPUREGISTER
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else if (left.resultdef.typ=orddef) then
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expectloc:=LOC_REGISTER;
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end;
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end;
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procedure tarmunaryminusnode.second_float;
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var
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pf: TOpPostfix;
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begin
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secondpass(left);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
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location:=left.location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSF,
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location.register,left.location.register,0),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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end;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv4,
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fpu_vfpv3_d16:
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begin
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location:=left.location;
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if (left.location.loc=LOC_CMMREGISTER) then
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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if (tfloatdef(left.resultdef).floattype=s32real) then
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pf:=PF_F32
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VNEG,
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location.register,left.location.register), pf));
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end;
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fpu_fpv4_s16:
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begin
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location:=left.location;
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if (left.location.loc=LOC_CMMREGISTER) then
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VNEG,
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location.register,left.location.register), PF_F32));
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end;
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fpu_soft:
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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location:=left.location;
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case location.size of
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OS_32:
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.register);
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OS_64:
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.registerhi);
|
|
else
|
|
internalerror(2014033101);
|
|
end;
|
|
end
|
|
else
|
|
internalerror(2009112602);
|
|
end;
|
|
end;
|
|
|
|
function tarmshlshrnode.first_shlshr64bitint: tnode;
|
|
begin
|
|
if GenerateThumbCode or GenerateThumb2Code then
|
|
result:=inherited
|
|
else
|
|
result := nil;
|
|
end;
|
|
|
|
procedure tarmshlshrnode.second_64bit;
|
|
var
|
|
v : TConstExprInt;
|
|
so: tshifterop;
|
|
lreg, resreg: TRegister64;
|
|
|
|
procedure emit_instr(p: tai);
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(p);
|
|
end;
|
|
|
|
{This code is build like it gets called with sm=SM_LSR all the time, for SM_LSL dst* and src* have to be reversed}
|
|
procedure shift_less_than_32(srchi, srclo, dsthi, dstlo: TRegister; shiftval: Byte; sm: TShiftMode);
|
|
begin
|
|
shifterop_reset(so);
|
|
|
|
so.shiftimm:=shiftval;
|
|
so.shiftmode:=sm;
|
|
emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dstlo, srclo, so));
|
|
emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dsthi, srchi, so));
|
|
|
|
if sm = SM_LSR then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
|
|
so.shiftimm:=32-shiftval;
|
|
emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, dstlo, dstlo, srchi, so));
|
|
|
|
end;
|
|
|
|
{This code is build like it gets called with sm=SM_LSR all the time, for SM_LSL dst* and src* have to be reversed
|
|
This will generate
|
|
mov shiftval1, shiftval
|
|
cmp shiftval1, #64
|
|
movcs shiftval1, #64
|
|
rsb shiftval2, shiftval1, #32
|
|
mov dstlo, srclo, lsr shiftval1
|
|
mov dsthi, srchi, lsr shiftval1
|
|
orr dstlo, srchi, lsl shiftval2
|
|
subs shiftval2, shiftval1, #32
|
|
movpl dstlo, srchi, lsr shiftval2
|
|
}
|
|
procedure shift_by_variable(srchi, srclo, dsthi, dstlo, shiftval: TRegister; sm: TShiftMode);
|
|
var
|
|
shiftval1,shiftval2:TRegister;
|
|
begin
|
|
shifterop_reset(so);
|
|
shiftval1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, shiftval, shiftval1);
|
|
|
|
{The ARM barrel shifter only considers the lower 8 bits of a register for the shift}
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_instr(taicpu.op_reg_const(A_CMP, shiftval1, 64));
|
|
emit_instr(setcondition(taicpu.op_reg_const(A_MOV, shiftval1, 64), C_CS));
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
|
|
{Calculate how much the upper register needs to be shifted left}
|
|
emit_instr(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval1, 32));
|
|
|
|
so.shiftmode:=sm;
|
|
so.rs:=shiftval1;
|
|
|
|
{Shift and zerofill the hi+lo register}
|
|
emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dstlo, srclo, so));
|
|
emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dsthi, srchi, so));
|
|
|
|
{Fold in the lower 32-shiftval bits}
|
|
if sm = SM_LSR then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
|
|
so.rs:=shiftval2;
|
|
emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, dstlo, dstlo, srchi, so));
|
|
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval1, 32), PF_S));
|
|
|
|
so.shiftmode:=sm;
|
|
emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, dstlo, srchi, so), C_PL));
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
end;
|
|
|
|
begin
|
|
if GenerateThumbCode or GenerateThumb2Code then
|
|
begin
|
|
inherited;
|
|
exit;
|
|
end;
|
|
|
|
location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
|
|
location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
|
|
{ load left operator in a register }
|
|
if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
|
|
(left.location.size<>OS_64) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
|
|
|
|
lreg := left.location.register64;
|
|
resreg := location.register64;
|
|
shifterop_reset(so);
|
|
|
|
{ shifting by a constant directly coded: }
|
|
if (right.nodetype=ordconstn) then
|
|
begin
|
|
v:=Tordconstnode(right).value and 63;
|
|
{Single bit shift}
|
|
if v = 1 then
|
|
if nodetype=shln then
|
|
begin
|
|
{Shift left by one by 2 simple 32bit additions}
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, resreg.reglo, lreg.reglo, lreg.reglo), PF_S));
|
|
emit_instr(taicpu.op_reg_reg_reg(A_ADC, resreg.reghi, lreg.reghi, lreg.reghi));
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
end
|
|
else
|
|
begin
|
|
{Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry}
|
|
shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1;
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, resreg.reghi, lreg.reghi, so), PF_S));
|
|
so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount}
|
|
emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, resreg.reglo, lreg.reglo, so));
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
end
|
|
{Clear one register and use the cg to generate a normal 32-bit shift}
|
|
else if v >= 32 then
|
|
if nodetype=shln then
|
|
begin
|
|
emit_instr(taicpu.op_reg_const(A_MOV, resreg.reglo, 0));
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,v.uvalue-32,lreg.reglo,resreg.reghi);
|
|
end
|
|
else
|
|
begin
|
|
emit_instr(taicpu.op_reg_const(A_MOV, resreg.reghi, 0));
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,v.uvalue-32,lreg.reghi,resreg.reglo);
|
|
end
|
|
{Shift LESS than 32, thats the tricky one}
|
|
else if (v < 32) and (v > 1) then
|
|
if nodetype=shln then
|
|
shift_less_than_32(lreg.reglo, lreg.reghi, resreg.reglo, resreg.reghi, v.uvalue, SM_LSL)
|
|
else
|
|
shift_less_than_32(lreg.reghi, lreg.reglo, resreg.reghi, resreg.reglo, v.uvalue, SM_LSR);
|
|
end
|
|
else
|
|
begin
|
|
{ force right operator into a register }
|
|
if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
|
|
(right.location.size<>OS_32) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,u32inttype,true);
|
|
|
|
if nodetype = shln then
|
|
shift_by_variable(lreg.reglo, lreg.reghi, resreg.reglo, resreg.reghi, right.location.register, SM_LSL)
|
|
else
|
|
shift_by_variable(lreg.reghi, lreg.reglo, resreg.reghi, resreg.reglo, right.location.register, SM_LSR);
|
|
end;
|
|
end;
|
|
|
|
|
|
begin
|
|
cmoddivnode:=tarmmoddivnode;
|
|
cnotnode:=tarmnotnode;
|
|
cunaryminusnode:=tarmunaryminusnode;
|
|
cshlshrnode:=tarmshlshrnode;
|
|
end.
|