sergei 578348817b * MIPS: some progress with linker: ... * Fixed values of R_MIPS_GOT_HI16/LO16. + Implemented elf_mips_relocname + Check R_MIPS_PC16 relocations for overflows + Handle R_MIPS_JALR optimization hint. git-svn-id: trunk@33240 -		2016-03-13 17:13:23 +00:00
..
aasmcpu.pas	* MIPS: reworked and fixed procedure fixup_jmps:	2016-02-12 13:53:04 +00:00
aoptcpu.pas	+ Next portion of MIPS peephole optimizations. Get more aggressive and do more than a single pass if needed, enabling optimization of instructions that logically turn into MOVE due to register renaming.	2016-02-13 12:33:30 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* MIPS: Fixed code generation for PIC calls to local functions. Uncovered by r32803, before that the buggy branch was never taken because all functions were global.	2016-01-04 18:13:18 +00:00
cpubase.pas	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
cpuelf.pas	* MIPS: some progress with linker:	2016-03-13 17:13:23 +00:00
cpugas.pas	- MIPS: removed the ugly hack of splitting LDC1/SDC1 instructions into pairs of LWC1/SWC1 at assembler writer level. It probably was there as a workaround for insufficient alignment of double-precision variables, which was present once, but fixed a long time ago.	2016-02-11 15:09:19 +00:00
cpuinfo.pas	Moved tcontrollerdatatype out into cpuinfo.	2015-09-07 20:36:54 +00:00
cpunode.pas
cpupara.pas	* support marking defs created via the getreusable*() class methods as	2015-11-04 20:46:18 +00:00
cpupi.pas	* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.	2014-04-02 14:17:23 +00:00
cputarg.pas
hlcgcpu.pas	* moved g_external_wrapper() to the hlcg, and also g_intf_wrapper() because	2014-08-19 20:22:54 +00:00
itcpugas.pas	* Removed unused vars for mipsel compiler.	2015-09-17 15:46:30 +00:00
mipsreg.dat	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
ncpuadd.pas	* Removed unused vars for mipsel compiler.	2015-09-17 15:46:30 +00:00
ncpucall.pas
ncpucnv.pas	* replaced current_procinfo.currtrue/falselabel with storing the true/false	2015-08-27 18:28:57 +00:00
ncpuinln.pas
ncpuld.pas
ncpumat.pas	* synchronised with r28168 of trunk	2014-07-05 21:30:28 +00:00
ncpuset.pas	* Removed unused vars for mipsel compiler.	2015-09-17 15:46:30 +00:00
opcode.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
racpugas.pas	* Handle possible relocation types in assembler reader using a single AS_RELTYPE token, rather than with individual tokens for each case. Since possible relocations are target-dependent, this will allow to support any amount of them without modifying the base tattreader class.	2016-02-23 21:28:46 +00:00
rgcpu.pas	* synchronized with privatetrunk till r30095	2015-03-05 20:32:15 +00:00
rmipscon.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
rmipsdwf.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgas.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsgss.inc
rmipsnor.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsnum.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsrni.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssri.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssta.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipsstd.inc	* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).	2014-06-17 23:15:34 +00:00
rmipssup.inc	* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.	2014-06-22 22:01:44 +00:00
strinst.inc	+ MIPS: added movn and movz instructions.	2014-06-19 22:44:17 +00:00
symcpu.pas	o fixes handling of iso i/o parameters/program parameters:	2015-05-01 20:58:31 +00:00