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c482bafdaf
first 16 registers in RISC-V RVE and RVEC modes. However, there was still code in tcpuparamanager.create_paraloc_info_intern that allowed the allocation of up to register X17 in RVE and RVEC modes. Modified this function to take the processor mode into account and restrict it to X0..X15 in RVE and RVEC modes. Also put conditional code in setjump.inc assembler code to only set the first 16 registers in RVE and RVEC modes. The entire embedded-riscv32 RTL can now compile successfuly in RVEC mode.
70 lines
1.4 KiB
PHP
70 lines
1.4 KiB
PHP
var
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_stack_top: record end; external name '_stack_top';
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_data: record end; external name '_data';
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_edata: record end; external name '_edata';
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_text_start: record end; external name '_text_start';
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_etext: record end; external name '_etext';
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_bss_start: record end; external name '_bss_start';
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_bss_end: record end; external name '_bss_end';
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procedure Pascalmain; external name 'PASCALMAIN';
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procedure _haltproc; external Name '_haltproc';
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procedure HaltProc; noreturn;
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begin
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while true do;
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end;
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procedure InitMemAndStart; noreturn;
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var
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pdest, psrc, pend: PLongWord;
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begin
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pdest:=@_data;
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psrc:=@_etext;
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pend:=@_bss_start;
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while pdest<pend do
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begin
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pdest^:=psrc^;
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inc(pdest);
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inc(psrc);
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end;
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pend:=@_bss_end;
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while pdest<pend do
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begin
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pdest^:=0;
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inc(pdest);
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end;
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PASCALMAIN;
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HaltProc;
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end;
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procedure LowlevelStartup; assembler; nostackframe; [public, alias: '_START'];
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asm
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.weak ResetISR
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.set ResetISR, InitMemAndStart;
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.weak _haltproc
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.set _haltproc, HaltProc
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{ Initialize global Pointer }
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.option push
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.option norelax
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lui gp, %hi(_bss_start+0x800)
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addi gp, gp, %lo(_bss_start+0x800)
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.option pop
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{ Initialize Stack Pointer }
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.L1:
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auipc sp, %pcrel_hi(_stack_top)
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addi sp, sp, %pcrel_lo(.L1)
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{ Initialise FP to zero }
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addi fp, x0, 0
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jal x0, HandleArchSpecificReset
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end;
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