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https://gitlab.com/freepascal.org/fpc/source.git
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e815b923d5
* fixed downsizing the precision of floating point values
* floating point constants are now treated using only the minimal
precision required (e.g. 2.0 is now a single, 1.1 extended etc)
(Delphi compatible)
git-svn-id: trunk@5927 -
489 lines
18 KiB
ObjectPascal
489 lines
18 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate generic mathematical nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncgmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,cpubase,cgbase;
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type
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tcgunaryminusnode = class(tunaryminusnode)
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protected
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{ This routine is called to change the sign of the
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floating point value in the floating point
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register r.
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This routine should be overriden, since
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the generic version is not optimal at all. The
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generic version assumes that floating
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point values are stored in the register
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in IEEE-754 format.
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}
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procedure emit_float_sign_change(r: tregister; _size : tcgsize);virtual;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;virtual;abstract;
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{$endif SUPPORT_MMX}
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{$ifndef cpu64bit}
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procedure second_64bit;virtual;
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{$endif cpu64bit}
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procedure second_integer;virtual;
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procedure second_float;virtual;
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public
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procedure pass_generate_code;override;
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end;
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tcgmoddivnode = class(tmoddivnode)
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procedure pass_generate_code;override;
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protected
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{ This routine must do an actual 32-bit division, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the division must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a divide.
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}
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procedure emit_div_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
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{ This routine must do an actual 32-bit modulo, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the modulo must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a modulo.
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}
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procedure emit_mod_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
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{$ifndef cpu64bit}
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{ This routine must do an actual 64-bit division, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the division must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a divide.
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Currently, this routine should only be implemented on
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64-bit systems, otherwise a helper is called in 1st pass.
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}
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procedure emit64_div_reg_reg(signed: boolean;denum,num : tregister64);virtual;
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{$endif cpu64bit}
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end;
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tcgshlshrnode = class(tshlshrnode)
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{$ifndef cpu64bit}
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procedure second_64bit;virtual;
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{$endif cpu64bit}
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procedure second_integer;virtual;
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procedure pass_generate_code;override;
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end;
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tcgnotnode = class(tnotnode)
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protected
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procedure second_boolean;virtual;abstract;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;virtual;abstract;
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{$endif SUPPORT_MMX}
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{$ifndef cpu64bit}
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procedure second_64bit;virtual;
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{$endif cpu64bit}
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procedure second_integer;virtual;
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public
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procedure pass_generate_code;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,aasmbase,aasmtai,aasmdata,aasmcpu,defutil,
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parabase,
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pass_2,
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ncon,
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tgobj,ncgutil,cgobj,cgutils,paramgr
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{$ifndef cpu64bit}
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,cg64f32
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{$endif cpu64bit}
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;
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{*****************************************************************************
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TCGUNARYMINUSNODE
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*****************************************************************************}
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procedure tcgunaryminusnode.emit_float_sign_change(r: tregister; _size : tcgsize);
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var
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href,
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href2 : treference;
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begin
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{ get a temporary memory reference to store the floating
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point value
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}
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tg.gettemp(current_asmdata.CurrAsmList,tcgsize2size[_size],tt_normal,href);
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{ store the floating point value in the temporary memory area }
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cg.a_loadfpu_reg_ref(current_asmdata.CurrAsmList,_size,_size,r,href);
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{ only single and double ieee are supported, for little endian
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the signed bit is in the second dword }
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href2:=href;
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case _size of
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OS_F64 :
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if target_info.endian = endian_little then
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inc(href2.offset,4);
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OS_F32 :
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;
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else
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internalerror(200406021);
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end;
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{ flip sign-bit (bit 31/63) of single/double }
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cg.a_op_const_ref(current_asmdata.CurrAsmList,OP_XOR,OS_32,aint($80000000),href2);
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,_size,_size,href,r);
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tg.ungetiftemp(current_asmdata.CurrAsmList,href);
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end;
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{$ifndef cpu64bit}
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procedure tcgunaryminusnode.second_64bit;
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begin
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secondpass(left);
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{ load left operator in a register }
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location_copy(location,left.location);
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location_force_reg(current_asmdata.CurrAsmList,location,OS_64,false);
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cg64.a_op64_loc_reg(current_asmdata.CurrAsmList,OP_NEG,OS_64,
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location,joinreg64(location.register64.reglo,location.register64.reghi));
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end;
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{$endif cpu64bit}
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procedure tcgunaryminusnode.second_float;
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begin
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secondpass(left);
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE :
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begin
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
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left.location.size,location.size,
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left.location.reference,location.register);
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emit_float_sign_change(location.register,def_cgsize(left.resultdef));
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end;
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LOC_FPUREGISTER:
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begin
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location.register:=left.location.register;
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emit_float_sign_change(location.register,def_cgsize(left.resultdef));
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end;
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LOC_CFPUREGISTER:
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begin
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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cg.a_loadfpu_reg_reg(current_asmdata.CurrAsmList,left.location.size,location.size,left.location.register,location.register);
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emit_float_sign_change(location.register,def_cgsize(left.resultdef));
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end;
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else
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internalerror(200306021);
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end;
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end;
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procedure tcgunaryminusnode.second_integer;
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begin
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secondpass(left);
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{ load left operator in a register }
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location_copy(location,left.location);
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location_force_reg(current_asmdata.CurrAsmList,location,OS_SINT,false);
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,OS_SINT,location.register,location.register);
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end;
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procedure tcgunaryminusnode.pass_generate_code;
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begin
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{$ifndef cpu64bit}
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if is_64bit(left.resultdef) then
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second_64bit
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else
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{$endif cpu64bit}
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{$ifdef SUPPORT_MMX}
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if (cs_mmx in current_settings.localswitches) and is_mmx_able_array(left.resultdef) then
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second_mmx
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else
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{$endif SUPPORT_MMX}
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if (left.resultdef.typ=floatdef) then
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second_float
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else
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second_integer;
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end;
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{*****************************************************************************
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TCGMODDIVNODE
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*****************************************************************************}
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{$ifndef cpu64bit}
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procedure tcgmoddivnode.emit64_div_reg_reg(signed: boolean; denum,num:tregister64);
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begin
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{ handled in pass_1 already, unless pass_1 is
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overriden
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}
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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end;
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{$endif cpu64bit}
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procedure tcgmoddivnode.pass_generate_code;
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var
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hreg1 : tregister;
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hdenom : tregister;
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power : longint;
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hl : tasmlabel;
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paraloc1 : tcgpara;
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opsize : tcgsize;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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location_copy(location,left.location);
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{$ifndef cpu64bit}
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if is_64bit(resultdef) then
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begin
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if is_signed(left.resultdef) then
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opsize:=OS_S64
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else
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opsize:=OS_64;
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{ this code valid for 64-bit cpu's only ,
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otherwise helpers are called in pass_1
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}
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location_force_reg(current_asmdata.CurrAsmList,location,opsize,false);
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location_copy(location,left.location);
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location_force_reg(current_asmdata.CurrAsmList,right.location,opsize,false);
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emit64_div_reg_reg(is_signed(left.resultdef),
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joinreg64(right.location.register64.reglo,right.location.register64.reghi),
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joinreg64(location.register64.reglo,location.register64.reghi));
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end
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else
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{$endif cpu64bit}
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begin
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if is_signed(left.resultdef) then
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opsize:=OS_SINT
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else
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opsize:=OS_INT;
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{ put numerator in register }
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location_force_reg(current_asmdata.CurrAsmList,left.location,opsize,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and
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(right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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Begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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If is_signed(left.resultdef) Then
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Begin
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current_asmdata.getjumplabel(hl);
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_INT,OC_GT,0,hreg1,hl);
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if power=1 then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_ADD,OS_INT,1,hreg1)
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else
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_ADD,OS_INT,tordconstnode(right).value-1,hreg1);
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cg.a_label(current_asmdata.CurrAsmList,hl);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,power,hreg1);
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End
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Else { not signed }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,power,hreg1);
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End
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else
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begin
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{ bring denominator to hdenom }
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{ hdenom is always free, it's }
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{ only used for temporary }
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{ purposes }
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hdenom := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_loc_reg(current_asmdata.CurrAsmList,right.location.size,right.location,hdenom);
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{ verify if the divisor is zero, if so return an error
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immediately
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}
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current_asmdata.getjumplabel(hl);
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_INT,OC_NE,0,hdenom,hl);
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paraloc1.init;
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paramanager.getintparaloc(pocall_default,1,paraloc1);
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paramanager.allocparaloc(current_asmdata.CurrAsmList,paraloc1);
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cg.a_param_const(current_asmdata.CurrAsmList,OS_S32,200,paraloc1);
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paramanager.freeparaloc(current_asmdata.CurrAsmList,paraloc1);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_HANDLEERROR');
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paraloc1.done;
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cg.a_label(current_asmdata.CurrAsmList,hl);
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if nodetype = modn then
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emit_mod_reg_reg(is_signed(left.resultdef),hdenom,hreg1)
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else
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emit_div_reg_reg(is_signed(left.resultdef),hdenom,hreg1);
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end;
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location_reset(location,LOC_REGISTER,opsize);
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location.register:=hreg1;
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end;
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cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
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end;
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{*****************************************************************************
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TCGSHLRSHRNODE
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*****************************************************************************}
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{$ifndef cpu64bit}
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procedure tcgshlshrnode.second_64bit;
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begin
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{ already hanled in 1st pass }
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internalerror(2002081501);
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end;
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{$endif cpu64bit}
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procedure tcgshlshrnode.second_integer;
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var
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op : topcg;
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hcountreg : tregister;
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opsize : tcgsize;
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begin
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{ determine operator }
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case nodetype of
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shln: op:=OP_SHL;
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shrn: op:=OP_SHR;
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end;
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{ load left operators in a register }
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location_copy(location,left.location);
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if is_signed(left.resultdef) then
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opsize:=OS_SINT
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else
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opsize:=OS_INT;
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location_force_reg(current_asmdata.CurrAsmList,location,opsize,false);
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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{ l shl 32 should 0 imho, but neither TP nor Delphi do it in this way (FK)
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if right.value<=31 then
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}
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cg.a_op_const_reg(current_asmdata.CurrAsmList,op,location.size,
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tordconstnode(right).value and 31,location.register);
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{
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else
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emit_reg_reg(A_XOR,S_L,hregister1,
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hregister1);
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}
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end
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else
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begin
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{ load right operators in a register - this
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is done since most target cpu which will use this
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node do not support a shift count in a mem. location (cec)
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}
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if right.location.loc<>LOC_REGISTER then
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begin
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hcountreg:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_loc_reg(current_asmdata.CurrAsmList,right.location.size,right.location,hcountreg);
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end
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else
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hcountreg:=right.location.register;
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,op,opsize,hcountreg,location.register);
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end;
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end;
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procedure tcgshlshrnode.pass_generate_code;
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begin
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secondpass(left);
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secondpass(right);
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{$ifndef cpu64bit}
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if is_64bit(left.resultdef) then
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second_64bit
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else
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{$endif cpu64bit}
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second_integer;
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end;
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{*****************************************************************************
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TCGNOTNODE
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*****************************************************************************}
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{$ifndef cpu64bit}
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procedure tcgnotnode.second_64bit;
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begin
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secondpass(left);
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),false);
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location_copy(location,left.location);
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{ perform the NOT operation }
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cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,OP_NOT,location.size,left.location.register64,location.register64);
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end;
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{$endif cpu64bit}
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procedure tcgnotnode.second_integer;
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begin
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secondpass(left);
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),false);
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location_copy(location,left.location);
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{ perform the NOT operation }
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NOT,location.size,location.register,location.register);
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end;
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procedure tcgnotnode.pass_generate_code;
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begin
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if is_boolean(resultdef) then
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second_boolean
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{$ifdef SUPPORT_MMX}
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else if (cs_mmx in current_settings.localswitches) and is_mmx_able_array(left.resultdef) then
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second_mmx
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{$endif SUPPORT_MMX}
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{$ifndef cpu64bit}
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else if is_64bit(left.resultdef) then
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second_64bit
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{$endif cpu64bit}
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else
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second_integer;
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end;
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begin
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cmoddivnode:=tcgmoddivnode;
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cunaryminusnode:=tcgunaryminusnode;
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cshlshrnode:=tcgshlshrnode;
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cnotnode:=tcgnotnode;
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end.
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