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0b1a54f924
parameter, when the operation is 32-bit (even when the operation is 32-bit, the shift count is only 16-bit on 16-bit CPUs, so using 32-bits is wasting an extra register and an extra instruction to initialize it) git-svn-id: trunk@35733 -
689 lines
26 KiB
ObjectPascal
689 lines
26 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate generic mathematical nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncgmat;
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{$i fpcdefs.inc}
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interface
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uses
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symtype,
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node,nmat,cpubase,cgbase;
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type
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tcgunaryminusnode = class(tunaryminusnode)
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protected
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{ This routine is called to change the sign of the
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floating point value in the floating point
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register r.
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This routine should be overridden, since
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the generic version is not optimal at all. The
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generic version assumes that floating
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point values are stored in the register
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in IEEE-754 format.
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}
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procedure emit_float_sign_change(r: tregister; _size : tdef);virtual;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;virtual;abstract;
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{$endif SUPPORT_MMX}
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{$ifndef cpu64bitalu}
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procedure second_64bit;virtual;
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{$endif not cpu64bitalu}
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procedure second_integer;virtual;
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procedure second_float;virtual;
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procedure second_float_emulated;virtual;
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public
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procedure pass_generate_code;override;
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end;
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tcgmoddivnode = class(tmoddivnode)
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procedure pass_generate_code;override;
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protected
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{ This routine must do an actual 32-bit division, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the division must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a divide.
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}
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procedure emit_div_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
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{ This routine must do an actual 32-bit modulo, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the modulo must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a modulo.
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}
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procedure emit_mod_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
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{$ifndef cpu64bitalu}
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{ This routine must do an actual 64-bit division, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the division must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a divide.
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Currently, this routine should only be implemented on
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64-bit systems, otherwise a helper is called in 1st pass.
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}
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procedure emit64_div_reg_reg(signed: boolean;denum,num : tregister64);virtual;
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{$endif not cpu64bitalu}
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end;
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tcgshlshrnode = class(tshlshrnode)
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{$ifndef cpu64bitalu}
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procedure second_64bit;virtual;
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{$endif not cpu64bitalu}
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procedure second_integer;virtual;
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procedure pass_generate_code;override;
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end;
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tcgnotnode = class(tnotnode)
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protected
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function handle_locjump: boolean;
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procedure second_boolean;virtual;abstract;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;virtual;abstract;
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{$endif SUPPORT_MMX}
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{$ifndef cpu64bitalu}
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procedure second_64bit;virtual;
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{$endif not cpu64bitalu}
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procedure second_integer;virtual;
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public
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procedure pass_generate_code;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symtable,symconst,symdef,aasmbase,aasmtai,aasmdata,aasmcpu,defutil,
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parabase,
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pass_2,
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ncon,
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tgobj,ncgutil,cgobj,cgutils,paramgr,hlcgobj,procinfo
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{$ifndef cpu64bitalu}
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,cg64f32
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{$endif not cpu64bitalu}
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;
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{*****************************************************************************
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TCGUNARYMINUSNODE
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*****************************************************************************}
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procedure tcgunaryminusnode.emit_float_sign_change(r: tregister; _size : tdef);
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var
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href,
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href2 : treference;
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begin
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{ get a temporary memory reference to store the floating
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point value
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}
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tg.gethltemp(current_asmdata.CurrAsmList,_size,_size.size,tt_normal,href);
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{ store the floating point value in the temporary memory area }
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case getregtype(r) of
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R_FPUREGISTER:
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hlcg.a_loadfpu_reg_ref(current_asmdata.CurrAsmList,_size,_size,r,href);
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R_MMREGISTER:
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hlcg.a_loadmm_reg_ref(current_asmdata.CurrAsmList,_size,_size,r,href,mms_movescalar);
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else
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internalerror(2015091005);
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end;
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{ only single and double ieee are supported, for little endian
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the signed bit is in the second dword }
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href2:=href;
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if _size.typ<>floatdef then
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internalerror(2014012211);
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case tfloatdef(_size).floattype of
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s64real,
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s64comp,
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s64currency:
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if target_info.endian = endian_little then
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inc(href2.offset,4);
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s32real :
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;
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else
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internalerror(200406021);
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end;
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{ flip sign-bit (bit 31/63) of single/double }
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hlcg.a_op_const_ref(current_asmdata.CurrAsmList,OP_XOR,u32inttype,
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{$ifdef cpu64bitalu}
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aint($80000000),
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{$else cpu64bitalu}
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longint($80000000),
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{$endif cpu64bitalu}
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href2);
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case getregtype(r) of
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R_FPUREGISTER:
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hlcg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,_size,_size,href,r);
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R_MMREGISTER:
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hlcg.a_loadmm_ref_reg(current_asmdata.CurrAsmList,_size,_size,href,r,mms_movescalar);
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else
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internalerror(2015091006);
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end;
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tg.ungetiftemp(current_asmdata.CurrAsmList,href);
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end;
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{$ifndef cpu64bitalu}
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procedure tcgunaryminusnode.second_64bit;
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var
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tr: tregister;
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hl: tasmlabel;
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begin
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secondpass(left);
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location_reset(location,LOC_REGISTER,left.location.size);
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location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg64.a_op64_loc_reg(current_asmdata.CurrAsmList,OP_NEG,OS_S64,
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left.location,joinreg64(location.register64.reglo,location.register64.reghi));
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{ there's only overflow in case left was low(int64) -> -left = left }
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if (cs_check_overflow in current_settings.localswitches) then
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begin
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tr:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,
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longint($80000000),location.register64.reghi,tr);
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,
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location.register64.reglo,tr);
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current_asmdata.getjumplabel(hl);
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_32,OC_NE,0,tr,hl);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
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cg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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end;
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{$endif not cpu64bitalu}
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procedure tcgunaryminusnode.second_float_emulated;
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begin
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secondpass(left);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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location:=left.location;
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case location.size of
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OS_32:
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.register);
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OS_64:
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.registerhi);
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else
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internalerror(2014033101);
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end;
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end;
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procedure tcgunaryminusnode.second_float;
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begin
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secondpass(left);
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE :
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begin
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location.register:=hlcg.getregisterfordef(current_asmdata.CurrAsmList,resultdef);
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case getregtype(location.register) of
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R_FPUREGISTER:
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hlcg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
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left.resultdef,resultdef,
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left.location.reference,location.register);
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R_MMREGISTER:
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hlcg.a_loadmm_ref_reg(current_asmdata.CurrAsmList,
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left.resultdef,resultdef,
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left.location.reference,location.register,mms_movescalar);
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else
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internalerror(2015091004);
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end;
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emit_float_sign_change(location.register,left.resultdef);
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end;
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LOC_FPUREGISTER,
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LOC_CFPUREGISTER:
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begin
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location.register:=hlcg.getfpuregister(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_loadfpu_reg_reg(current_asmdata.CurrAsmList,left.resultdef,resultdef,left.location.register,location.register);
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emit_float_sign_change(location.register,left.resultdef);
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end;
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LOC_MMREGISTER,
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LOC_CMMREGISTER:
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begin
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location.register:=hlcg.getmmregister(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,left.resultdef,resultdef,left.location.register,location.register,mms_movescalar);
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emit_float_sign_change(location.register,left.resultdef);
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end
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else
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internalerror(200306021);
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end;
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end;
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procedure tcgunaryminusnode.second_integer;
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var
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hl: tasmlabel;
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opsize: tdef;
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begin
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secondpass(left);
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{$ifdef cpunodefaultint}
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opsize:=left.resultdef;
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{$else cpunodefaultint}
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{ in case of a 32 bit system that can natively execute 64 bit operations }
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if (left.resultdef.size<=sinttype.size) then
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opsize:=sinttype
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else
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opsize:={$ifdef cpu16bitalu}s32inttype{$else}s64inttype{$endif};
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{$endif cpunodefaultint}
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if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,opsize,false);
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location_reset(location,LOC_REGISTER,def_cgsize(opsize));
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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hlcg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,opsize,left.location.register,location.register);
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if (cs_check_overflow in current_settings.localswitches) then
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begin
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current_asmdata.getjumplabel(hl);
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hlcg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,opsize,OC_NE,torddef(opsize).low.svalue,location.register,hl);
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hlcg.g_call_system_proc(current_asmdata.CurrAsmList,'fpc_overflow',[],nil);
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hlcg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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end;
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procedure tcgunaryminusnode.pass_generate_code;
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begin
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{$ifndef cpu64bitalu}
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if is_64bit(left.resultdef) then
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second_64bit
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else
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{$endif not cpu64bitalu}
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{$ifdef SUPPORT_MMX}
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if (cs_mmx in current_settings.localswitches) and is_mmx_able_array(left.resultdef) then
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second_mmx
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else
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{$endif SUPPORT_MMX}
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if (left.resultdef.typ=floatdef) then
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begin
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if (cs_fp_emulation in current_settings.moduleswitches) then
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second_float_emulated
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else
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second_float;
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end
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else
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second_integer;
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end;
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{*****************************************************************************
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TCGMODDIVNODE
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*****************************************************************************}
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{$ifndef cpu64bitalu}
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procedure tcgmoddivnode.emit64_div_reg_reg(signed: boolean; denum,num:tregister64);
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begin
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{ handled in pass_1 already, unless pass_1 is
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overridden
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}
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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end;
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{$endif not cpu64bitalu}
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procedure tcgmoddivnode.pass_generate_code;
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var
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hreg1 : tregister;
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hdenom : tregister;
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power : longint;
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hl : tasmlabel;
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paraloc1 : tcgpara;
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opsize : tcgsize;
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opdef : tdef;
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pd: tprocdef;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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location_copy(location,left.location);
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{$ifndef cpu64bitalu}
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if is_64bit(resultdef) then
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begin
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if is_signed(left.resultdef) then
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opdef:=s64inttype
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else
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opdef:=u64inttype;
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{ this code valid for 64-bit cpu's only ,
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otherwise helpers are called in pass_1
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}
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hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,opdef,false);
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location_copy(location,left.location);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,opdef,false);
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emit64_div_reg_reg(is_signed(left.resultdef),
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joinreg64(right.location.register64.reglo,right.location.register64.reghi),
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joinreg64(location.register64.reglo,location.register64.reghi));
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end
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else
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{$endif not cpu64bitalu}
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begin
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if is_signed(left.resultdef) then
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begin
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opsize:=OS_SINT;
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opdef:=ossinttype;
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end
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else
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begin
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opsize:=OS_INT;
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opdef:=osuinttype;
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end;
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{ put numerator in register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,opdef,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and
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(right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value.svalue,power) then
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Begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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If is_signed(left.resultdef) Then
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Begin
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current_asmdata.getjumplabel(hl);
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_INT,OC_GT,0,hreg1,hl);
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if power=1 then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_ADD,OS_INT,1,hreg1)
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else
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_ADD,OS_INT,Tordconstnode(right).value.svalue-1,hreg1);
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cg.a_label(current_asmdata.CurrAsmList,hl);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,power,hreg1);
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End
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Else { not signed }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,power,hreg1);
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End
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else
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begin
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{ bring denominator to hdenom }
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{ hdenom is always free, it's }
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{ only used for temporary }
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{ purposes }
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hdenom := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,hdenom);
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{ verify if the divisor is zero, if so return an error immediately,
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except if we have a const node, where we don't need this, because
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then zero check was done earlier.
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}
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if (right.nodetype <> ordconstn) then
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begin
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current_asmdata.getjumplabel(hl);
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_INT,OC_NE,0,hdenom,hl);
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paraloc1.init;
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pd:=search_system_proc('fpc_handleerror');
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paramanager.getintparaloc(current_asmdata.CurrAsmList,pd,1,paraloc1);
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cg.a_load_const_cgpara(current_asmdata.CurrAsmList,OS_S32,aint(200),paraloc1);
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paramanager.freecgpara(current_asmdata.CurrAsmList,paraloc1);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_HANDLEERROR',false);
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paraloc1.done;
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cg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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if nodetype = modn then
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emit_mod_reg_reg(is_signed(left.resultdef),hdenom,hreg1)
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else
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emit_div_reg_reg(is_signed(left.resultdef),hdenom,hreg1);
|
|
end;
|
|
location_reset(location,LOC_REGISTER,opsize);
|
|
location.register:=hreg1;
|
|
end;
|
|
cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
TCGSHLRSHRNODE
|
|
*****************************************************************************}
|
|
|
|
|
|
{$ifndef cpu64bitalu}
|
|
procedure tcgshlshrnode.second_64bit;
|
|
begin
|
|
{ already hanled in 1st pass }
|
|
internalerror(2002081501);
|
|
end;
|
|
{$endif not cpu64bitalu}
|
|
|
|
|
|
procedure tcgshlshrnode.second_integer;
|
|
var
|
|
op : topcg;
|
|
opdef,shiftcountdef: tdef;
|
|
hcountreg : tregister;
|
|
opsize : tcgsize;
|
|
shiftval : longint;
|
|
begin
|
|
{ determine operator }
|
|
case nodetype of
|
|
shln: op:=OP_SHL;
|
|
shrn: op:=OP_SHR;
|
|
else
|
|
internalerror(2013120102);
|
|
end;
|
|
{$ifdef cpunodefaultint}
|
|
opsize:=left.location.size;
|
|
opdef:=left.resultdef;
|
|
shiftcountdef:=opdef;
|
|
{$else cpunodefaultint}
|
|
if left.resultdef.size<=4 then
|
|
begin
|
|
if is_signed(left.resultdef) then
|
|
begin
|
|
if (sizeof(aint)<4) and
|
|
(left.resultdef.size<=sizeof(aint)) then
|
|
begin
|
|
opsize:=OS_SINT;
|
|
opdef:=sinttype;
|
|
end
|
|
else
|
|
begin
|
|
opdef:=s32inttype;
|
|
opsize:=OS_S32;
|
|
end;
|
|
{$ifdef cpu16bitalu}
|
|
shiftcountdef:=s16inttype;
|
|
{$else cpu16bitalu}
|
|
shiftcountdef:=opdef;
|
|
{$endif cpu16bitalu}
|
|
end
|
|
else
|
|
begin
|
|
if (sizeof(aint)<4) and
|
|
(left.resultdef.size<=sizeof(aint)) then
|
|
begin
|
|
opsize:=OS_INT;
|
|
opdef:=uinttype;
|
|
end
|
|
else
|
|
begin
|
|
opdef:=u32inttype;
|
|
opsize:=OS_32;
|
|
end;
|
|
{$ifdef cpu16bitalu}
|
|
shiftcountdef:=u16inttype;
|
|
{$else cpu16bitalu}
|
|
shiftcountdef:=opdef;
|
|
{$endif cpu16bitalu}
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
if is_signed(left.resultdef) then
|
|
begin
|
|
opdef:=s64inttype;
|
|
opsize:=OS_S64;
|
|
end
|
|
else
|
|
begin
|
|
opdef:=u64inttype;
|
|
opsize:=OS_64;
|
|
end;
|
|
shiftcountdef:=opdef;
|
|
end;
|
|
{$endif cpunodefaultint}
|
|
|
|
if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
|
|
{ location_force_reg can be also used to change the size of a register }
|
|
(left.location.size<>opsize) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,opdef,true);
|
|
location_reset(location,LOC_REGISTER,opsize);
|
|
location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
|
|
|
|
{ shifting by a constant directly coded: }
|
|
if (right.nodetype=ordconstn) then
|
|
begin
|
|
{ shl/shr must "wrap around", so use ... and 31 }
|
|
{ In TP, "byte/word shl 16 = 0", so no "and 15" in case of
|
|
a 16 bit ALU }
|
|
if tcgsize2size[opsize]<=4 then
|
|
shiftval:=tordconstnode(right).value.uvalue and 31
|
|
else
|
|
shiftval:=tordconstnode(right).value.uvalue and 63;
|
|
hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,opdef,
|
|
shiftval,left.location.register,location.register);
|
|
end
|
|
else
|
|
begin
|
|
{ load right operators in a register - this
|
|
is done since most target cpu which will use this
|
|
node do not support a shift count in a mem. location (cec)
|
|
}
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,shiftcountdef,true);
|
|
hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,opdef,right.location.register,left.location.register,location.register);
|
|
end;
|
|
{ shl/shr nodes return the same type as left, which can be different
|
|
from opdef }
|
|
if opdef<>resultdef then
|
|
begin
|
|
hcountreg:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
|
|
hlcg.a_load_reg_reg(current_asmdata.CurrAsmList,opdef,resultdef,location.register,hcountreg);
|
|
location.register:=hcountreg;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgshlshrnode.pass_generate_code;
|
|
begin
|
|
secondpass(left);
|
|
secondpass(right);
|
|
{$ifndef cpu64bitalu}
|
|
if is_64bit(left.resultdef) then
|
|
second_64bit
|
|
else
|
|
{$endif not cpu64bitalu}
|
|
second_integer;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
TCGNOTNODE
|
|
*****************************************************************************}
|
|
|
|
{$ifndef cpu64bitalu}
|
|
procedure tcgnotnode.second_64bit;
|
|
begin
|
|
secondpass(left);
|
|
if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
|
|
location_reset(location,LOC_REGISTER,left.location.size);
|
|
location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
{ perform the NOT operation }
|
|
cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,OP_NOT,location.size,left.location.register64,location.register64);
|
|
end;
|
|
{$endif not cpu64bitalu}
|
|
|
|
|
|
procedure tcgnotnode.second_integer;
|
|
begin
|
|
secondpass(left);
|
|
if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
|
|
location_reset(location,LOC_REGISTER,left.location.size);
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
|
|
{ perform the NOT operation }
|
|
hlcg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NOT,left.resultdef,left.location.register,location.register);
|
|
end;
|
|
|
|
|
|
function tcgnotnode.handle_locjump: boolean;
|
|
begin
|
|
result:=(left.expectloc=LOC_JUMP);
|
|
if result then
|
|
begin
|
|
secondpass(left);
|
|
|
|
if is_constboolnode(left) then
|
|
internalerror(2014010101);
|
|
if left.location.loc<>LOC_JUMP then
|
|
internalerror(2012081306);
|
|
|
|
{ switch true and false labels to invert result }
|
|
location_reset_jump(location,left.location.falselabel,left.location.truelabel);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgnotnode.pass_generate_code;
|
|
begin
|
|
if is_boolean(resultdef) then
|
|
second_boolean
|
|
{$ifdef SUPPORT_MMX}
|
|
else if (cs_mmx in current_settings.localswitches) and is_mmx_able_array(left.resultdef) then
|
|
second_mmx
|
|
{$endif SUPPORT_MMX}
|
|
{$ifndef cpu64bitalu}
|
|
else if is_64bit(left.resultdef) then
|
|
second_64bit
|
|
{$endif not cpu64bitalu}
|
|
else
|
|
second_integer;
|
|
end;
|
|
|
|
begin
|
|
cmoddivnode:=tcgmoddivnode;
|
|
cunaryminusnode:=tcgunaryminusnode;
|
|
cshlshrnode:=tcgshlshrnode;
|
|
cnotnode:=tcgnotnode;
|
|
end.
|