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https://gitlab.com/freepascal.org/fpc/source.git
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65c3ba277c
ungetcpuregister * renamed (get|unget)explicitregister(s) to ..cpuregister * removed location-release/reference_release
1267 lines
45 KiB
ObjectPascal
1267 lines
45 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the code generator for the SPARC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,parabase,
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cgbase,cgobj,cg64f32,
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aasmbase,aasmtai,aasmcpu,
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cpubase,cpuinfo,
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node,symconst,SymType,
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rgcpu;
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type
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TCgSparc=class(tcg)
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protected
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function IsSimpleRef(const ref:treference):boolean;
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public
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procedure init_register_allocators;override;
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procedure done_register_allocators;override;
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function getfpuregister(list:Taasmoutput;size:Tcgsize):Tregister;override;
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{ sparc special, needed by cg64 }
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procedure make_simple_ref(list:taasmoutput;var ref: treference);
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procedure handle_load_store(list:taasmoutput;isstore:boolean;op: tasmop;reg:tregister;ref: treference);
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procedure handle_reg_const_reg(list:taasmoutput;op:Tasmop;src:tregister;a:aint;dst:tregister);
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{ parameter }
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procedure a_param_const(list:TAasmOutput;size:tcgsize;a:aint;const paraloc:TCGPara);override;
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procedure a_param_ref(list:TAasmOutput;sz:tcgsize;const r:TReference;const paraloc:TCGPara);override;
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procedure a_paramaddr_ref(list:TAasmOutput;const r:TReference;const paraloc:TCGPara);override;
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procedure a_paramfpu_reg(list : taasmoutput;size : tcgsize;const r : tregister;const paraloc : TCGPara);override;
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procedure a_paramfpu_ref(list : taasmoutput;size : tcgsize;const ref : treference;const paraloc : TCGPara);override;
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// procedure a_loadany_param_ref(list : taasmoutput;const paraloc : TCGPara;const ref:treference;shuffle : pmmshuffle);override;
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procedure a_loadany_param_reg(list : taasmoutput;const paraloc : TCGPara;const reg:tregister;shuffle : pmmshuffle);override;
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procedure a_call_name(list:TAasmOutput;const s:string);override;
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procedure a_call_reg(list:TAasmOutput;Reg:TRegister);override;
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{ General purpose instructions }
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procedure a_op_const_reg(list:TAasmOutput;Op:TOpCG;size:tcgsize;a:aint;reg:TRegister);override;
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procedure a_op_reg_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;src, dst:TRegister);override;
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procedure a_op_const_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;a:aint;src, dst:tregister);override;
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procedure a_op_reg_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);override;
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{ move instructions }
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procedure a_load_const_reg(list:TAasmOutput;size:tcgsize;a:aint;reg:tregister);override;
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procedure a_load_const_ref(list:TAasmOutput;size:tcgsize;a:aint;const ref:TReference);override;
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procedure a_load_reg_ref(list:TAasmOutput;FromSize,ToSize:TCgSize;reg:TRegister;const ref:TReference);override;
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procedure a_load_ref_reg(list:TAasmOutput;FromSize,ToSize:TCgSize;const ref:TReference;reg:tregister);override;
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procedure a_load_reg_reg(list:TAasmOutput;FromSize,ToSize:TCgSize;reg1,reg2:tregister);override;
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procedure a_loadaddr_ref_reg(list:TAasmOutput;const ref:TReference;r:tregister);override;
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{ fpu move instructions }
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procedure a_loadfpu_reg_reg(list:TAasmOutput;size:tcgsize;reg1, reg2:tregister);override;
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procedure a_loadfpu_ref_reg(list:TAasmOutput;size:tcgsize;const ref:TReference;reg:tregister);override;
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procedure a_loadfpu_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;const ref:TReference);override;
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{ comparison operations }
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procedure a_cmp_const_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aint;reg:tregister;l:tasmlabel);override;
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procedure a_cmp_reg_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);override;
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procedure a_jmp_always(List:TAasmOutput;l:TAsmLabel);override;
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procedure a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:tasmlabel);{ override;}
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procedure a_jmp_flags(list:TAasmOutput;const f:TResFlags;l:tasmlabel);override;
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procedure g_flags2reg(list:TAasmOutput;Size:TCgSize;const f:tresflags;reg:TRegister);override;
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procedure g_overflowCheck(List:TAasmOutput;const Loc:TLocation;def:TDef);override;
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procedure g_proc_entry(list : taasmoutput;localsize : longint;nostackframe:boolean);override;
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procedure g_proc_exit(list : taasmoutput;parasize:longint;nostackframe:boolean);override;
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procedure g_restore_all_registers(list:TAasmOutput;const funcretparaloc:TCGPara);override;
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procedure g_restore_standard_registers(list:taasmoutput);override;
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procedure g_save_all_registers(list : taasmoutput);override;
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procedure g_save_standard_registers(list : taasmoutput);override;
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procedure g_concatcopy(list : taasmoutput;const source,dest : treference;len : aint;loadref : boolean);override;
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end;
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TCg64Sparc=class(tcg64f32)
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private
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procedure get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp);
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public
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procedure a_load64_reg_ref(list : taasmoutput;reg : tregister64;const ref : treference);override;
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procedure a_load64_ref_reg(list : taasmoutput;const ref : treference;reg : tregister64);override;
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procedure a_param64_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);override;
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procedure a_op64_reg_reg(list:TAasmOutput;op:TOpCG;regsrc,regdst:TRegister64);override;
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procedure a_op64_const_reg(list:TAasmOutput;op:TOpCG;value:int64;regdst:TRegister64);override;
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procedure a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;value : int64;regsrc,regdst : tregister64);override;
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procedure a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);override;
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end;
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const
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TOpCG2AsmOp : array[topcg] of TAsmOp=(
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A_NONE,A_ADD,A_AND,A_UDIV,A_SDIV,A_UMUL,A_SMUL,A_NEG,A_NOT,A_OR,A_SRA,A_SLL,A_SRL,A_SUB,A_XOR
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);
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TOpCmp2AsmCond : array[topcmp] of TAsmCond=(C_NONE,
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C_E,C_G,C_L,C_GE,C_LE,C_NE,C_BE,C_B,C_AE,C_A
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);
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implementation
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uses
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globals,verbose,systems,cutils,
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symdef,paramgr,
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tgobj,cpupi,cgutils;
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{****************************************************************************
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This is private property, keep out! :)
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****************************************************************************}
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function TCgSparc.IsSimpleRef(const ref:treference):boolean;
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begin
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if (ref.base=NR_NO) and (ref.index<>NR_NO) then
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InternalError(2002100804);
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result :=not(assigned(ref.symbol))and
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(((ref.index = NR_NO) and
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(ref.offset >= simm13lo) and
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(ref.offset <= simm13hi)) or
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((ref.index <> NR_NO) and
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(ref.offset = 0)));
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end;
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procedure tcgsparc.make_simple_ref(list:taasmoutput;var ref: treference);
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var
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tmpreg : tregister;
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tmpref : treference;
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begin
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tmpreg:=NR_NO;
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{ Be sure to have a base register }
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if (ref.base=NR_NO) then
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begin
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ref.base:=ref.index;
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ref.index:=NR_NO;
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end;
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{ When need to use SETHI, do it first }
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if assigned(ref.symbol) or
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(ref.offset<simm13lo) or
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(ref.offset>simm13hi) then
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begin
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tmpreg:=GetIntRegister(list,OS_INT);
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reference_reset(tmpref);
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tmpref.symbol:=ref.symbol;
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tmpref.offset:=ref.offset;
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tmpref.refaddr:=addr_hi;
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list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,tmpreg));
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{ Load the low part is left }
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{$warning TODO Maybe not needed to load symbol}
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tmpref.refaddr:=addr_lo;
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list.concat(taicpu.op_reg_ref_reg(A_OR,tmpreg,tmpref,tmpreg));
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{ The offset and symbol are loaded, reset in reference }
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ref.offset:=0;
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ref.symbol:=nil;
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{ Only an index register or offset is allowed }
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if tmpreg<>NR_NO then
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begin
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if (ref.index<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.index,tmpreg));
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ref.index:=tmpreg;
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end
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else
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begin
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if ref.base<>NR_NO then
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ref.index:=tmpreg
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else
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ref.base:=tmpreg;
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end;
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end;
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end;
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if (ref.base<>NR_NO) then
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begin
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if (ref.index<>NR_NO) and
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((ref.offset<>0) or assigned(ref.symbol)) then
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begin
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if tmpreg=NR_NO then
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tmpreg:=GetIntRegister(list,OS_INT);
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list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,tmpreg));
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ref.base:=tmpreg;
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ref.index:=NR_NO;
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end;
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end;
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end;
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procedure tcgsparc.handle_load_store(list:taasmoutput;isstore:boolean;op: tasmop;reg:tregister;ref: treference);
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begin
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make_simple_ref(list,ref);
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if isstore then
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list.concat(taicpu.op_reg_ref(op,reg,ref))
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else
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list.concat(taicpu.op_ref_reg(op,ref,reg));
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end;
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procedure tcgsparc.handle_reg_const_reg(list:taasmoutput;op:Tasmop;src:tregister;a:aint;dst:tregister);
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var
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tmpreg : tregister;
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begin
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if (a<simm13lo) or
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(a>simm13hi) then
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begin
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tmpreg:=GetIntRegister(list,OS_INT);
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a_load_const_reg(list,OS_INT,a,tmpreg);
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list.concat(taicpu.op_reg_reg_reg(op,src,tmpreg,dst));
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end
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else
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list.concat(taicpu.op_reg_const_reg(op,src,a,dst));
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end;
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{****************************************************************************
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Assembler code
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****************************************************************************}
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procedure Tcgsparc.init_register_allocators;
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begin
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inherited init_register_allocators;
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_O0,RS_O1,RS_O2,RS_O3,RS_O4,RS_O5,
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RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7],
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first_int_imreg,[]);
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBFS,
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[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,
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RS_F8,RS_F9,RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15,
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RS_F16,RS_F17,RS_F18,RS_F19,RS_F20,RS_F21,RS_F22,RS_F23,
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RS_F24,RS_F25,RS_F26,RS_F27,RS_F28,RS_F29,RS_F30,RS_F31],
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first_fpu_imreg,[]);
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end;
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procedure Tcgsparc.done_register_allocators;
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begin
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rg[R_INTREGISTER].free;
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rg[R_FPUREGISTER].free;
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inherited done_register_allocators;
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end;
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function tcgsparc.getfpuregister(list:Taasmoutput;size:Tcgsize):Tregister;
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begin
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if size=OS_F64 then
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result:=rg[R_FPUREGISTER].getregister(list,R_SUBFD)
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else
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result:=rg[R_FPUREGISTER].getregister(list,R_SUBFS);
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end;
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procedure TCgSparc.a_param_const(list:TAasmOutput;size:tcgsize;a:aint;const paraloc:TCGPara);
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var
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Ref:TReference;
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begin
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paraloc.check_simple_location;
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case paraloc.location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load_const_reg(list,size,a,paraloc.location^.register);
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LOC_REFERENCE:
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begin
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{ Code conventions need the parameters being allocated in %o6+92 }
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with paraloc.location^.Reference do
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begin
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if (Index=NR_SP) and (Offset<Target_info.first_parm_offset) then
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InternalError(2002081104);
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reference_reset_base(ref,index,offset);
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end;
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a_load_const_ref(list,size,a,ref);
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end;
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else
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InternalError(2002122200);
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end;
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end;
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procedure TCgSparc.a_param_ref(list:TAasmOutput;sz:TCgSize;const r:TReference;const paraloc:TCGPara);
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var
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ref: treference;
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tmpreg:TRegister;
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begin
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paraloc.check_simple_location;
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with paraloc.location^ do
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begin
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case loc of
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LOC_REGISTER,LOC_CREGISTER :
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a_load_ref_reg(list,sz,sz,r,Register);
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LOC_REFERENCE:
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begin
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{ Code conventions need the parameters being allocated in %o6+92 }
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with Reference do
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begin
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if (Index=NR_SP) and (Offset<Target_info.first_parm_offset) then
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InternalError(2002081104);
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reference_reset_base(ref,index,offset);
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end;
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tmpreg:=GetIntRegister(list,OS_INT);
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a_load_ref_reg(list,sz,sz,r,tmpreg);
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a_load_reg_ref(list,sz,sz,tmpreg,ref);
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end;
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else
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internalerror(2002081103);
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end;
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end;
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end;
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procedure TCgSparc.a_paramaddr_ref(list:TAasmOutput;const r:TReference;const paraloc:TCGPara);
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var
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Ref:TReference;
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TmpReg:TRegister;
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begin
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paraloc.check_simple_location;
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with paraloc.location^ do
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begin
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case loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_loadaddr_ref_reg(list,r,register);
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LOC_REFERENCE:
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begin
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reference_reset(ref);
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ref.base := reference.index;
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ref.offset := reference.offset;
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tmpreg:=GetAddressRegister(list);
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a_loadaddr_ref_reg(list,r,tmpreg);
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a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
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end;
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else
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internalerror(2002080701);
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end;
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end;
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end;
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procedure tcgsparc.a_paramfpu_ref(list : taasmoutput;size : tcgsize;const ref : treference;const paraloc : TCGPara);
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var
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href,href2 : treference;
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hloc : pcgparalocation;
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begin
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href:=ref;
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hloc:=paraloc.location;
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while assigned(hloc) do
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begin
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case hloc^.loc of
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LOC_REGISTER :
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a_load_ref_reg(list,hloc^.size,hloc^.size,href,hloc^.register);
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LOC_REFERENCE :
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begin
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reference_reset_base(href2,hloc^.reference.index,hloc^.reference.offset);
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a_load_ref_ref(list,hloc^.size,hloc^.size,href,href2);
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end;
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else
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internalerror(200408241);
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end;
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inc(href.offset,tcgsize2size[hloc^.size]);
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hloc:=hloc^.next;
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end;
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end;
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procedure tcgsparc.a_paramfpu_reg(list : taasmoutput;size : tcgsize;const r : tregister;const paraloc : TCGPara);
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var
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href : treference;
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begin
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tg.GetTemp(list,TCGSize2Size[size],tt_normal,href);
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a_loadfpu_reg_ref(list,size,r,href);
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a_paramfpu_ref(list,size,href,paraloc);
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tg.Ungettemp(list,href);
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end;
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(*
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procedure tcgsparc.a_paramfpu_ref(list : taasmoutput;size : tcgsize;const ref : treference;const paraloc : TCGPara);
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var
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tempparaloc : TCGPara;
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begin
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{ floats are pushed in the int registers }
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tempparaloc:=paraloc;
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case paraloc.size of
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OS_F32,OS_32 :
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begin
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tempparaloc.size:=OS_32;
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a_param_ref(list,OS_32,ref,tempparaloc);
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end;
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OS_F64,OS_64 :
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begin
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tempparaloc.size:=OS_64;
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cg64.a_param64_ref(list,ref,tempparaloc);
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end;
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else
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internalerror(200307021);
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end;
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end;
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procedure tcgsparc.a_loadany_param_ref(list : taasmoutput;const paraloc : TCGPara;const ref:treference;shuffle : pmmshuffle);
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var
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href,
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tempref : treference;
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tempparaloc : TCGPara;
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begin
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{ Load floats like ints }
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tempparaloc:=paraloc;
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case paraloc.size of
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OS_F32 :
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tempparaloc.size:=OS_32;
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OS_F64 :
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tempparaloc.size:=OS_64;
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end;
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{ Word 0 is in register, word 1 is in reference }
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if (tempparaloc.loc=LOC_REFERENCE) and (tempparaloc.low_in_reg) then
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begin
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tempref:=ref;
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cg.a_load_reg_ref(list,OS_INT,OS_INT,tempparaloc.register,tempref);
|
|
inc(tempref.offset,4);
|
|
reference_reset_base(href,tempparaloc.reference.index,tempparaloc.reference.offset);
|
|
cg.a_load_ref_ref(list,OS_INT,OS_INT,href,tempref);
|
|
end
|
|
else
|
|
inherited a_loadany_param_ref(list,tempparaloc,ref,shuffle);
|
|
end;
|
|
*)
|
|
|
|
|
|
procedure tcgsparc.a_loadany_param_reg(list : taasmoutput;const paraloc : TCGPara;const reg:tregister;shuffle : pmmshuffle);
|
|
var
|
|
href : treference;
|
|
begin
|
|
paraloc.check_simple_location;
|
|
{ Float load use a temp reference }
|
|
if getregtype(reg)=R_FPUREGISTER then
|
|
begin
|
|
tg.GetTemp(list,TCGSize2Size[paraloc.size],tt_normal,href);
|
|
a_loadany_param_ref(list,paraloc,href,shuffle);
|
|
a_loadfpu_ref_reg(list,paraloc.size,href,reg);
|
|
tg.Ungettemp(list,href);
|
|
end
|
|
else
|
|
inherited a_loadany_param_reg(list,paraloc,reg,shuffle);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_call_name(list:TAasmOutput;const s:string);
|
|
begin
|
|
list.concat(taicpu.op_sym(A_CALL,objectlibrary.newasmsymbol(s,AB_EXTERNAL,AT_FUNCTION)));
|
|
{ Delay slot }
|
|
list.concat(taicpu.op_none(A_NOP));
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_call_reg(list:TAasmOutput;Reg:TRegister);
|
|
begin
|
|
list.concat(taicpu.op_reg(A_CALL,reg));
|
|
{ Delay slot }
|
|
list.concat(taicpu.op_none(A_NOP));
|
|
end;
|
|
|
|
|
|
{********************** load instructions ********************}
|
|
|
|
procedure TCgSparc.a_load_const_reg(list : TAasmOutput;size : TCGSize;a : aint;reg : TRegister);
|
|
begin
|
|
{ we don't use the set instruction here because it could be evalutated to two
|
|
instructions which would cause problems with the delay slot (FK) }
|
|
if (a=0) then
|
|
list.concat(taicpu.op_reg(A_CLR,reg))
|
|
{ sethi allows to set the upper 22 bit, so we'll take full advantage of it }
|
|
else if (a and aint($1fff))=0 then
|
|
list.concat(taicpu.op_const_reg(A_SETHI,a shr 10,reg))
|
|
else if (a>=simm13lo) and (a<=simm13hi) then
|
|
list.concat(taicpu.op_const_reg(A_MOV,a,reg))
|
|
else
|
|
begin
|
|
list.concat(taicpu.op_const_reg(A_SETHI,a shr 10,reg));
|
|
list.concat(taicpu.op_reg_const_reg(A_OR,reg,a and aint($3ff),reg));
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_load_const_ref(list : TAasmOutput;size : tcgsize;a : aint;const ref : TReference);
|
|
begin
|
|
if a=0 then
|
|
a_load_reg_ref(list,size,size,NR_G0,ref)
|
|
else
|
|
inherited a_load_const_ref(list,size,a,ref);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_load_reg_ref(list:TAasmOutput;FromSize,ToSize:TCGSize;reg:tregister;const Ref:TReference);
|
|
var
|
|
op : tasmop;
|
|
begin
|
|
if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
|
|
fromsize := tosize;
|
|
case fromsize of
|
|
{ signed integer registers }
|
|
OS_8,
|
|
OS_S8:
|
|
Op:=A_STB;
|
|
OS_16,
|
|
OS_S16:
|
|
Op:=A_STH;
|
|
OS_32,
|
|
OS_S32:
|
|
Op:=A_ST;
|
|
else
|
|
InternalError(2002122100);
|
|
end;
|
|
handle_load_store(list,true,op,reg,ref);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_load_ref_reg(list:TAasmOutput;FromSize,ToSize:TCgSize;const ref:TReference;reg:tregister);
|
|
var
|
|
op : tasmop;
|
|
begin
|
|
if (TCGSize2Size[fromsize] >= TCGSize2Size[tosize]) then
|
|
fromsize := tosize;
|
|
case fromsize of
|
|
OS_S8:
|
|
Op:=A_LDSB;{Load Signed Byte}
|
|
OS_8:
|
|
Op:=A_LDUB;{Load Unsigned Byte}
|
|
OS_S16:
|
|
Op:=A_LDSH;{Load Signed Halfword}
|
|
OS_16:
|
|
Op:=A_LDUH;{Load Unsigned Halfword}
|
|
OS_S32,
|
|
OS_32:
|
|
Op:=A_LD;{Load Word}
|
|
OS_S64,
|
|
OS_64:
|
|
Op:=A_LDD;{Load a Long Word}
|
|
else
|
|
InternalError(2002122101);
|
|
end;
|
|
handle_load_store(list,false,op,reg,ref);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_load_reg_reg(list:TAasmOutput;fromsize,tosize:tcgsize;reg1,reg2:tregister);
|
|
var
|
|
instr : taicpu;
|
|
begin
|
|
if (tcgsize2size[tosize]<tcgsize2size[fromsize]) or
|
|
(
|
|
(tcgsize2size[tosize] = tcgsize2size[fromsize]) and
|
|
(tosize <> fromsize) and
|
|
not(fromsize in [OS_32,OS_S32])
|
|
) then
|
|
begin
|
|
case tosize of
|
|
OS_8 :
|
|
a_op_const_reg_reg(list,OP_AND,tosize,$ff,reg1,reg2);
|
|
OS_16 :
|
|
a_op_const_reg_reg(list,OP_AND,tosize,$ffff,reg1,reg2);
|
|
OS_32,
|
|
OS_S32 :
|
|
begin
|
|
instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
|
|
list.Concat(instr);
|
|
{ Notify the register allocator that we have written a move instruction so
|
|
it can try to eliminate it. }
|
|
add_move_instruction(instr);
|
|
end;
|
|
OS_S8 :
|
|
begin
|
|
list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,24,reg2));
|
|
list.concat(taicpu.op_reg_const_reg(A_SRA,reg2,24,reg2));
|
|
end;
|
|
OS_S16 :
|
|
begin
|
|
list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,16,reg2));
|
|
list.concat(taicpu.op_reg_const_reg(A_SRA,reg2,16,reg2));
|
|
end;
|
|
else
|
|
internalerror(2002090901);
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
{ same size, only a register mov required }
|
|
instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
|
|
list.Concat(instr);
|
|
{ Notify the register allocator that we have written a move instruction so
|
|
it can try to eliminate it. }
|
|
add_move_instruction(instr);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_loadaddr_ref_reg(list : TAasmOutput;const ref : TReference;r : tregister);
|
|
var
|
|
tmpref : treference;
|
|
hreg : tregister;
|
|
begin
|
|
if (ref.base=NR_NO) and (ref.index<>NR_NO) then
|
|
internalerror(200306171);
|
|
{ At least big offset (need SETHI), maybe base and maybe index }
|
|
if assigned(ref.symbol) or
|
|
(ref.offset<simm13lo) or
|
|
(ref.offset>simm13hi) then
|
|
begin
|
|
hreg:=GetAddressRegister(list);
|
|
reference_reset(tmpref);
|
|
tmpref.symbol := ref.symbol;
|
|
tmpref.offset := ref.offset;
|
|
tmpref.refaddr := addr_hi;
|
|
list.concat(taicpu.op_ref_reg(A_SETHI,tmpref,hreg));
|
|
{ Only the low part is left }
|
|
tmpref.refaddr:=addr_lo;
|
|
list.concat(taicpu.op_reg_ref_reg(A_OR,hreg,tmpref,hreg));
|
|
if ref.base<>NR_NO then
|
|
begin
|
|
if ref.index<>NR_NO then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.base,hreg));
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.index,r));
|
|
end
|
|
else
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.base,r));
|
|
end
|
|
else
|
|
begin
|
|
if hreg<>r then
|
|
a_load_reg_reg(list,OS_ADDR,OS_ADDR,hreg,r);
|
|
end;
|
|
end
|
|
else
|
|
{ At least small offset, maybe base and maybe index }
|
|
if ref.offset<>0 then
|
|
begin
|
|
if ref.base<>NR_NO then
|
|
begin
|
|
if ref.index<>NR_NO then
|
|
begin
|
|
hreg:=GetAddressRegister(list);
|
|
list.concat(taicpu.op_reg_const_reg(A_ADD,ref.base,ref.offset,hreg));
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,ref.index,r));
|
|
end
|
|
else
|
|
list.concat(taicpu.op_reg_const_reg(A_ADD,ref.base,ref.offset,r));
|
|
end
|
|
else
|
|
list.concat(taicpu.op_const_reg(A_MOV,ref.offset,r));
|
|
end
|
|
else
|
|
{ Both base and index }
|
|
if ref.index<>NR_NO then
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,ref.base,ref.index,r))
|
|
else
|
|
{ Only base }
|
|
if ref.base<>NR_NO then
|
|
a_load_reg_reg(list,OS_ADDR,OS_ADDR,ref.base,r)
|
|
else
|
|
{ only offset, can be generated by absolute }
|
|
a_load_const_reg(list,OS_ADDR,ref.offset,r);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_loadfpu_reg_reg(list:TAasmOutput;size:tcgsize;reg1, reg2:tregister);
|
|
const
|
|
FpuMovInstr : Array[OS_F32..OS_F64] of TAsmOp =
|
|
(A_FMOVS,A_FMOVD);
|
|
var
|
|
instr : taicpu;
|
|
begin
|
|
if reg1<>reg2 then
|
|
begin
|
|
instr:=taicpu.op_reg_reg(fpumovinstr[size],reg1,reg2);
|
|
list.Concat(instr);
|
|
{ Notify the register allocator that we have written a move instruction so
|
|
it can try to eliminate it. }
|
|
add_move_instruction(instr);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_loadfpu_ref_reg(list:TAasmOutput;size:tcgsize;const ref:TReference;reg:tregister);
|
|
const
|
|
FpuLoadInstr : Array[OS_F32..OS_F64] of TAsmOp =
|
|
(A_LDF,A_LDDF);
|
|
begin
|
|
{ several functions call this procedure with OS_32 or OS_64 }
|
|
{ so this makes life easier (FK) }
|
|
case size of
|
|
OS_32,OS_F32:
|
|
size:=OS_F32;
|
|
OS_64,OS_F64,OS_C64:
|
|
size:=OS_F64;
|
|
else
|
|
internalerror(200201121);
|
|
end;
|
|
handle_load_store(list,false,fpuloadinstr[size],reg,ref);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_loadfpu_reg_ref(list:TAasmOutput;size:tcgsize;reg:tregister;const ref:TReference);
|
|
const
|
|
FpuLoadInstr : Array[OS_F32..OS_F64] of TAsmOp =
|
|
(A_STF,A_STDF);
|
|
begin
|
|
{ several functions call this procedure with OS_32 or OS_64 }
|
|
{ so this makes life easier (FK) }
|
|
case size of
|
|
OS_32,OS_F32:
|
|
size:=OS_F32;
|
|
OS_64,OS_F64,OS_C64:
|
|
size:=OS_F64;
|
|
else
|
|
internalerror(200201121);
|
|
end;
|
|
handle_load_store(list,true,fpuloadinstr[size],reg,ref);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_op_const_reg(list:TAasmOutput;Op:TOpCG;size:tcgsize;a:aint;reg:TRegister);
|
|
begin
|
|
if Op in [OP_NEG,OP_NOT] then
|
|
internalerror(200306011);
|
|
if (a=0) then
|
|
list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],reg,NR_G0,reg))
|
|
else
|
|
handle_reg_const_reg(list,TOpCG2AsmOp[op],reg,a,reg);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_op_reg_reg(list:TAasmOutput;Op:TOpCG;size:TCGSize;src, dst:TRegister);
|
|
var
|
|
a : aint;
|
|
begin
|
|
Case Op of
|
|
OP_NEG :
|
|
list.concat(taicpu.op_reg_reg(TOpCG2AsmOp[op],src,dst));
|
|
OP_NOT :
|
|
begin
|
|
case size of
|
|
OS_8 :
|
|
a:=aint($ffffff00);
|
|
OS_16 :
|
|
a:=aint($ffff0000);
|
|
else
|
|
a:=0;
|
|
end;
|
|
handle_reg_const_reg(list,A_XNOR,src,a,dst);
|
|
end;
|
|
else
|
|
list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src,dst));
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_op_const_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;a:aint;src, dst:tregister);
|
|
var
|
|
power : longInt;
|
|
begin
|
|
case op of
|
|
OP_IMUL :
|
|
begin
|
|
if not(cs_check_overflow in aktlocalswitches) and
|
|
ispowerof2(a,power) then
|
|
begin
|
|
{ can be done with a shift }
|
|
inherited a_op_const_reg_reg(list,op,size,a,src,dst);
|
|
exit;
|
|
end;
|
|
end;
|
|
OP_SUB,
|
|
OP_ADD :
|
|
begin
|
|
if (a=0) then
|
|
begin
|
|
a_load_reg_reg(list,size,size,src,dst);
|
|
exit;
|
|
end;
|
|
end;
|
|
end;
|
|
handle_reg_const_reg(list,TOpCG2AsmOp[op],src,a,dst);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_op_reg_reg_reg(list:TAasmOutput;op:TOpCg;size:tcgsize;src1, src2, dst:tregister);
|
|
begin
|
|
list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],src2,src1,dst));
|
|
end;
|
|
|
|
|
|
{*************** compare instructructions ****************}
|
|
|
|
procedure TCgSparc.a_cmp_const_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;a:aint;reg:tregister;l:tasmlabel);
|
|
begin
|
|
if (a=0) then
|
|
list.concat(taicpu.op_reg_reg_reg(A_SUBcc,reg,NR_G0,NR_G0))
|
|
else
|
|
handle_reg_const_reg(list,A_SUBcc,reg,a,NR_G0);
|
|
a_jmp_cond(list,cmp_op,l);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_cmp_reg_reg_label(list:TAasmOutput;size:tcgsize;cmp_op:topcmp;reg1,reg2:tregister;l:tasmlabel);
|
|
begin
|
|
list.concat(taicpu.op_reg_reg_reg(A_SUBcc,reg2,reg1,NR_G0));
|
|
a_jmp_cond(list,cmp_op,l);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_jmp_always(List:TAasmOutput;l:TAsmLabel);
|
|
begin
|
|
List.Concat(TAiCpu.op_sym(A_BA,objectlibrary.newasmsymbol(l.name,AB_EXTERNAL,AT_FUNCTION)));
|
|
{ Delay slot }
|
|
list.Concat(TAiCpu.Op_none(A_NOP));
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_jmp_cond(list:TAasmOutput;cond:TOpCmp;l:TAsmLabel);
|
|
var
|
|
ai:TAiCpu;
|
|
begin
|
|
ai:=TAiCpu.Op_sym(A_Bxx,l);
|
|
ai.SetCondition(TOpCmp2AsmCond[cond]);
|
|
list.Concat(ai);
|
|
{ Delay slot }
|
|
list.Concat(TAiCpu.Op_none(A_NOP));
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.a_jmp_flags(list:TAasmOutput;const f:TResFlags;l:tasmlabel);
|
|
var
|
|
ai : taicpu;
|
|
op : tasmop;
|
|
begin
|
|
if f in [F_FE,F_FNE,F_FG,F_FL,F_FGE,F_FLE] then
|
|
op:=A_FBxx
|
|
else
|
|
op:=A_Bxx;
|
|
ai := Taicpu.op_sym(op,l);
|
|
ai.SetCondition(flags_to_cond(f));
|
|
list.Concat(ai);
|
|
{ Delay slot }
|
|
list.Concat(TAiCpu.Op_none(A_NOP));
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_flags2reg(list:TAasmOutput;Size:TCgSize;const f:tresflags;reg:TRegister);
|
|
var
|
|
hl : tasmlabel;
|
|
begin
|
|
objectlibrary.getlabel(hl);
|
|
a_load_const_reg(list,size,1,reg);
|
|
a_jmp_flags(list,f,hl);
|
|
a_load_const_reg(list,size,0,reg);
|
|
a_label(list,hl);
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_overflowCheck(List:TAasmOutput;const Loc:TLocation;def:TDef);
|
|
var
|
|
hl : tasmlabel;
|
|
begin
|
|
if not(cs_check_overflow in aktlocalswitches) then
|
|
exit;
|
|
objectlibrary.getlabel(hl);
|
|
if not((def.deftype=pointerdef)or
|
|
((def.deftype=orddef)and
|
|
(torddef(def).typ in [u64bit,u16bit,u32bit,u8bit,uchar,bool8bit,bool16bit,bool32bit]))) then
|
|
begin
|
|
//r.enum:=R_CR7;
|
|
//list.concat(taicpu.op_reg(A_MCRXR,r));
|
|
//a_jmp_cond(list,A_Bxx,C_OV,hl)
|
|
a_jmp_always(list,hl)
|
|
end
|
|
else
|
|
a_jmp_cond(list,OC_AE,hl);
|
|
a_call_name(list,'FPC_OVERFLOW');
|
|
a_label(list,hl);
|
|
end;
|
|
|
|
{ *********** entry/exit code and address loading ************ }
|
|
|
|
procedure TCgSparc.g_proc_entry(list : taasmoutput;localsize : longint;nostackframe:boolean);
|
|
begin
|
|
if nostackframe then
|
|
exit;
|
|
{ Althogh the SPARC architecture require only word alignment, software
|
|
convention and the operating system require every stack frame to be double word
|
|
aligned }
|
|
LocalSize:=align(LocalSize,8);
|
|
{ Execute the SAVE instruction to get a new register window and create a new
|
|
stack frame. In the "SAVE %i6,size,%i6" the first %i6 is related to the state
|
|
before execution of the SAVE instrucion so it is the caller %i6, when the %i6
|
|
after execution of that instruction is the called function stack pointer}
|
|
{ constant can be 13 bit signed, since it's negative, size can be max. 4096 }
|
|
if LocalSize>4096 then
|
|
begin
|
|
a_load_const_reg(list,OS_ADDR,-LocalSize,NR_G1);
|
|
list.concat(Taicpu.Op_reg_reg_reg(A_SAVE,NR_STACK_POINTER_REG,NR_G1,NR_STACK_POINTER_REG));
|
|
end
|
|
else
|
|
list.concat(Taicpu.Op_reg_const_reg(A_SAVE,NR_STACK_POINTER_REG,-LocalSize,NR_STACK_POINTER_REG));
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_restore_all_registers(list:TaasmOutput;const funcretparaloc:TCGPara);
|
|
begin
|
|
{ The sparc port uses the sparc standard calling convetions so this function has no used }
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_restore_standard_registers(list:taasmoutput);
|
|
begin
|
|
{ The sparc port uses the sparc standard calling convetions so this function has no used }
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_proc_exit(list : taasmoutput;parasize:longint;nostackframe:boolean);
|
|
begin
|
|
if nostackframe then
|
|
begin
|
|
{ Here we need to use RETL instead of RET so it uses %o7 }
|
|
list.concat(Taicpu.op_none(A_RETL));
|
|
list.concat(Taicpu.op_none(A_NOP))
|
|
end
|
|
else
|
|
begin
|
|
{ We use trivial restore in the delay slot of the JMPL instruction, as we
|
|
already set result onto %i0 }
|
|
list.concat(Taicpu.op_none(A_RET));
|
|
list.concat(Taicpu.op_none(A_RESTORE));
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_save_all_registers(list : taasmoutput);
|
|
begin
|
|
{ The sparc port uses the sparc standard calling convetions so this function has no used }
|
|
end;
|
|
|
|
|
|
procedure TCgSparc.g_save_standard_registers(list : taasmoutput);
|
|
begin
|
|
{ The sparc port uses the sparc standard calling convetions so this function has no used }
|
|
end;
|
|
|
|
|
|
{ ************* concatcopy ************ }
|
|
|
|
procedure TCgSparc.g_concatcopy(list:taasmoutput;const source,dest:treference;len:aint;loadref:boolean);
|
|
var
|
|
tmpreg1,
|
|
hreg,
|
|
countreg: TRegister;
|
|
src, dst: TReference;
|
|
lab: tasmlabel;
|
|
count, count2: aint;
|
|
orgsrc, orgdst: boolean;
|
|
begin
|
|
if len>high(longint) then
|
|
internalerror(2002072704);
|
|
reference_reset(src);
|
|
reference_reset(dst);
|
|
{ load the address of source into src.base }
|
|
if loadref then
|
|
begin
|
|
src.base:=GetAddressRegister(list);
|
|
a_load_ref_reg(list,OS_32,OS_32,source,src.base);
|
|
orgsrc := false;
|
|
end
|
|
else
|
|
begin
|
|
src.base:=GetAddressRegister(list);
|
|
a_loadaddr_ref_reg(list,source,src.base);
|
|
orgsrc := false;
|
|
end;
|
|
{ load the address of dest into dst.base }
|
|
dst.base:=GetAddressRegister(list);
|
|
a_loadaddr_ref_reg(list,dest,dst.base);
|
|
orgdst := false;
|
|
{ generate a loop }
|
|
count:=len div 4;
|
|
if count>4 then
|
|
begin
|
|
{ the offsets are zero after the a_loadaddress_ref_reg and just }
|
|
{ have to be set to 8. I put an Inc there so debugging may be }
|
|
{ easier (should offset be different from zero here, it will be }
|
|
{ easy to notice in the generated assembler }
|
|
countreg:=GetIntRegister(list,OS_INT);
|
|
tmpreg1:=GetIntRegister(list,OS_INT);
|
|
a_load_const_reg(list,OS_INT,count,countreg);
|
|
{ explicitely allocate R_O0 since it can be used safely here }
|
|
{ (for holding date that's being copied) }
|
|
objectlibrary.getlabel(lab);
|
|
a_label(list, lab);
|
|
list.concat(taicpu.op_ref_reg(A_LD,src,tmpreg1));
|
|
list.concat(taicpu.op_reg_ref(A_ST,tmpreg1,dst));
|
|
list.concat(taicpu.op_reg_const_reg(A_ADD,src.base,4,src.base));
|
|
list.concat(taicpu.op_reg_const_reg(A_ADD,dst.base,4,dst.base));
|
|
list.concat(taicpu.op_reg_const_reg(A_SUBcc,countreg,1,countreg));
|
|
a_jmp_cond(list,OC_NE,lab);
|
|
list.concat(taicpu.op_none(A_NOP));
|
|
{ keep the registers alive }
|
|
list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
|
|
list.concat(taicpu.op_reg_reg(A_MOV,src.base,src.base));
|
|
list.concat(taicpu.op_reg_reg(A_MOV,dst.base,dst.base));
|
|
len := len mod 4;
|
|
end;
|
|
{ unrolled loop }
|
|
count:=len div 4;
|
|
if count>0 then
|
|
begin
|
|
tmpreg1:=GetIntRegister(list,OS_INT);
|
|
for count2 := 1 to count do
|
|
begin
|
|
list.concat(taicpu.op_ref_reg(A_LD,src,tmpreg1));
|
|
list.concat(taicpu.op_reg_ref(A_ST,tmpreg1,dst));
|
|
inc(src.offset,4);
|
|
inc(dst.offset,4);
|
|
end;
|
|
len := len mod 4;
|
|
end;
|
|
if (len and 4) <> 0 then
|
|
begin
|
|
hreg:=GetIntRegister(list,OS_INT);
|
|
a_load_ref_reg(list,OS_32,OS_32,src,hreg);
|
|
a_load_reg_ref(list,OS_32,OS_32,hreg,dst);
|
|
inc(src.offset,4);
|
|
inc(dst.offset,4);
|
|
end;
|
|
{ copy the leftovers }
|
|
if (len and 2) <> 0 then
|
|
begin
|
|
hreg:=GetIntRegister(list,OS_INT);
|
|
a_load_ref_reg(list,OS_16,OS_16,src,hreg);
|
|
a_load_reg_ref(list,OS_16,OS_16,hreg,dst);
|
|
inc(src.offset,2);
|
|
inc(dst.offset,2);
|
|
end;
|
|
if (len and 1) <> 0 then
|
|
begin
|
|
hreg:=GetIntRegister(list,OS_INT);
|
|
a_load_ref_reg(list,OS_8,OS_8,src,hreg);
|
|
a_load_reg_ref(list,OS_8,OS_8,hreg,dst);
|
|
end;
|
|
end;
|
|
|
|
{****************************************************************************
|
|
TCG64Sparc
|
|
****************************************************************************}
|
|
|
|
|
|
procedure tcg64sparc.a_load64_reg_ref(list : taasmoutput;reg : tregister64;const ref : treference);
|
|
var
|
|
tmpref: treference;
|
|
begin
|
|
{ Override this function to prevent loading the reference twice }
|
|
tmpref:=ref;
|
|
tcgsparc(cg).make_simple_ref(list,tmpref);
|
|
cg.a_load_reg_ref(list,OS_32,OS_32,reg.reghi,tmpref);
|
|
inc(tmpref.offset,4);
|
|
cg.a_load_reg_ref(list,OS_32,OS_32,reg.reglo,tmpref);
|
|
end;
|
|
|
|
|
|
procedure tcg64sparc.a_load64_ref_reg(list : taasmoutput;const ref : treference;reg : tregister64);
|
|
var
|
|
tmpref: treference;
|
|
begin
|
|
{ Override this function to prevent loading the reference twice }
|
|
tmpref:=ref;
|
|
tcgsparc(cg).make_simple_ref(list,tmpref);
|
|
cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reghi);
|
|
inc(tmpref.offset,4);
|
|
cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reglo);
|
|
end;
|
|
|
|
|
|
procedure tcg64sparc.a_param64_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);
|
|
var
|
|
hreg64 : tregister64;
|
|
begin
|
|
{ Override this function to prevent loading the reference twice.
|
|
Use here some extra registers, but those are optimized away by the RA }
|
|
hreg64.reglo:=cg.GetIntRegister(list,OS_32);
|
|
hreg64.reghi:=cg.GetIntRegister(list,OS_32);
|
|
a_load64_ref_reg(list,r,hreg64);
|
|
a_param64_reg(list,hreg64,paraloc);
|
|
end;
|
|
|
|
|
|
procedure TCg64Sparc.get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp);
|
|
begin
|
|
case op of
|
|
OP_ADD :
|
|
begin
|
|
op1:=A_ADDCC;
|
|
op2:=A_ADDX;
|
|
end;
|
|
OP_SUB :
|
|
begin
|
|
op1:=A_SUBCC;
|
|
op2:=A_SUBX;
|
|
end;
|
|
OP_XOR :
|
|
begin
|
|
op1:=A_XOR;
|
|
op2:=A_XOR;
|
|
end;
|
|
OP_OR :
|
|
begin
|
|
op1:=A_OR;
|
|
op2:=A_OR;
|
|
end;
|
|
OP_AND :
|
|
begin
|
|
op1:=A_AND;
|
|
op2:=A_AND;
|
|
end;
|
|
else
|
|
internalerror(200203241);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCg64Sparc.a_op64_reg_reg(list:TAasmOutput;op:TOpCG;regsrc,regdst:TRegister64);
|
|
var
|
|
op1,op2 : TAsmOp;
|
|
begin
|
|
case op of
|
|
OP_NEG :
|
|
begin
|
|
{ Use the simple code: y=0-z }
|
|
list.concat(taicpu.op_reg_reg_reg(A_SUBcc,NR_G0,regsrc.reglo,regdst.reglo));
|
|
list.concat(taicpu.op_reg_reg_reg(A_SUBX,NR_G0,regsrc.reghi,regdst.reghi));
|
|
exit;
|
|
end;
|
|
OP_NOT :
|
|
begin
|
|
list.concat(taicpu.op_reg_reg_reg(A_XNOR,regsrc.reglo,NR_G0,regdst.reglo));
|
|
list.concat(taicpu.op_reg_reg_reg(A_XNOR,regsrc.reghi,NR_G0,regdst.reghi));
|
|
exit;
|
|
end;
|
|
end;
|
|
get_64bit_ops(op,op1,op2);
|
|
list.concat(taicpu.op_reg_reg_reg(op1,regdst.reglo,regsrc.reglo,regdst.reglo));
|
|
list.concat(taicpu.op_reg_reg_reg(op2,regdst.reghi,regsrc.reghi,regdst.reghi));
|
|
end;
|
|
|
|
|
|
procedure TCg64Sparc.a_op64_const_reg(list:TAasmOutput;op:TOpCG;value:int64;regdst:TRegister64);
|
|
var
|
|
op1,op2:TAsmOp;
|
|
begin
|
|
case op of
|
|
OP_NEG,
|
|
OP_NOT :
|
|
internalerror(200306017);
|
|
end;
|
|
get_64bit_ops(op,op1,op2);
|
|
tcgsparc(cg).handle_reg_const_reg(list,op1,regdst.reglo,aint(lo(value)),regdst.reglo);
|
|
tcgsparc(cg).handle_reg_const_reg(list,op1,regdst.reghi,aint(hi(value)),regdst.reghi);
|
|
end;
|
|
|
|
|
|
procedure tcg64sparc.a_op64_const_reg_reg(list: taasmoutput;op:TOpCG;value : int64; regsrc,regdst : tregister64);
|
|
var
|
|
op1,op2:TAsmOp;
|
|
begin
|
|
case op of
|
|
OP_NEG,
|
|
OP_NOT :
|
|
internalerror(200306017);
|
|
end;
|
|
get_64bit_ops(op,op1,op2);
|
|
tcgsparc(cg).handle_reg_const_reg(list,op1,regsrc.reglo,aint(lo(value)),regdst.reglo);
|
|
tcgsparc(cg).handle_reg_const_reg(list,op1,regsrc.reghi,aint(hi(value)),regdst.reghi);
|
|
end;
|
|
|
|
|
|
procedure tcg64sparc.a_op64_reg_reg_reg(list: taasmoutput;op:TOpCG;regsrc1,regsrc2,regdst : tregister64);
|
|
var
|
|
op1,op2:TAsmOp;
|
|
begin
|
|
case op of
|
|
OP_NEG,
|
|
OP_NOT :
|
|
internalerror(200306017);
|
|
end;
|
|
get_64bit_ops(op,op1,op2);
|
|
list.concat(taicpu.op_reg_reg_reg(op1,regsrc2.reglo,regsrc1.reglo,regdst.reglo));
|
|
list.concat(taicpu.op_reg_reg_reg(op2,regsrc2.reghi,regsrc1.reghi,regdst.reghi));
|
|
end;
|
|
|
|
|
|
begin
|
|
cg:=TCgSparc.Create;
|
|
cg64:=TCg64Sparc.Create;
|
|
end.
|
|
{
|
|
$Log$
|
|
Revision 1.89 2004-09-25 14:23:55 peter
|
|
* ungetregister is now only used for cpuregisters, renamed to
|
|
ungetcpuregister
|
|
* renamed (get|unget)explicitregister(s) to ..cpuregister
|
|
* removed location-release/reference_release
|
|
|
|
Revision 1.88 2004/09/21 20:33:00 peter
|
|
* don't remove MOV reg1,reg1 it is needed for the RA
|
|
|
|
Revision 1.87 2004/09/21 17:25:13 peter
|
|
* paraloc branch merged
|
|
|
|
Revision 1.86.4.5 2004/09/20 20:43:15 peter
|
|
* implement reg_ref/ref_reg for 64bit to prevent loading the
|
|
address symbol twice
|
|
|
|
Revision 1.86.4.4 2004/09/17 17:19:26 peter
|
|
* fixed 64 bit unaryminus for sparc
|
|
* fixed 64 bit inlining
|
|
* signness of not operation
|
|
|
|
Revision 1.86.4.3 2004/09/12 21:31:03 peter
|
|
* sign extension added
|
|
|
|
Revision 1.86.4.2 2004/09/12 13:36:40 peter
|
|
* fixed alignment issues
|
|
|
|
Revision 1.86.4.1 2004/08/31 20:43:06 peter
|
|
* paraloc patch
|
|
|
|
Revision 1.86 2004/08/25 20:40:04 florian
|
|
* fixed absolute on sparc
|
|
|
|
Revision 1.85 2004/08/24 21:02:32 florian
|
|
* fixed longbool(<int64>) on sparc
|
|
|
|
Revision 1.84 2004/06/20 08:55:32 florian
|
|
* logs truncated
|
|
|
|
Revision 1.83 2004/06/16 20:07:10 florian
|
|
* dwarf branch merged
|
|
|
|
Revision 1.82.2.9 2004/06/02 19:05:16 peter
|
|
* use a_load_const_reg to load const
|
|
|
|
Revision 1.82.2.8 2004/06/02 16:07:40 peter
|
|
* implement op64_reg_reg_reg
|
|
|
|
Revision 1.82.2.7 2004/05/31 22:07:54 peter
|
|
* don't use float in concatcopy
|
|
|
|
Revision 1.82.2.6 2004/05/30 17:54:14 florian
|
|
+ implemented cmp64bit
|
|
* started to fix spilling
|
|
* fixed int64 sub partially
|
|
|
|
}
|