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265 lines
10 KiB
ObjectPascal
265 lines
10 KiB
ObjectPascal
{
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Copyright (c) 1998-2008 by Florian Klaempfl
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Generates AVR assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit navrmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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tavrmoddivnode = class(tmoddivnode)
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function first_moddivint: tnode;override;
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procedure pass_generate_code;override;
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end;
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tavrnotnode = class(tcgnotnode)
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procedure second_boolean;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,constexp,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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cgbase,cgobj,cgutils,
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pass_2,procinfo,
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ncon,
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cpubase,
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ncgutil,cgcpu;
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{*****************************************************************************
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TAVRMODDIVNODE
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*****************************************************************************}
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function tavrmoddivnode.first_moddivint: tnode;
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var
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power : longint;
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begin
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if (right.nodetype=ordconstn) and
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(nodetype=divn) and
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(ispowerof2(tordconstnode(right).value,power) or
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(tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1))
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) and
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not(is_64bitint(resultdef)) then
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result:=nil
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else
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result:=inherited first_moddivint;
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end;
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procedure tavrmoddivnode.pass_generate_code;
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var
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power : longint;
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numerator,
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helper1,
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helper2,
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resultreg : tregister;
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size : Tcgsize;
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so : tshifterop;
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{
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procedure genOrdConstNodeDiv;
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begin
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if tordconstnode(right).value=0 then
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internalerror(2005061701)
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else if tordconstnode(right).value=1 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, numerator, resultreg)
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else if (tordconstnode(right).value = int64(-1)) then
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begin
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// note: only in the signed case possible..., may overflow
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MVN,
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resultreg,numerator),toppostfix(ord(cs_check_overflow in current_settings.localswitches)*ord(PF_S))));
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end
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else if ispowerof2(tordconstnode(right).value,power) then
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begin
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if (is_signed(right.resultdef)) then
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begin
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helper1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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helper2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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shifterop_reset(so);
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so.shiftmode:=SM_ASR;
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so.shiftimm:=31;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_shifterop(A_MOV,helper1,numerator,so));
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shifterop_reset(so);
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so.shiftmode:=SM_LSR;
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so.shiftimm:=32-power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,helper2,numerator,helper1,so));
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shifterop_reset(so);
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so.shiftmode:=SM_ASR;
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so.shiftimm:=power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_shifterop(A_MOV,resultreg,helper2,so));
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end
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,power,numerator,resultreg)
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end;
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end;
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}
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{
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procedure genOrdConstNodeMod;
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var
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modreg, maskreg, tempreg : tregister;
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begin
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061702);
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end
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else if (abs(tordconstnode(right).value.svalue) = 1) then
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begin
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// x mod +/-1 is always zero
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, 0, resultreg);
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end
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else if (ispowerof2(tordconstnode(right).value, power)) then
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begin
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if (is_signed(right.resultdef)) then begin
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tempreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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maskreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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modreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, abs(tordconstnode(right).value.svalue)-1, modreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, 31, numerator, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, numerator, modreg, tempreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ANDC, maskreg, maskreg, modreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC, modreg, tempreg, 0));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBFE, modreg, modreg, modreg));
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, modreg, maskreg, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_INT, maskreg, tempreg, resultreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, tordconstnode(right).value.svalue-1, numerator, resultreg);
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end;
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end else begin
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genOrdConstNodeDiv();
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_MUL, OS_INT, tordconstnode(right).value.svalue, resultreg, resultreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, resultreg, numerator, resultreg);
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end;
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end;
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}
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begin
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{
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secondpass(left);
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secondpass(right);
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resultdef);
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location_force_reg(current_asmdata.CurrAsmList,left.location,
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size,true);
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location_copy(location,left.location);
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numerator:=location.register;
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resultreg:=location.register;
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if location.loc=LOC_CREGISTER then
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begin
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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end
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else if (nodetype=modn) or (right.nodetype=ordconstn) then
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begin
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// for a modulus op, and for const nodes we need the result register
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// to be an extra register
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resultreg:=cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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if right.nodetype=ordconstn then
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begin
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if nodetype=divn then
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genOrdConstNodeDiv
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else
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// genOrdConstNodeMod;
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end;
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location.register:=resultreg;
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{ unsigned division/module can only overflow in case of division by zero }
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{ (but checking this overflow flag is more convoluted than performing a }
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{ simple comparison with 0) }
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if is_signed(right.resultdef) then
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cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
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}
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end;
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{*****************************************************************************
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TAVRNOTNODE
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*****************************************************************************}
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procedure tavrnotnode.second_boolean;
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var
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hl : tasmlabel;
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tmpreg : tregister;
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i : longint;
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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}
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if left.expectloc=LOC_JUMP then
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begin
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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secondpass(left);
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maketojumpbool(current_asmdata.CurrAsmList,left,lr_load_regvars);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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location.loc:=LOC_JUMP;
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end
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else
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begin
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE,
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LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF :
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begin
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CPI,left.location.register,0));
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tmpreg:=left.location.register;
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{ avr has no cpci, so we use the first register as "zero" register }
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for i:=2 to tcgsize2size[left.location.size] do
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg,left.location.register));
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end;
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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begin
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cmoddivnode:=tavrmoddivnode;
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cnotnode:=tavrnotnode;
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end.
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