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1df13c788c
* started to fix ppc, needs an overhaul + stabs info improve for spilling, not sure if it works correctly/completly - MMX_SUPPORT removed from Makefile.fpc
1936 lines
62 KiB
ObjectPascal
1936 lines
62 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the base class for the register allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{$i fpcdefs.inc}
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{ Allow duplicate allocations, can be used to get the .s file written }
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{ $define ALLOWDUPREG}
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{#******************************************************************************
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@abstract(Abstract register allocator unit)
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Register allocator introduction.
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Free Pascal uses a Chaitin style register allocator. We use a variant similair
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to the one described in the book "Modern compiler implementation in C" by
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Andrew W. Appel., published by Cambridge University Press.
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The register allocator that is described by Appel uses a much improved way
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of register coalescing, called "iterated register coalescing". Instead
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of doing coalescing as a prepass to the register allocation, the coalescing
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is done inside the register allocator. This has the advantage that the
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register allocator can coalesce very aggresively without introducing spills.
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Reading this book is recommended for a complete understanding. Here is a small
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introduction.
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The code generator thinks it has an infinite amount of registers. Our processor
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has a limited amount of registers. Therefore we must reduce the amount of
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registers until there are less enough to fit into the processors registers.
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Registers can interfere or not interfere. If two imaginary registers interfere
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they cannot be placed into the same psysical register. Reduction of registers
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is done by:
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- "coalescing" Two registers that do not interfere are combined
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into one register.
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- "spilling" A register is changed into a memory location and the generated
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code is modified to use the memory location instead of the register.
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Register allocation is a graph colouring problem. Each register is a colour, and
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if two registers interfere there is a connection between them in the graph.
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In addition to the imaginary registers in the code generator, the psysical
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CPU registers are also present in this graph. This allows us to make
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interferences between imaginary registers and cpu registers. This is very
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usefull for describing archtectural constraints, like for example that
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the div instruction modifies edx, so variables that are in use at that time
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cannot be stored into edx. This can be modelled by making edx interfere
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with those variables.
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Graph colouring is an NP complete problem. Therefore we use an approximation
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that pushes registers to colour on to a stack. This is done in the "simplify"
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procedure.
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The register allocator first checks which registers are a candidate for
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coalescing.
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*******************************************************************************}
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unit rgobj;
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interface
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uses
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cutils, cpubase,
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aasmbase,aasmtai,aasmcpu,
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cclasses,globtype,cgbase,node,
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{$ifdef delphi}
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dmisc,
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{$endif}
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cpuinfo
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;
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const
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ALL_OTHERREGISTERS=[low(tregisterindex)..high(tregisterindex)];
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type
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regvarother_longintarray = array[tregisterindex] of longint;
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regvarother_booleanarray = array[tregisterindex] of boolean;
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regvarint_longintarray = array[first_int_supreg..last_int_supreg] of longint;
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regvarint_ptreearray = array[first_int_supreg..last_int_supreg] of tnode;
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tpushedsavedloc = record
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case byte of
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0: (pushed: boolean);
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1: (ofs: longint);
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end;
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tpushedsavedother = array[tregisterindex] of tpushedsavedloc;
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Tinterferencebitmap=array[Tsuperregister] of set of Tsuperregister;
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Tinterferenceadjlist=array[Tsuperregister] of Pstring;
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Tinterferencegraph=record
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bitmap:Tinterferencebitmap;
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adjlist:Tinterferenceadjlist;
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end;
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Pinterferencegraph=^Tinterferencegraph;
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Tmovelist=record
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count:cardinal;
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data:array[0..$ffff] of Tlinkedlistitem;
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end;
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Pmovelist=^Tmovelist;
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{In the register allocator we keep track of move instructions.
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These instructions are moved between five linked lists. There
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is also a linked list per register to keep track about the moves
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it is associated with. Because we need to determine quickly in
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which of the five lists it is we add anu enumeradtion to each
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move instruction.}
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Tmoveset=(ms_coalesced_moves,ms_constrained_moves,ms_frozen_moves,
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ms_worklist_moves,ms_active_moves);
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Tmoveins=class(Tlinkedlistitem)
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moveset:Tmoveset;
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{ $ifdef ra_debug}
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x,y:Tsuperregister;
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{ $endif}
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instruction:Taicpu;
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end;
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{#------------------------------------------------------------------
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This class implements the abstract register allocator. It is used by the
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code generator to allocate and free registers which might be valid across
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nodes. It also contains utility routines related to registers.
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Some of the methods in this class should be overriden
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by cpu-specific implementations.
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--------------------------------------------------------------------}
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trgobj=class
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preserved_by_proc,used_in_proc:Tsuperregisterset;
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is_reg_var:Tsuperregisterset; {old regvars}
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reg_var_loaded:Tsuperregisterset; {old regvars}
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{# The register allocator assigns each register a colour.}
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colour:array[Tsuperregister] of Tsuperregister;
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spillednodes:string;
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constructor create(Acpu_registers:byte;
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Aregtype:Tregistertype;
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Adefaultsub:Tsubregister;
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const Ausable:string;
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Afirst_imaginary:Tsuperregister;
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Apreserved_by_proc:Tsuperregisterset);
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destructor destroy;override;
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{# Allocate a register. An internalerror will be generated if there is
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no more free registers which can be allocated.}
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function getregister(list:Taasmoutput;subreg:Tsubregister):Tregister;
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procedure add_constraints(reg:Tregister);virtual;
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{# Allocate an ABT register. An internalerror will be generated if there
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are no more free registers that can be allocated. An explanantion of
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abt registers can be found near the implementation.}
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function getabtregister(list:Taasmoutput;subreg:Tsubregister):Tregister;
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{# Get the register specified.}
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procedure getexplicitregister(list:Taasmoutput;r:Tregister);
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{# Get multiple registers specified.}
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procedure allocexplicitregisters(list:Taasmoutput;r:Tsuperregisterset);
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{# Free multiple registers specified.}
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procedure deallocexplicitregisters(list:Taasmoutput;r:Tsuperregisterset);
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{# Deallocate any kind of register }
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procedure ungetregister(list:Taasmoutput;r:Tregister);virtual;
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{# Do the register allocation.}
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procedure do_register_allocation(list:Taasmoutput;headertai:tai);
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{ procedure resetusableregisters;virtual;}
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{ procedure makeregvar(reg:Tsuperregister);}
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{$ifdef EXTDEBUG}
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procedure writegraph(loopidx:longint);
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{$endif EXTDEBUG}
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procedure add_move_instruction(instr:Taicpu);
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{# Prepare the register colouring.}
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procedure prepare_colouring;
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{# Clean up after register colouring.}
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procedure epilogue_colouring;
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{# Colour the registers; that is do the register allocation.}
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procedure colour_registers;
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{# Spills certain registers in the specified assembler list.}
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function spill_registers(list:Taasmoutput;headertai:tai;const regs_to_spill:string):boolean;
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{# Adds an interference edge.}
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procedure add_edge(u,v:Tsuperregister);
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unusedregs,usableregs:Tsuperregisterset;
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protected
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regtype:Tregistertype;
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{ default subregister used }
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defaultsub:tsubregister;
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{# First imaginary register.}
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first_imaginary,
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{# Last register allocated.}
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lastused,
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{# Highest register allocated until now.}
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maxreg:Tsuperregister;
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usable_registers:string[32];
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countusableregs:byte; {old regvars}
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cpu_registers:byte;
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igraph:Tinterferencegraph;
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degree:array[0..255] of byte;
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alias:array[Tsuperregister] of Tsuperregister;
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simplifyworklist,freezeworklist,spillworklist:string;
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coalescednodes:string;
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selectstack:string;
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abtlist:string;
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movelist:array[Tsuperregister] of Pmovelist;
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worklist_moves,active_moves,frozen_moves,
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coalesced_moves,constrained_moves:Tlinkedlist;
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procedure getregisterinline(list:Taasmoutput;position:Tai;subreg:Tsubregister;var result:Tregister);
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procedure ungetregisterinline(list:Taasmoutput;position:Tai;r:Tregister);
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procedure add_edges_used(u:Tsuperregister);
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procedure add_to_movelist(u:Tsuperregister;data:Tlinkedlistitem);
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function move_related(n:Tsuperregister):boolean;
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procedure make_work_list;
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procedure enable_moves(n:Tsuperregister);
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procedure decrement_degree(m:Tsuperregister);
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procedure simplify;
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function get_alias(n:Tsuperregister):Tsuperregister;
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procedure add_worklist(u:Tsuperregister);
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function adjacent_ok(u,v:Tsuperregister):boolean;
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function conservative(u,v:Tsuperregister):boolean;
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procedure combine(u,v:Tsuperregister);
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procedure coalesce;
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procedure freeze_moves(u:Tsuperregister);
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procedure freeze;
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procedure select_spill;
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procedure assign_colours;
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procedure clear_interferences(u:Tsuperregister);
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end;
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const {# This value is used in tsaved. If the array value is equal
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to this, then this means that this register is not used.}
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reg_not_saved = $7fffffff;
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first_reg = 0;
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last_reg = 254;
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maxspillingcounter = 20;
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implementation
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uses
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systems,
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globals,verbose,tgobj,procinfo;
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{******************************************************************************
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trgobj
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******************************************************************************}
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constructor trgobj.create(Acpu_registers:byte;
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Aregtype:Tregistertype;
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Adefaultsub:Tsubregister;
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const Ausable:string;
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Afirst_imaginary:Tsuperregister;
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Apreserved_by_proc:Tsuperregisterset);
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var i:Tsuperregister;
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begin
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used_in_proc:=[];
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{ resetusableregisters;}
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lastused:=0;
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maxreg:=Afirst_imaginary;
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first_imaginary:=Afirst_imaginary;
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cpu_registers:=Acpu_registers;
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regtype:=Aregtype;
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defaultsub:=Adefaultsub;
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unusedregs:=[first_reg..last_reg]; { 255 (RS_INVALID) can't be used }
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{$ifdef powerpc}
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preserved_by_proc:=[RS_R13..RS_R31];
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{$else powerpc}
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preserved_by_proc:=[];
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{$endif powerpc}
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fillchar(igraph,sizeof(igraph),0);
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fillchar(degree,sizeof(degree),0);
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{Precoloured nodes should have an infinite degree, which we can approach
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by 255.}
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for i:=0 to first_imaginary-1 do
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degree[i]:=255;
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fillchar(movelist,sizeof(movelist),0);
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worklist_moves:=Tlinkedlist.create;
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usable_registers:=Ausable;
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abtlist:='';
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fillchar(colour,sizeof(colour),RS_INVALID);
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end;
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destructor trgobj.destroy;
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var i:Tsuperregister;
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begin
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for i:=low(Tsuperregister) to high(Tsuperregister) do
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begin
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if igraph.adjlist[i]<>nil then
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dispose(igraph.adjlist[i]);
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if movelist[i]<>nil then
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dispose(movelist[i]);
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end;
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worklist_moves.free;
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end;
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function trgobj.getregister(list:Taasmoutput;subreg:Tsubregister):Tregister;
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var i,p:Tsuperregister;
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r:Tregister;
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min : byte;
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adj : pstring;
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begin
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if maxreg<last_reg then
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begin
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inc(maxreg);
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p:=maxreg;
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min:=0;
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end
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else
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begin
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min:=$ff;
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p:=first_imaginary;
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for i:=first_imaginary to maxreg do
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if (i in unusedregs) and
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(pos(char(i),abtlist)=0) then
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begin
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adj:=igraph.adjlist[Tsuperregister(i)];
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if adj=nil then
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begin
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p:=i;
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min:=0;
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break; {We won't find smaller ones.}
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end
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else
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if length(adj^)<min then
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begin
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p:=i;
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min:=length(adj^);
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if min=0 then
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break; {We won't find smaller ones.}
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end;
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end;
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if min=$ff then
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begin
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{$ifdef ALLOWDUPREG}
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result:=newreg(regtype,RS_INVALID,subreg);
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exit;
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{$else}
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internalerror(10);
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{$endif}
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end;
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end;
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exclude(unusedregs,p);
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include(used_in_proc,p);
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r:=newreg(regtype,p,subreg);
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list.concat(Tai_regalloc.alloc(r));
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add_edges_used(p);
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add_constraints(r);
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result:=r;
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end;
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procedure trgobj.ungetregister(list:Taasmoutput;r:Tregister);
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var supreg:Tsuperregister;
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begin
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supreg:=getsupreg(r);
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if not (supreg in unusedregs) then
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begin
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include(unusedregs,supreg);
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list.concat(Tai_regalloc.dealloc(r));
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add_edges_used(supreg);
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add_constraints(r);
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end;
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end;
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procedure trgobj.getexplicitregister(list:Taasmoutput;r:Tregister);
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var supreg:Tsuperregister;
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begin
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supreg:=getsupreg(r);
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if supreg in unusedregs then
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begin
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exclude(unusedregs,supreg);
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include(used_in_proc,supreg);
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list.concat(Tai_regalloc.alloc(r));
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add_edges_used(supreg);
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add_constraints(r);
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end
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else
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{$ifndef ALLOWDUPREG}
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internalerror(200301103)
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{$endif ALLOWDUPREG}
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;
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end;
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procedure trgobj.allocexplicitregisters(list:Taasmoutput;r:Tsuperregisterset);
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var reg:Tregister;
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i:Tsuperregister;
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begin
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if unusedregs*r=r then
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begin
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unusedregs:=unusedregs-r;
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used_in_proc:=used_in_proc+r;
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for i:=0 to first_imaginary-1 do
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if i in r then
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begin
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add_edges_used(i);
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reg:=newreg(regtype,i,R_SUBWHOLE);
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list.concat(Tai_regalloc.alloc(reg));
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end;
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end
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else
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{$ifndef ALLOWDUPREG}
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internalerror(200305061)
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{$endif ALLOWDUPREG}
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;
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end;
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procedure trgobj.deallocexplicitregisters(list:Taasmoutput;r:Tsuperregisterset);
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var reg:Tregister;
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i:Tsuperregister;
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begin
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if unusedregs*r=[] then
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begin
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unusedregs:=unusedregs+r;
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for i:=first_imaginary-1 downto 0 do
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if i in r then
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begin
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reg:=newreg(regtype,i,R_SUBWHOLE);
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list.concat(Tai_regalloc.dealloc(reg));
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end;
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end
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else
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internalerror(200305061);
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end;
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procedure trgobj.do_register_allocation(list:Taasmoutput;headertai:tai);
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var spillingcounter:byte;
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fastspill:boolean;
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begin
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{Do register allocation.}
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spillingcounter:=0;
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repeat
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prepare_colouring;
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colour_registers;
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epilogue_colouring;
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fastspill:=true;
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if spillednodes<>'' then
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begin
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inc(spillingcounter);
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if spillingcounter>maxspillingcounter then
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internalerror(200309041);
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fastspill:=spill_registers(list,headertai,spillednodes);
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end;
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until (spillednodes='') or not fastspill;
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end;
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procedure trgobj.add_constraints(reg:Tregister);
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begin
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end;
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procedure trgobj.add_edge(u,v:Tsuperregister);
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{This procedure will add an edge to the virtual interference graph.}
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procedure addadj(u,v:Tsuperregister);
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begin
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if igraph.adjlist[u]=nil then
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begin
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getmem(igraph.adjlist[u],16);
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igraph.adjlist[u]^:='';
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end
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else if (length(igraph.adjlist[u]^) and 15)=15 then
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reallocmem(igraph.adjlist[u],length(igraph.adjlist[u]^)+16);
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igraph.adjlist[u]^:=igraph.adjlist[u]^+char(v);
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end;
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begin
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if (u<>v) and not(v in igraph.bitmap[u]) then
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begin
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include(igraph.bitmap[u],v);
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include(igraph.bitmap[v],u);
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{Precoloured nodes are not stored in the interference graph.}
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if not(u in [first_int_supreg..last_int_supreg]) then
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begin
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addadj(u,v);
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inc(degree[u]);
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end;
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if not(v in [first_int_supreg..last_int_supreg]) then
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begin
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addadj(v,u);
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inc(degree[v]);
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end;
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end;
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end;
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|
procedure trgobj.add_edges_used(u:Tsuperregister);
|
|
|
|
var i:Tsuperregister;
|
|
|
|
begin
|
|
for i:=0 to maxreg do
|
|
if not(i in unusedregs) then
|
|
add_edge(u,i);
|
|
end;
|
|
|
|
{$ifdef EXTDEBUG}
|
|
procedure trgobj.writegraph(loopidx:longint);
|
|
|
|
{This procedure writes out the current interference graph in the
|
|
register allocator.}
|
|
|
|
|
|
var f:text;
|
|
i,j:Tsuperregister;
|
|
|
|
begin
|
|
assign(f,'igraph'+tostr(loopidx));
|
|
rewrite(f);
|
|
writeln(f,'Interference graph');
|
|
writeln(f);
|
|
write(f,' ');
|
|
for i:=0 to 15 do
|
|
for j:=0 to 15 do
|
|
write(f,hexstr(i,1));
|
|
writeln(f);
|
|
write(f,' ');
|
|
for i:=0 to 15 do
|
|
write(f,'0123456789ABCDEF');
|
|
writeln(f);
|
|
for i:=0 to 255 do
|
|
begin
|
|
write(f,hexstr(i,2):4);
|
|
for j:=0 to 255 do
|
|
if j in igraph.bitmap[i] then
|
|
write(f,'*')
|
|
else
|
|
write(f,'-');
|
|
writeln(f);
|
|
end;
|
|
close(f);
|
|
end;
|
|
{$endif EXTDEBUG}
|
|
|
|
procedure trgobj.add_to_movelist(u:Tsuperregister;data:Tlinkedlistitem);
|
|
|
|
begin
|
|
if movelist[u]=nil then
|
|
begin
|
|
getmem(movelist[u],64);
|
|
movelist[u]^.count:=0;
|
|
end
|
|
else if (movelist[u]^.count and 15)=15 then
|
|
reallocmem(movelist[u],(movelist[u]^.count+1)*4+64);
|
|
movelist[u]^.data[movelist[u]^.count]:=data;
|
|
inc(movelist[u]^.count);
|
|
end;
|
|
|
|
procedure trgobj.add_move_instruction(instr:Taicpu);
|
|
|
|
{This procedure notifies a certain as a move instruction so the
|
|
register allocator can try to eliminate it.}
|
|
|
|
var i:Tmoveins;
|
|
ssupreg,dsupreg:Tsuperregister;
|
|
|
|
begin
|
|
i:=Tmoveins.create;
|
|
i.moveset:=ms_worklist_moves;
|
|
i.instruction:=instr;
|
|
worklist_moves.insert(i);
|
|
ssupreg:=getsupreg(instr.oper[O_MOV_SOURCE].reg);
|
|
add_to_movelist(ssupreg,i);
|
|
dsupreg:=getsupreg(instr.oper[O_MOV_DEST].reg);
|
|
if ssupreg<>dsupreg then
|
|
{Avoid adding the same move instruction twice to a single register.}
|
|
add_to_movelist(dsupreg,i);
|
|
i.x:=ssupreg;
|
|
i.y:=dsupreg;
|
|
end;
|
|
|
|
function trgobj.move_related(n:Tsuperregister):boolean;
|
|
|
|
var i:cardinal;
|
|
|
|
begin
|
|
move_related:=false;
|
|
if movelist[n]<>nil then
|
|
begin
|
|
for i:=0 to movelist[n]^.count-1 do
|
|
if Tmoveins(movelist[n]^.data[i]).moveset in
|
|
[ms_worklist_moves,ms_active_moves] then
|
|
begin
|
|
move_related:=true;
|
|
break;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
procedure trgobj.make_work_list;
|
|
|
|
var n:Tsuperregister;
|
|
|
|
begin
|
|
{If we have 7 cpu registers, and the degree of a node is 7, we cannot
|
|
assign it to any of the registers, thus it is significant.}
|
|
for n:=first_imaginary to maxreg do
|
|
if degree[n]>=cpu_registers then
|
|
spillworklist:=spillworklist+char(n)
|
|
else if move_related(n) then
|
|
freezeworklist:=freezeworklist+char(n)
|
|
else
|
|
simplifyworklist:=simplifyworklist+char(n);
|
|
end;
|
|
|
|
procedure trgobj.prepare_colouring;
|
|
|
|
begin
|
|
make_work_list;
|
|
active_moves:=Tlinkedlist.create;
|
|
frozen_moves:=Tlinkedlist.create;
|
|
coalesced_moves:=Tlinkedlist.create;
|
|
constrained_moves:=Tlinkedlist.create;
|
|
fillchar(alias,sizeof(alias),0);
|
|
coalescednodes:='';
|
|
selectstack:='';
|
|
end;
|
|
|
|
procedure trgobj.enable_moves(n:Tsuperregister);
|
|
|
|
var m:Tlinkedlistitem;
|
|
i:cardinal;
|
|
|
|
begin
|
|
if movelist[n]<>nil then
|
|
for i:=0 to movelist[n]^.count-1 do
|
|
begin
|
|
m:=movelist[n]^.data[i];
|
|
if Tmoveins(m).moveset in [ms_worklist_moves,ms_active_moves] then
|
|
begin
|
|
if Tmoveins(m).moveset=ms_active_moves then
|
|
begin
|
|
{Move m from the set active_moves to the set worklist_moves.}
|
|
active_moves.remove(m);
|
|
Tmoveins(m).moveset:=ms_worklist_moves;
|
|
worklist_moves.concat(m);
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
procedure trgobj.decrement_degree(m:Tsuperregister);
|
|
|
|
var adj:Pstring;
|
|
d:byte;
|
|
i,p:byte;
|
|
n:char;
|
|
|
|
begin
|
|
d:=degree[m];
|
|
if degree[m]>0 then
|
|
dec(degree[m]);
|
|
if d=cpu_registers then
|
|
begin
|
|
{Enable moves for m.}
|
|
enable_moves(m);
|
|
{Enable moves for adjacent.}
|
|
adj:=igraph.adjlist[m];
|
|
if adj<>nil then
|
|
for i:=1 to length(adj^) do
|
|
begin
|
|
n:=adj^[i];
|
|
if (pos(n,selectstack) or pos(n,coalescednodes))=0 then
|
|
enable_moves(Tsuperregister(n));
|
|
end;
|
|
{Remove the node from the spillworklist.}
|
|
p:=pos(char(m),spillworklist);
|
|
if p=0 then
|
|
internalerror(200305301); {must be found}
|
|
if length(spillworklist)>1 then
|
|
spillworklist[p]:=spillworklist[length(spillworklist)];
|
|
dec(spillworklist[0]);
|
|
|
|
if move_related(m) then
|
|
freezeworklist:=freezeworklist+char(m)
|
|
else
|
|
simplifyworklist:=simplifyworklist+char(m);
|
|
end;
|
|
end;
|
|
|
|
procedure trgobj.simplify;
|
|
|
|
var adj:Pstring;
|
|
i,min,p:byte;
|
|
m:char;
|
|
n:Tsuperregister;
|
|
|
|
begin
|
|
{We the element with the least interferences out of the
|
|
simplifyworklist.}
|
|
min:=$ff;
|
|
p:=1;
|
|
for i:=1 to length(simplifyworklist) do
|
|
begin
|
|
adj:=igraph.adjlist[Tsuperregister(simplifyworklist[i])];
|
|
if adj=nil then
|
|
begin
|
|
min:=0;
|
|
break; {We won't find smaller ones.}
|
|
end
|
|
else
|
|
if length(adj^)<min then
|
|
begin
|
|
min:=length(adj^);
|
|
if min=0 then
|
|
break; {We won't find smaller ones.}
|
|
p:=i;
|
|
end;
|
|
end;
|
|
n:=Tsuperregister(simplifyworklist[p]);
|
|
if length(simplifyworklist)>1 then
|
|
simplifyworklist[p]:=simplifyworklist[length(simplifyworklist)];
|
|
dec(simplifyworklist[0]);
|
|
|
|
{Push it on the selectstack.}
|
|
selectstack:=selectstack+char(n);
|
|
adj:=igraph.adjlist[n];
|
|
if adj<>nil then
|
|
for i:=1 to length(adj^) do
|
|
begin
|
|
m:=adj^[i];
|
|
if ((pos(m,selectstack) or pos(m,coalescednodes))=0) and
|
|
not (Tsuperregister(m) in [first_int_supreg..last_int_supreg]) then
|
|
decrement_degree(Tsuperregister(m));
|
|
end;
|
|
end;
|
|
|
|
function trgobj.get_alias(n:Tsuperregister):Tsuperregister;
|
|
|
|
begin
|
|
while pos(char(n),coalescednodes)<>0 do
|
|
n:=alias[n];
|
|
get_alias:=n;
|
|
end;
|
|
|
|
procedure trgobj.add_worklist(u:Tsuperregister);
|
|
|
|
var p:byte;
|
|
|
|
begin
|
|
if not(u in [first_int_supreg..last_int_supreg]) and
|
|
not move_related(u) and
|
|
(degree[u]<cpu_registers) then
|
|
begin
|
|
p:=pos(char(u),freezeworklist);
|
|
if p=0 then
|
|
internalerror(200308161); {must be found}
|
|
if length(freezeworklist)>1 then
|
|
freezeworklist[p]:=freezeworklist[length(freezeworklist)];
|
|
dec(freezeworklist[0]);
|
|
simplifyworklist:=simplifyworklist+char(u);
|
|
end;
|
|
end;
|
|
|
|
function trgobj.adjacent_ok(u,v:Tsuperregister):boolean;
|
|
|
|
{Check wether u and v should be coalesced. u is precoloured.}
|
|
|
|
function ok(t,r:Tsuperregister):boolean;
|
|
|
|
begin
|
|
ok:=(degree[t]<cpu_registers) or
|
|
(t in [first_int_supreg..last_int_supreg]) or
|
|
(r in igraph.bitmap[t]);
|
|
end;
|
|
|
|
var adj:Pstring;
|
|
i:byte;
|
|
t:char;
|
|
|
|
begin
|
|
adjacent_ok:=true;
|
|
adj:=igraph.adjlist[v];
|
|
if adj<>nil then
|
|
for i:=1 to length(adj^) do
|
|
begin
|
|
t:=adj^[i];
|
|
if (pos(t,selectstack) or pos(t,coalescednodes))=0 then
|
|
if not ok(Tsuperregister(t),u) then
|
|
begin
|
|
adjacent_ok:=false;
|
|
break;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
function trgobj.conservative(u,v:Tsuperregister):boolean;
|
|
|
|
var adj:Pstring;
|
|
done:set of char; {To prevent that we count nodes twice.}
|
|
i,k:byte;
|
|
n:char;
|
|
|
|
begin
|
|
k:=0;
|
|
done:=[];
|
|
adj:=igraph.adjlist[u];
|
|
if adj<>nil then
|
|
for i:=1 to length(adj^) do
|
|
begin
|
|
n:=adj^[i];
|
|
if (pos(n,selectstack) or pos(n,coalescednodes))=0 then
|
|
begin
|
|
include(done,n);
|
|
if degree[Tsuperregister(n)]>=cpu_registers then
|
|
inc(k);
|
|
end;
|
|
end;
|
|
adj:=igraph.adjlist[v];
|
|
if adj<>nil then
|
|
for i:=1 to length(adj^) do
|
|
begin
|
|
n:=adj^[i];
|
|
if ((pos(n,selectstack) or pos(n,coalescednodes))=0) and
|
|
not (n in done) and
|
|
(degree[Tsuperregister(n)]>=cpu_registers) then
|
|
inc(k);
|
|
end;
|
|
conservative:=(k<cpu_registers);
|
|
end;
|
|
|
|
procedure trgobj.combine(u,v:Tsuperregister);
|
|
|
|
var add:boolean;
|
|
adj:Pstring;
|
|
i,p:byte;
|
|
n,o:cardinal;
|
|
t:char;
|
|
decrement:boolean;
|
|
|
|
begin
|
|
p:=pos(char(v),freezeworklist);
|
|
if p<>0 then
|
|
delete(freezeworklist,p,1)
|
|
else
|
|
delete(spillworklist,pos(char(v),spillworklist),1);
|
|
coalescednodes:=coalescednodes+char(v);
|
|
alias[v]:=u;
|
|
|
|
{Combine both movelists. Since the movelists are sets, only add
|
|
elements that are not already present.}
|
|
if assigned(movelist[v]) then
|
|
begin
|
|
for n:=0 to movelist[v]^.count-1 do
|
|
begin
|
|
add:=true;
|
|
for o:=0 to movelist[u]^.count-1 do
|
|
if movelist[u]^.data[o]=movelist[v]^.data[n] then
|
|
begin
|
|
add:=false;
|
|
break;
|
|
end;
|
|
if add then
|
|
add_to_movelist(u,movelist[v]^.data[n]);
|
|
end;
|
|
enable_moves(v);
|
|
end;
|
|
|
|
adj:=igraph.adjlist[v];
|
|
if adj<>nil then
|
|
for i:=1 to length(adj^) do
|
|
begin
|
|
t:=adj^[i];
|
|
if (pos(t,selectstack) or pos(t,coalescednodes))=0 then
|
|
begin
|
|
decrement:=(Tsuperregister(t)<>u) and not(u in igraph.bitmap[Tsuperregister(t)]);
|
|
add_edge(Tsuperregister(t),u);
|
|
{Do not call decrement_degree because it might move nodes between
|
|
lists while the degree does not change (add_edge will increase it).
|
|
Instead, we will decrement manually. (Only if the degree has been
|
|
increased.)}
|
|
if decrement and not (Tsuperregister(t) in [first_int_supreg..last_int_supreg])
|
|
and (degree[Tsuperregister(t)]>0) then
|
|
dec(degree[Tsuperregister(t)]);
|
|
end;
|
|
end;
|
|
p:=pos(char(u),freezeworklist);
|
|
if (degree[u]>=cpu_registers) and (p<>0) then
|
|
begin
|
|
delete(freezeworklist,p,1);
|
|
spillworklist:=spillworklist+char(u);
|
|
end;
|
|
end;
|
|
|
|
procedure trgobj.coalesce;
|
|
|
|
var m:Tmoveins;
|
|
x,y,u,v:Tsuperregister;
|
|
|
|
begin
|
|
m:=Tmoveins(worklist_moves.getfirst);
|
|
x:=get_alias(getsupreg(m.instruction.oper[0].reg));
|
|
y:=get_alias(getsupreg(m.instruction.oper[1].reg));
|
|
if y in [first_int_supreg..last_int_supreg] then
|
|
begin
|
|
u:=y;
|
|
v:=x;
|
|
end
|
|
else
|
|
begin
|
|
u:=x;
|
|
v:=y;
|
|
end;
|
|
if (u=v) then
|
|
begin
|
|
m.moveset:=ms_coalesced_moves; {Already coalesced.}
|
|
coalesced_moves.insert(m);
|
|
add_worklist(u);
|
|
end
|
|
{Do u and v interfere? In that case the move is constrained. Two
|
|
precoloured nodes interfere allways. If v is precoloured, by the above
|
|
code u is precoloured, thus interference...}
|
|
else if (v in [first_int_supreg..last_int_supreg]) or (u in igraph.bitmap[v]) then
|
|
begin
|
|
m.moveset:=ms_constrained_moves; {Cannot coalesce yet...}
|
|
constrained_moves.insert(m);
|
|
add_worklist(u);
|
|
add_worklist(v);
|
|
end
|
|
{Next test: is it possible and a good idea to coalesce??}
|
|
else if ((u in [first_int_supreg..last_int_supreg]) and adjacent_ok(u,v)) or
|
|
(not(u in [first_int_supreg..last_int_supreg]) and conservative(u,v)) then
|
|
begin
|
|
m.moveset:=ms_coalesced_moves; {Move coalesced!}
|
|
coalesced_moves.insert(m);
|
|
combine(u,v);
|
|
add_worklist(u);
|
|
end
|
|
else
|
|
begin
|
|
m.moveset:=ms_active_moves;
|
|
active_moves.insert(m);
|
|
end;
|
|
end;
|
|
|
|
procedure trgobj.freeze_moves(u:Tsuperregister);
|
|
|
|
var i:cardinal;
|
|
m:Tlinkedlistitem;
|
|
v,x,y:Tsuperregister;
|
|
|
|
begin
|
|
if movelist[u]<>nil then
|
|
for i:=0 to movelist[u]^.count-1 do
|
|
begin
|
|
m:=movelist[u]^.data[i];
|
|
if Tmoveins(m).moveset in [ms_worklist_moves,ms_active_moves] then
|
|
begin
|
|
x:=getsupreg(Tmoveins(m).instruction.oper[0].reg);
|
|
y:=getsupreg(Tmoveins(m).instruction.oper[1].reg);
|
|
if get_alias(y)=get_alias(u) then
|
|
v:=get_alias(x)
|
|
else
|
|
v:=get_alias(y);
|
|
{Move m from active_moves/worklist_moves to frozen_moves.}
|
|
if Tmoveins(m).moveset=ms_active_moves then
|
|
active_moves.remove(m)
|
|
else
|
|
worklist_moves.remove(m);
|
|
Tmoveins(m).moveset:=ms_frozen_moves;
|
|
frozen_moves.insert(m);
|
|
|
|
if not(v in [first_int_supreg..last_int_supreg]) and
|
|
not(move_related(v)) and
|
|
(degree[v]<cpu_registers) then
|
|
begin
|
|
delete(freezeworklist,pos(char(v),freezeworklist),1);
|
|
simplifyworklist:=simplifyworklist+char(v);
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
procedure trgobj.freeze;
|
|
|
|
var n:Tsuperregister;
|
|
|
|
begin
|
|
{We need to take a random element out of the freezeworklist. We take
|
|
the last element. Dirty code!}
|
|
n:=Tsuperregister(freezeworklist[byte(freezeworklist[0])]);
|
|
dec(freezeworklist[0]);
|
|
{Add it to the simplifyworklist.}
|
|
simplifyworklist:=simplifyworklist+char(n);
|
|
freeze_moves(n);
|
|
end;
|
|
|
|
procedure trgobj.select_spill;
|
|
|
|
var n:char;
|
|
|
|
begin
|
|
{This code is WAY too naive. We need not to select just a register, but
|
|
the register that is used the least...}
|
|
n:=spillworklist[byte(spillworklist[0])];
|
|
dec(spillworklist[0]);
|
|
simplifyworklist:=simplifyworklist+n;
|
|
freeze_moves(Tsuperregister(n));
|
|
end;
|
|
|
|
procedure trgobj.assign_colours;
|
|
|
|
{Assign_colours assigns the actual colours to the registers.}
|
|
|
|
var adj:Pstring;
|
|
i,j,k:byte;
|
|
n,a,c:Tsuperregister;
|
|
adj_colours,colourednodes:set of Tsuperregister;
|
|
w:char;
|
|
|
|
begin
|
|
spillednodes:='';
|
|
{Reset colours}
|
|
for i:=0 to maxreg do
|
|
colour[i]:=i;
|
|
{Colour the cpu registers...}
|
|
colourednodes:=[first_int_supreg..last_int_supreg];
|
|
{Now colour the imaginary registers on the select-stack.}
|
|
for i:=length(selectstack) downto 1 do
|
|
begin
|
|
n:=Tsuperregister(selectstack[i]);
|
|
{Create a list of colours that we cannot assign to n.}
|
|
adj_colours:=[];
|
|
adj:=igraph.adjlist[n];
|
|
if adj<>nil then
|
|
for j:=1 to length(adj^) do
|
|
begin
|
|
w:=adj^[j];
|
|
a:=get_alias(Tsuperregister(w));
|
|
if a in colourednodes then
|
|
include(adj_colours,colour[a]);
|
|
end;
|
|
include(adj_colours,RS_STACK_POINTER_REG);
|
|
{Assume a spill by default...}
|
|
spillednodes:=spillednodes+char(n);
|
|
{Search for a colour not in this list.}
|
|
for k:=1 to length(usable_registers) do
|
|
begin
|
|
c:=Tsuperregister(usable_registers[k]);
|
|
if not(c in adj_colours) then
|
|
begin
|
|
colour[n]:=c;
|
|
dec(spillednodes[0]); {Colour found: no spill.}
|
|
include(colourednodes,n);
|
|
if n in used_in_proc then
|
|
include(used_in_proc,c);
|
|
break;
|
|
end;
|
|
end;
|
|
end;
|
|
{Finally colour the nodes that were coalesced.}
|
|
for i:=1 to length(coalescednodes) do
|
|
begin
|
|
n:=Tsuperregister(coalescednodes[i]);
|
|
k:=get_alias(n);
|
|
colour[n]:=colour[k];
|
|
if n in used_in_proc then
|
|
include(used_in_proc,colour[k]);
|
|
end;
|
|
{$ifdef ra_debug}
|
|
if aktfilepos.line=2502 then
|
|
begin
|
|
writeln('colourlist ',length(freezeworklist));
|
|
for i:=0 to maxintreg do
|
|
writeln(i:4,' ',colour[i]:4)
|
|
end;
|
|
{$endif ra_debug}
|
|
end;
|
|
|
|
procedure trgobj.colour_registers;
|
|
|
|
begin
|
|
repeat
|
|
if length(simplifyworklist)<>0 then
|
|
simplify
|
|
else if not(worklist_moves.empty) then
|
|
coalesce
|
|
else if length(freezeworklist)<>0 then
|
|
freeze
|
|
else if length(spillworklist)<>0 then
|
|
select_spill;
|
|
until (length(simplifyworklist)=0) and
|
|
worklist_moves.empty and
|
|
(length(freezeworklist)=0) and
|
|
(length(spillworklist)=0);
|
|
assign_colours;
|
|
end;
|
|
|
|
procedure trgobj.epilogue_colouring;
|
|
|
|
{
|
|
procedure move_to_worklist_moves(list:Tlinkedlist);
|
|
|
|
var p:Tlinkedlistitem;
|
|
|
|
begin
|
|
p:=list.first;
|
|
while p<>nil do
|
|
begin
|
|
Tmoveins(p).moveset:=ms_worklist_moves;
|
|
p:=p.next;
|
|
end;
|
|
worklist_moves.concatlist(list);
|
|
end;
|
|
}
|
|
|
|
var i:Tsuperregister;
|
|
|
|
begin
|
|
worklist_moves.clear;
|
|
{$ifdef Principle_wrong_by_definition}
|
|
{Move everything back to worklist_moves.}
|
|
move_to_worklist_moves(active_moves);
|
|
move_to_worklist_moves(frozen_moves);
|
|
move_to_worklist_moves(coalesced_moves);
|
|
move_to_worklist_moves(constrained_moves);
|
|
{$endif Principle_wrong_by_definition}
|
|
active_moves.destroy;
|
|
active_moves:=nil;
|
|
frozen_moves.destroy;
|
|
frozen_moves:=nil;
|
|
coalesced_moves.destroy;
|
|
coalesced_moves:=nil;
|
|
constrained_moves.destroy;
|
|
constrained_moves:=nil;
|
|
for i:=0 to 255 do
|
|
if movelist[i]<>nil then
|
|
begin
|
|
dispose(movelist[i]);
|
|
movelist[i]:=0;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure trgobj.clear_interferences(u:Tsuperregister);
|
|
|
|
{Remove node u from the interference graph and remove all collected
|
|
move instructions it is associated with.}
|
|
|
|
var i:byte;
|
|
j,k,count:cardinal;
|
|
v:Tsuperregister;
|
|
m,n:Tmoveins;
|
|
|
|
begin
|
|
if igraph.adjlist[u]<>nil then
|
|
begin
|
|
for i:=1 to length(igraph.adjlist[u]^) do
|
|
begin
|
|
v:=Tsuperregister(igraph.adjlist[u]^[i]);
|
|
{Remove (u,v) and (v,u) from bitmap.}
|
|
exclude(igraph.bitmap[u],v);
|
|
exclude(igraph.bitmap[v],u);
|
|
{Remove (v,u) from adjacency list.}
|
|
if igraph.adjlist[v]<>nil then
|
|
begin
|
|
delete(igraph.adjlist[v]^,pos(char(v),igraph.adjlist[v]^),1);
|
|
if length(igraph.adjlist[v]^)=0 then
|
|
begin
|
|
dispose(igraph.adjlist[v]);
|
|
igraph.adjlist[v]:=nil;
|
|
end;
|
|
end;
|
|
end;
|
|
{Remove ( u,* ) from adjacency list.}
|
|
dispose(igraph.adjlist[u]);
|
|
igraph.adjlist[u]:=nil;
|
|
end;
|
|
{$ifdef Principle_wrong_by_definition}
|
|
{Now remove the moves.}
|
|
if movelist[u]<>nil then
|
|
begin
|
|
for j:=0 to movelist[u]^.count-1 do
|
|
begin
|
|
m:=Tmoveins(movelist[u]^.data[j]);
|
|
{Get the other register of the move instruction.}
|
|
v:=m.instruction.oper[0].reg.number shr 8;
|
|
if v=u then
|
|
v:=m.instruction.oper[1].reg.number shr 8;
|
|
repeat
|
|
repeat
|
|
if (u<>v) and (movelist[v]<>nil) then
|
|
begin
|
|
{Remove the move from it's movelist.}
|
|
count:=movelist[v]^.count-1;
|
|
for k:=0 to count do
|
|
if m=movelist[v]^.data[k] then
|
|
begin
|
|
if k<>count then
|
|
movelist[v]^.data[k]:=movelist[v]^.data[count];
|
|
dec(movelist[v]^.count);
|
|
if count=0 then
|
|
begin
|
|
dispose(movelist[v]);
|
|
movelist[v]:=nil;
|
|
end;
|
|
break;
|
|
end;
|
|
end;
|
|
{The complexity is enourmous: the register might have been
|
|
coalesced. In that case it's movelists have been added to
|
|
it's coalescing alias. (DM)}
|
|
v:=alias[v];
|
|
until v=0;
|
|
{And also register u might have been coalesced.}
|
|
u:=alias[u];
|
|
until u=0;
|
|
|
|
case m.moveset of
|
|
ms_coalesced_moves:
|
|
coalesced_moves.remove(m);
|
|
ms_constrained_moves:
|
|
constrained_moves.remove(m);
|
|
ms_frozen_moves:
|
|
frozen_moves.remove(m);
|
|
ms_worklist_moves:
|
|
worklist_moves.remove(m);
|
|
ms_active_moves:
|
|
active_moves.remove(m);
|
|
end;
|
|
end;
|
|
dispose(movelist[u]);
|
|
movelist[u]:=nil;
|
|
end;
|
|
{$endif Principle_wrong_by_definition}
|
|
end;
|
|
|
|
procedure trgobj.getregisterinline(list:Taasmoutput;
|
|
position:Tai;subreg:Tsubregister;var result:Tregister);
|
|
var min,p,i:Tsuperregister;
|
|
r:Tregister;
|
|
adj:Pstring;
|
|
begin
|
|
if maxreg<last_reg then
|
|
begin
|
|
inc(maxreg);
|
|
p:=maxreg;
|
|
min:=0;
|
|
end
|
|
else
|
|
begin
|
|
min:=$ff;
|
|
p:=first_imaginary;
|
|
for i:=first_imaginary to maxreg do
|
|
if (i in unusedregs) and
|
|
(pos(char(i),abtlist)=0) and
|
|
(pos(char(i),spillednodes)=0) then
|
|
begin
|
|
adj:=igraph.adjlist[Tsuperregister(i)];
|
|
if adj=nil then
|
|
begin
|
|
p:=i;
|
|
min:=0;
|
|
break; {We won't find smaller ones.}
|
|
end
|
|
else
|
|
if length(adj^)<min then
|
|
begin
|
|
p:=i;
|
|
min:=length(adj^);
|
|
if min=0 then
|
|
break; {We won't find smaller ones.}
|
|
end;
|
|
end;
|
|
|
|
if min=$ff then
|
|
begin
|
|
{$ifdef ALLOWDUPREG}
|
|
result:=newreg(regtype,RS_INVALID,subreg);
|
|
exit;
|
|
{$else}
|
|
internalerror(10);
|
|
{$endif}
|
|
end;
|
|
end;
|
|
|
|
{$ifdef ra_debug}
|
|
writeln('Spilling temp: ',p,' min ',min);
|
|
{$endif ra_debug}
|
|
|
|
exclude(unusedregs,p);
|
|
include(used_in_proc,p);
|
|
r:=newreg(regtype,p,subreg);
|
|
if position=nil then
|
|
list.insert(Tai_regalloc.alloc(r))
|
|
else
|
|
list.insertafter(Tai_regalloc.alloc(r),position);
|
|
add_edges_used(p);
|
|
add_constraints(r);
|
|
result:=r;
|
|
end;
|
|
|
|
|
|
{In some cases we can get in big trouble. See this example:
|
|
|
|
; register reg23d released
|
|
; register eax allocated
|
|
; register ebx allocated
|
|
; register ecx allocated
|
|
; register edx allocated
|
|
; register esi allocated
|
|
; register edi allocated
|
|
call [reg23d]
|
|
|
|
This code is ok, *except* when reg23d is spilled. In that case the
|
|
spilled would introduce a help register which can never get
|
|
allocated to a real register because it interferes with all of them.
|
|
|
|
To solve this we introduce the ABT ("avoid big trouble :)" ) registers.
|
|
|
|
If you allocate an ABT register you get a register that has less
|
|
than cpu_register interferences and will not be allocated ever again
|
|
by the normal register get procedures. In other words it is for sure it
|
|
will never get spilled.}
|
|
|
|
function trgobj.getabtregister(list:Taasmoutput;subreg:tsubregister):Tregister;
|
|
|
|
var p,i:Tsuperregister;
|
|
r:Tregister;
|
|
found:boolean;
|
|
min : byte;
|
|
adj:Pstring;
|
|
|
|
begin
|
|
min:=$ff;
|
|
for i:=1 to length(abtlist) do
|
|
if Tsuperregister(abtlist[i]) in unusedregs then
|
|
begin
|
|
p:=tsuperregister(abtlist[i]);
|
|
min:=0;
|
|
break;
|
|
end;
|
|
|
|
if min>0 then
|
|
begin
|
|
if maxreg<last_reg then
|
|
begin
|
|
inc(maxreg);
|
|
p:=maxreg;
|
|
min:=0;
|
|
end
|
|
else
|
|
begin
|
|
p:=first_imaginary;
|
|
for i:=first_imaginary to maxreg do
|
|
if (i in unusedregs) and
|
|
((igraph.adjlist[i]=nil) or
|
|
(length(igraph.adjlist[i]^)<cpu_registers)) then
|
|
begin
|
|
adj:=igraph.adjlist[i];
|
|
if adj=nil then
|
|
begin
|
|
p:=i;
|
|
min:=0;
|
|
break; {We won't find smaller ones.}
|
|
end
|
|
else
|
|
if length(adj^)<min then
|
|
begin
|
|
p:=i;
|
|
min:=length(adj^);
|
|
if min=0 then
|
|
break; {We won't find smaller ones.}
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
if min=$ff then
|
|
begin
|
|
{$ifdef ALLOWDUPREG}
|
|
result:=newreg(regtype,RS_INVALID,cgsize2subreg(size));
|
|
exit;
|
|
{$else}
|
|
internalerror(10);
|
|
{$endif}
|
|
end;
|
|
end;
|
|
|
|
exclude(unusedregs,p);
|
|
include(used_in_proc,p);
|
|
r:=newreg(regtype,p,subreg);
|
|
list.concat(Tai_regalloc.alloc(r));
|
|
result:=r;
|
|
add_edges_used(p);
|
|
add_constraints(r);
|
|
if pos(char(p),abtlist)=0 then
|
|
abtlist:=abtlist+char(p);
|
|
end;
|
|
|
|
|
|
procedure trgobj.ungetregisterinline(list:Taasmoutput;
|
|
position:Tai;r:Tregister);
|
|
|
|
var supreg:Tsuperregister;
|
|
|
|
begin
|
|
supreg:=getsupreg(r);
|
|
include(unusedregs,supreg);
|
|
if position=nil then
|
|
list.insert(Tai_regalloc.dealloc(r))
|
|
else
|
|
list.insertafter(Tai_regalloc.dealloc(r),position);
|
|
add_edges_used(supreg);
|
|
add_constraints(r);
|
|
end;
|
|
|
|
function trgobj.spill_registers(list:Taasmoutput;headertai:tai;const regs_to_spill:string):boolean;
|
|
|
|
{Returns true if any help registers have been used.}
|
|
|
|
var i:byte;
|
|
p,q:Tai;
|
|
regs_to_spill_set:Tsuperregisterset;
|
|
spill_temps:^Tspill_temp_list;
|
|
supreg : tsuperregister;
|
|
templist : taasmoutput;
|
|
begin
|
|
spill_registers:=false;
|
|
unusedregs:=[first_reg..last_reg];
|
|
fillchar(degree,sizeof(degree),0);
|
|
{Precoloured nodes should have an infinite degree, which we can approach
|
|
by 255.}
|
|
for i:=first_int_supreg to last_int_supreg do
|
|
degree[i]:=255;
|
|
{ exclude(unusedregs,RS_STACK_POINTER_REG);}
|
|
if current_procinfo.framepointer=NR_FRAME_POINTER_REG then
|
|
{Make sure the register allocator won't allocate registers into ebp.}
|
|
exclude(unusedregs,RS_FRAME_POINTER_REG);
|
|
new(spill_temps);
|
|
fillchar(spill_temps^,sizeof(spill_temps^),0);
|
|
regs_to_spill_set:=[];
|
|
{ Allocate temps and insert in front of the list }
|
|
templist:=taasmoutput.create;
|
|
for i:=1 to length(regs_to_spill) do
|
|
begin
|
|
{Alternative representation.}
|
|
include(regs_to_spill_set,Tsuperregister(regs_to_spill[i]));
|
|
{Clear all interferences of the spilled register.}
|
|
clear_interferences(Tsuperregister(regs_to_spill[i]));
|
|
{Get a temp for the spilled register}
|
|
tg.gettemp(templist,4,tt_noreuse,spill_temps^[Tsuperregister(regs_to_spill[i])]);
|
|
end;
|
|
list.insertlistafter(headertai,templist);
|
|
templist.free;
|
|
{ Walk through all instructions, we can start with the headertai,
|
|
because before the header tai is only symbols }
|
|
p:=headertai;
|
|
while assigned(p) do
|
|
begin
|
|
case p.typ of
|
|
ait_regalloc:
|
|
begin
|
|
{A register allocation of a spilled register can be removed.}
|
|
supreg:=getsupreg(Tai_regalloc(p).reg);
|
|
if supreg in regs_to_spill_set then
|
|
begin
|
|
q:=p;
|
|
p:=Tai(p.next);
|
|
list.remove(q);
|
|
continue;
|
|
end
|
|
else
|
|
if Tai_regalloc(p).allocation then
|
|
exclude(unusedregs,supreg)
|
|
else
|
|
include(unusedregs,supreg);
|
|
end;
|
|
ait_instruction:
|
|
begin
|
|
aktfilepos:=Taicpu_abstract(p).fileinfo;
|
|
if Taicpu_abstract(p).spill_registers(list,@getregisterinline,
|
|
@ungetregisterinline,
|
|
regs_to_spill_set,
|
|
unusedregs,
|
|
spill_temps^) then
|
|
spill_registers:=true;
|
|
if Taicpu_abstract(p).is_move then
|
|
add_move_instruction(Taicpu(p));
|
|
end;
|
|
end;
|
|
p:=Tai(p.next);
|
|
end;
|
|
aktfilepos:=current_procinfo.exitpos;
|
|
for i:=1 to length(regs_to_spill) do
|
|
tg.ungettemp(list,spill_temps^[Tsuperregister(regs_to_spill[i])]);
|
|
dispose(spill_temps);
|
|
end;
|
|
|
|
end.
|
|
|
|
{
|
|
$Log$
|
|
Revision 1.84 2003-10-11 16:06:42 florian
|
|
* fixed some MMX<->SSE
|
|
* started to fix ppc, needs an overhaul
|
|
+ stabs info improve for spilling, not sure if it works correctly/completly
|
|
- MMX_SUPPORT removed from Makefile.fpc
|
|
|
|
Revision 1.83 2003/10/10 17:48:14 peter
|
|
* old trgobj moved to x86/rgcpu and renamed to trgx86fpu
|
|
* tregisteralloctor renamed to trgobj
|
|
* removed rgobj from a lot of units
|
|
* moved location_* and reference_* to cgobj
|
|
* first things for mmx register allocation
|
|
|
|
Revision 1.82 2003/10/09 21:31:37 daniel
|
|
* Register allocator splitted, ans abstract now
|
|
|
|
Revision 1.81 2003/10/01 20:34:49 peter
|
|
* procinfo unit contains tprocinfo
|
|
* cginfo renamed to cgbase
|
|
* moved cgmessage to verbose
|
|
* fixed ppc and sparc compiles
|
|
|
|
Revision 1.80 2003/09/30 19:54:42 peter
|
|
* reuse registers with the least conflicts
|
|
|
|
Revision 1.79 2003/09/29 20:58:56 peter
|
|
* optimized releasing of registers
|
|
|
|
Revision 1.78 2003/09/28 13:41:12 peter
|
|
* return reg 255 when allowdupreg is defined
|
|
|
|
Revision 1.77 2003/09/25 16:19:32 peter
|
|
* fix filepositions
|
|
* insert spill temp allocations at the start of the proc
|
|
|
|
Revision 1.76 2003/09/16 16:17:01 peter
|
|
* varspez in calls to push_addr_param
|
|
|
|
Revision 1.75 2003/09/12 19:07:42 daniel
|
|
* Fixed fast spilling functionality by re-adding the code that initializes
|
|
precoloured nodes to degree 255. I would like to play hangman on the one
|
|
who removed that code.
|
|
|
|
Revision 1.74 2003/09/11 11:54:59 florian
|
|
* improved arm code generation
|
|
* move some protected and private field around
|
|
* the temp. register for register parameters/arguments are now released
|
|
before the move to the parameter register is done. This improves
|
|
the code in a lot of cases.
|
|
|
|
Revision 1.73 2003/09/09 20:59:27 daniel
|
|
* Adding register allocation order
|
|
|
|
Revision 1.72 2003/09/09 15:55:44 peter
|
|
* use register with least interferences in spillregister
|
|
|
|
Revision 1.71 2003/09/07 22:09:35 peter
|
|
* preparations for different default calling conventions
|
|
* various RA fixes
|
|
|
|
Revision 1.70 2003/09/03 21:06:45 peter
|
|
* fixes for FPU register allocation
|
|
|
|
Revision 1.69 2003/09/03 15:55:01 peter
|
|
* NEWRA branch merged
|
|
|
|
Revision 1.68 2003/09/03 11:18:37 florian
|
|
* fixed arm concatcopy
|
|
+ arm support in the common compiler sources added
|
|
* moved some generic cg code around
|
|
+ tfputype added
|
|
* ...
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Revision 1.67.2.5 2003/08/31 20:44:07 peter
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* fixed getexplicitregisterint tregister value
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Revision 1.67.2.4 2003/08/31 20:40:50 daniel
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* Fixed add_edges_used
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Revision 1.67.2.3 2003/08/29 17:28:59 peter
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* next batch of updates
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Revision 1.67.2.2 2003/08/28 18:35:08 peter
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* tregister changed to cardinal
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Revision 1.67.2.1 2003/08/27 19:55:54 peter
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* first tregister patch
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Revision 1.67 2003/08/23 10:46:21 daniel
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* Register allocator bugfix for h2pas
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Revision 1.66 2003/08/17 16:59:20 jonas
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* fixed regvars so they work with newra (at least for ppc)
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* fixed some volatile register bugs
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+ -dnotranslation option for -dnewra, which causes the registers not to
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be translated from virtual to normal registers. Requires support in
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the assembler writer as well, which is only implemented in aggas/
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agppcgas currently
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Revision 1.65 2003/08/17 14:32:48 daniel
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* Precoloured nodes now have an infinite degree approached with 255,
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like they should.
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Revision 1.64 2003/08/17 08:48:02 daniel
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* Another register allocator bug fixed.
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* cpu_registers set to 6 for i386
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Revision 1.63 2003/08/09 18:56:54 daniel
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* cs_regalloc renamed to cs_regvars to avoid confusion with register
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allocator
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* Some preventive changes to i386 spillinh code
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Revision 1.62 2003/08/03 14:09:50 daniel
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* Fixed a register allocator bug
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* Figured out why -dnewra generates superfluous "mov reg1,reg2"
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statements: changes in location_force. These moves are now no longer
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constrained so they are optimized away.
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Revision 1.61 2003/07/21 13:32:39 jonas
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* add_edges_used() is now also called for registers allocated with
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getexplicitregisterint()
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* writing the intereference graph is now only done with -dradebug2 and
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the created files are now called "igraph.<module_name>"
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Revision 1.60 2003/07/06 15:31:21 daniel
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* Fixed register allocator. *Lots* of fixes.
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Revision 1.59 2003/07/06 15:00:47 jonas
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* fixed my previous completely broken commit. It's not perfect though,
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registers > last_int_supreg and < max_intreg may still be "translated"
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Revision 1.58 2003/07/06 14:45:05 jonas
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* support integer registers that are not managed by newra (ie. don't
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translate register numbers that fall outside the range
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first_int_supreg..last_int_supreg)
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Revision 1.57 2003/07/02 22:18:04 peter
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* paraloc splitted in callerparaloc,calleeparaloc
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* sparc calling convention updates
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Revision 1.56 2003/06/17 16:34:44 jonas
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* lots of newra fixes (need getfuncretparaloc implementation for i386)!
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* renamed all_intregisters to volatile_intregisters and made it
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processor dependent
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Revision 1.55 2003/06/14 14:53:50 jonas
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* fixed newra cycle for x86
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* added constants for indicating source and destination operands of the
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"move reg,reg" instruction to aasmcpu (and use those in rgobj)
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Revision 1.54 2003/06/13 21:19:31 peter
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* current_procdef removed, use current_procinfo.procdef instead
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Revision 1.53 2003/06/12 21:11:10 peter
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* ungetregisterfpu gets size parameter
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Revision 1.52 2003/06/12 16:43:07 peter
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* newra compiles for sparc
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Revision 1.51 2003/06/09 14:54:26 jonas
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* (de)allocation of registers for parameters is now performed properly
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(and checked on the ppc)
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- removed obsolete allocation of all parameter registers at the start
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of a procedure (and deallocation at the end)
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Revision 1.50 2003/06/03 21:11:09 peter
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* cg.a_load_* get a from and to size specifier
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* makeregsize only accepts newregister
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* i386 uses generic tcgnotnode,tcgunaryminus
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Revision 1.49 2003/06/03 13:01:59 daniel
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* Register allocator finished
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Revision 1.48 2003/06/01 21:38:06 peter
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* getregisterfpu size parameter added
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* op_const_reg size parameter added
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* sparc updates
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Revision 1.47 2003/05/31 20:31:11 jonas
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* set inital costs of assigning a variable to a register to 120 for
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non-i386, because the used register must be store to memory at the
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start and loaded again at the end
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Revision 1.46 2003/05/30 18:55:21 jonas
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* fixed several regvar related bugs for non-i386. make cycle with -Or now
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works for ppc
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Revision 1.45 2003/05/30 12:36:13 jonas
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* use as little different registers on the ppc until newra is released,
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since every used register must be saved
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Revision 1.44 2003/05/17 13:30:08 jonas
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* changed tt_persistant to tt_persistent :)
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* tempcreatenode now doesn't accept a boolean anymore for persistent
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temps, but a ttemptype, so you can also create ansistring temps etc
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Revision 1.43 2003/05/16 14:33:31 peter
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* regvar fixes
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Revision 1.42 2003/04/26 20:03:49 daniel
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* Bug fix in simplify
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Revision 1.41 2003/04/25 20:59:35 peter
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* removed funcretn,funcretsym, function result is now in varsym
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and aliases for result and function name are added using absolutesym
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* vs_hidden parameter for funcret passed in parameter
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* vs_hidden fixes
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* writenode changed to printnode and released from extdebug
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* -vp option added to generate a tree.log with the nodetree
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* nicer printnode for statements, callnode
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Revision 1.40 2003/04/25 08:25:26 daniel
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* Ifdefs around a lot of calls to cleartempgen
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* Fixed registers that are allocated but not freed in several nodes
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* Tweak to register allocator to cause less spills
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* 8-bit registers now interfere with esi,edi and ebp
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Compiler can now compile rtl successfully when using new register
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allocator
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Revision 1.39 2003/04/23 20:23:06 peter
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* compile fix for no-newra
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Revision 1.38 2003/04/23 14:42:07 daniel
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* Further register allocator work. Compiler now smaller with new
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allocator than without.
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* Somebody forgot to adjust ppu version number
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Revision 1.37 2003/04/22 23:50:23 peter
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* firstpass uses expectloc
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* checks if there are differences between the expectloc and
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location.loc from secondpass in EXTDEBUG
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Revision 1.36 2003/04/22 10:09:35 daniel
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+ Implemented the actual register allocator
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+ Scratch registers unavailable when new register allocator used
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+ maybe_save/maybe_restore unavailable when new register allocator used
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Revision 1.35 2003/04/21 19:16:49 peter
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* count address regs separate
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Revision 1.34 2003/04/17 16:48:21 daniel
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* Added some code to keep track of move instructions in register
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allocator
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Revision 1.33 2003/04/17 07:50:24 daniel
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* Some work on interference graph construction
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Revision 1.32 2003/03/28 19:16:57 peter
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* generic constructor working for i386
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* remove fixed self register
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* esi added as address register for i386
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Revision 1.31 2003/03/11 21:46:24 jonas
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* lots of new regallocator fixes, both in generic and ppc-specific code
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(ppc compiler still can't compile the linux system unit though)
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Revision 1.30 2003/03/09 21:18:59 olle
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+ added cutils to the uses clause
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Revision 1.29 2003/03/08 20:36:41 daniel
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+ Added newra version of Ti386shlshrnode
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+ Added interference graph construction code
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Revision 1.28 2003/03/08 13:59:16 daniel
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* Work to handle new register notation in ag386nsm
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+ Added newra version of Ti386moddivnode
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Revision 1.27 2003/03/08 10:53:48 daniel
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* Created newra version of secondmul in n386add.pas
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Revision 1.26 2003/03/08 08:59:07 daniel
|
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+ $define newra will enable new register allocator
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+ getregisterint will return imaginary registers with $newra
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+ -sr switch added, will skip register allocation so you can see
|
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the direct output of the code generator before register allocation
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Revision 1.25 2003/02/26 20:50:45 daniel
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* Fixed ungetreference
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Revision 1.24 2003/02/19 22:39:56 daniel
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* Fixed a few issues
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Revision 1.23 2003/02/19 22:00:14 daniel
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* Code generator converted to new register notation
|
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- Horribily outdated todo.txt removed
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Revision 1.22 2003/02/02 19:25:54 carl
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* Several bugfixes for m68k target (register alloc., opcode emission)
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+ VIS target
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+ Generic add more complete (still not verified)
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Revision 1.21 2003/01/08 18:43:57 daniel
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* Tregister changed into a record
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Revision 1.20 2002/10/05 12:43:28 carl
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* fixes for Delphi 6 compilation
|
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(warning : Some features do not work under Delphi)
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Revision 1.19 2002/08/23 16:14:49 peter
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* tempgen cleanup
|
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* tt_noreuse temp type added that will be used in genentrycode
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Revision 1.18 2002/08/17 22:09:47 florian
|
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* result type handling in tcgcal.pass_2 overhauled
|
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* better tnode.dowrite
|
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* some ppc stuff fixed
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Revision 1.17 2002/08/17 09:23:42 florian
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* first part of procinfo rewrite
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Revision 1.16 2002/08/06 20:55:23 florian
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* first part of ppc calling conventions fix
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Revision 1.15 2002/08/05 18:27:48 carl
|
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+ more more more documentation
|
|
+ first version include/exclude (can't test though, not enough scratch for i386 :()...
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Revision 1.14 2002/08/04 19:06:41 carl
|
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+ added generic exception support (still does not work!)
|
|
+ more documentation
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Revision 1.13 2002/07/07 09:52:32 florian
|
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* powerpc target fixed, very simple units can be compiled
|
|
* some basic stuff for better callparanode handling, far from being finished
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Revision 1.12 2002/07/01 18:46:26 peter
|
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* internal linker
|
|
* reorganized aasm layer
|
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Revision 1.11 2002/05/18 13:34:17 peter
|
|
* readded missing revisions
|
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|
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Revision 1.10 2002/05/16 19:46:44 carl
|
|
+ defines.inc -> fpcdefs.inc to avoid conflicts if compiling by hand
|
|
+ try to fix temp allocation (still in ifdef)
|
|
+ generic constructor calls
|
|
+ start of tassembler / tmodulebase class cleanup
|
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|
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Revision 1.8 2002/04/21 15:23:03 carl
|
|
+ makeregsize
|
|
+ changeregsize is now a local routine
|
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|
Revision 1.7 2002/04/20 21:32:25 carl
|
|
+ generic FPC_CHECKPOINTER
|
|
+ first parameter offset in stack now portable
|
|
* rename some constants
|
|
+ move some cpu stuff to other units
|
|
- remove unused constents
|
|
* fix stacksize for some targets
|
|
* fix generic size problems which depend now on EXTEND_SIZE constant
|
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|
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Revision 1.6 2002/04/15 19:03:31 carl
|
|
+ reg2str -> std_reg2str()
|
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|
Revision 1.5 2002/04/06 18:13:01 jonas
|
|
* several powerpc-related additions and fixes
|
|
|
|
Revision 1.4 2002/04/04 19:06:04 peter
|
|
* removed unused units
|
|
* use tlocation.size in cg.a_*loc*() routines
|
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Revision 1.3 2002/04/02 17:11:29 peter
|
|
* tlocation,treference update
|
|
* LOC_CONSTANT added for better constant handling
|
|
* secondadd splitted in multiple routines
|
|
* location_force_reg added for loading a location to a register
|
|
of a specified size
|
|
* secondassignment parses now first the right and then the left node
|
|
(this is compatible with Kylix). This saves a lot of push/pop especially
|
|
with string operations
|
|
* adapted some routines to use the new cg methods
|
|
|
|
Revision 1.2 2002/04/01 19:24:25 jonas
|
|
* fixed different parameter name in interface and implementation
|
|
declaration of a method (only 1.0.x detected this)
|
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|
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Revision 1.1 2002/03/31 20:26:36 jonas
|
|
+ a_loadfpu_* and a_loadmm_* methods in tcg
|
|
* register allocation is now handled by a class and is mostly processor
|
|
independent (+rgobj.pas and i386/rgcpu.pas)
|
|
* temp allocation is now handled by a class (+tgobj.pas, -i386\tgcpu.pas)
|
|
* some small improvements and fixes to the optimizer
|
|
* some register allocation fixes
|
|
* some fpuvaroffset fixes in the unary minus node
|
|
* push/popusedregisters is now called rg.save/restoreusedregisters and
|
|
(for i386) uses temps instead of push/pop's when using -Op3 (that code is
|
|
also better optimizable)
|
|
* fixed and optimized register saving/restoring for new/dispose nodes
|
|
* LOC_FPU locations now also require their "register" field to be set to
|
|
R_ST, not R_ST0 (the latter is used for LOC_CFPUREGISTER locations only)
|
|
- list field removed of the tnode class because it's not used currently
|
|
and can cause hard-to-find bugs
|
|
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|
}
|