Jonas Maebe 122d0d36d6 + volatile() expression that marks an expression as volatile ... * disable matching volatile references in the assembler optimisers, so they can't be removed (more conservative than needed, but better than removing too many) o the CSE optimiser will ignore them by default, because they're an unknown inline node for it * also removed no longer used fpc_in_move_x and fpc_in_fillchar_x inline node identifiers from rtl/inc/innr.inc, and placed fpc_in_unaligned_x at the right place git-svn-id: trunk@40465 -		2018-12-04 19:53:20 +00:00
..
aasmcpu.pas	* patch by Christo Crause: more descriptive error message when BRxx destination out of reach	2018-02-25 15:31:17 +00:00
agavrgas.pas	* LDD/STD need always an offset, resolves #33086	2018-01-28 21:06:13 +00:00
aoptcpu.pas	+ volatile() expression that marks an expression as volatile	2018-12-04 19:53:20 +00:00
aoptcpub.pas	- get rid of MaxOps, it is redundant with max_operands	2018-11-02 21:32:29 +00:00
aoptcpud.pas
avrreg.dat	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ccpuinnr.inc	+ implemented some AVR specific intrinsics	2017-11-01 16:33:34 +00:00
cgcpu.pas	* converted Boolean8 to an internal type, and mapped Boolean to the	2018-10-16 21:14:18 +00:00
cpubase.pas	* max_operands needs only to be 2 on avr	2018-11-03 10:39:58 +00:00
cpuinfo.pas	* patch by Christo Crause: the subarch type for atmega 8, 8A, 16 & 32 was incorrect. Atmega8A was also listed under the wrong subarch type in the makefile, also fixed.	2018-02-18 10:54:59 +00:00
cpunode.pas	+ implemented some AVR specific intrinsics	2017-11-01 16:33:34 +00:00
cpupara.pas
cpupi.pas
cputarg.pas
hlcgcpu.pas
itcpugas.pas
navradd.pas	* GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved	2017-09-11 14:53:06 +00:00
navrcnv.pas
navrinl.pas	+ implemented some AVR specific intrinsics	2017-11-01 16:33:34 +00:00
navrmat.pas	* missing skiplabel added, resolves #33423	2018-03-13 18:45:32 +00:00
navrmem.pas	* use unique internalerror instead of copying that from ncgmem (though it should never happen that both occur at once in a AVR compiler)	2017-07-28 15:54:03 +00:00
navrutil.pas
raavr.pas	* max_operands needs only to be 2 on avr	2018-11-03 10:39:58 +00:00
raavrgas.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
ravrcon.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrdwa.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrnor.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrnum.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrrni.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrsri.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrsta.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrstd.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
ravrsup.inc	* keep the names of X, Y and Z in assembler files, fixes issue #32150	2017-07-23 19:24:45 +00:00
rgcpu.pas	* keep track of the temp position separately from the offset in references,	2018-04-22 17:03:16 +00:00
symcpu.pas