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0fc1fd6ac1
labels of LOC_JUMP in the node's location. This generates some extra jumps
for short circuit boolean and/or-expressions if optimizations are off, but
with optimisations enabled the generated code is the same (except for JVM
because the jump threading optimisation isn't enabled there yet).
git-svn-id: trunk@31431 -
550 lines
21 KiB
ObjectPascal
550 lines
21 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl and Jonas Maebe
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Code generation for add nodes on the Motorola 680x0 family
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n68kadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,nadd,ncgadd,cpubase,cgbase;
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type
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t68kaddnode = class(tcgaddnode)
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private
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function getresflags(unsigned: boolean) : tresflags;
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protected
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpordinal;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,symtype,
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aasmbase,aasmtai,aasmdata,aasmcpu,defutil,htypechk,
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cpuinfo,pass_1,pass_2,regvars,
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cpupara,cgutils,procinfo,
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ncon,nset,
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ncgutil,tgobj,rgobj,rgcpu,cgobj,cgcpu,hlcgobj,cg64f32;
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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function t68kaddnode.getresflags(unsigned : boolean) : tresflags;
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begin
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case nodetype of
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equaln : getresflags:=F_E;
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unequaln : getresflags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case nodetype of
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ltn : getresflags:=F_G;
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lten : getresflags:=F_GE;
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gtn : getresflags:=F_L;
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gten : getresflags:=F_LE;
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else
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internalerror(2014082030);
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end
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else
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case nodetype of
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ltn : getresflags:=F_L;
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lten : getresflags:=F_LE;
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gtn : getresflags:=F_G;
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gten : getresflags:=F_GE;
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else
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internalerror(2014082031);
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end;
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end
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else
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begin
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if nf_swapped in flags then
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case nodetype of
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ltn : getresflags:=F_A;
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lten : getresflags:=F_AE;
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gtn : getresflags:=F_B;
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gten : getresflags:=F_BE;
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else
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internalerror(2014082032);
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end
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else
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case nodetype of
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ltn : getresflags:=F_B;
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lten : getresflags:=F_BE;
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gtn : getresflags:=F_A;
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gten : getresflags:=F_AE;
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else
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internalerror(2014082033);
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end;
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end;
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end;
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end;
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{*****************************************************************************
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AddFloat
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*****************************************************************************}
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procedure t68kaddnode.second_addfloat;
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var
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op : TAsmOp;
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href : TReference;
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begin
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pass_left_right;
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case nodetype of
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addn :
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op:=A_FADD;
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muln :
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op:=A_FMUL;
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subn :
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op:=A_FSUB;
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slashn :
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op:=A_FDIV;
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else
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internalerror(200403182);
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end;
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// get the operands in the correct order, there are no special cases
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// here, everything is register-based
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if nf_swapped in flags then
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swapleftright;
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case current_settings.fputype of
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fpu_68881:
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begin
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{ have left in the register, right can be a memory location }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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{ initialize the result }
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register := cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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{ emit the actual operation }
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cg.a_loadfpu_reg_reg(current_asmdata.CurrAsmlist,OS_NO,OS_NO,left.location.register,location.register);
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case right.location.loc of
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,S_FX,right.location.register,location.register));
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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href:=right.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(op,tcgsize2opsize[right.location.size],href,location.register));
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end
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else
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internalerror(2015021501);
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end;
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end;
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else
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// softfpu should be handled in pass1, others are not yet supported...
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internalerror(2015010201);
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end;
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end;
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procedure t68kaddnode.second_cmpfloat;
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var
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tmpreg : tregister;
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ai: taicpu;
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href : TReference;
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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case current_settings.fputype of
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fpu_68881:
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begin
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{ force left fpureg as register, right can be reference }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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{ emit compare }
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case right.location.loc of
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LOC_FPUREGISTER,LOC_CFPUREGISTER:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FCMP,S_FX,right.location.register,left.location.register));
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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href:=right.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_FCMP,tcgsize2opsize[right.location.size],href,left.location.register));
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end
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else
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internalerror(2015021502);
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end;
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// temporary(?) hack, move condition result back to the CPU from the FPU.
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// 6888x has its own FBcc branch instructions and FScc flags->reg instruction,
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// which we don't support yet in the rest of the cg. (KB)
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_8);
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ai:=taicpu.op_reg(A_FSxx,S_B,tmpreg);
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ai.SetCondition(flags_to_cond(getresflags(false)));
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current_asmdata.CurrAsmList.concat(ai);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_NEG,S_B,tmpreg));
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location_reset(location,LOC_REGISTER,OS_8);
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location.register:=tmpreg;
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end;
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else
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// softfpu should be handled in pass1, others are not yet supported...
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internalerror(2015010201);
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end;
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end;
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{*****************************************************************************
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Smallsets
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*****************************************************************************}
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procedure t68kaddnode.second_cmpsmallset;
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var
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tmpreg : tregister;
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begin
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pass_left_right;
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location_reset(location,LOC_FLAGS,OS_NO);
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if (not(nf_swapped in flags) and
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(nodetype = lten)) or
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((nf_swapped in flags) and
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(nodetype = gten)) then
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swapleftright;
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{ Try to keep right as a constant }
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if right.location.loc<>LOC_CONSTANT then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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case nodetype of
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equaln,
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unequaln:
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begin
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if right.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,right.location.value,left.location.register))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register,left.location.register));
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if nodetype=equaln then
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location.resflags:=F_E
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else
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location.resflags:=F_NE;
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end;
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lten,
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gten:
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begin
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,left.location.size);
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if right.location.loc=LOC_CONSTANT then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_AND,OS_32,left.location.register,right.location.register,tmpreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,tmpreg,right.location.register));
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location.resflags:=F_E;
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end;
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else
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internalerror(2013092701);
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end;
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end;
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{*****************************************************************************
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Ordinals
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*****************************************************************************}
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procedure t68kaddnode.second_cmpordinal;
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var
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unsigned : boolean;
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tmpreg : tregister;
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opsize : topsize;
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cmpsize : tcgsize;
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href: treference;
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begin
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{ determine if the comparison will be unsigned }
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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{ this puts constant operand (if any) to the right }
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pass_left_right;
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{ tentatively assume left size (correct for possible TST, will fix later) }
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cmpsize:=def_cgsize(left.resultdef);
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opsize:=tcgsize2opsize[cmpsize];
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{ set result location }
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location_reset(location,LOC_FLAGS,OS_NO);
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{ see if we can optimize into TST }
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if (right.location.loc=LOC_CONSTANT) and (right.location.value=0) then
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begin
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{ Unsigned <0 or >=0 should not reach pass2, most likely }
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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href:=left.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_TST,opsize,href));
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location_freetemp(current_asmdata.CurrAsmList,left.location);
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end;
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else
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,opsize,left.location.register));
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end;
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location.resflags := getresflags(unsigned);
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exit;
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end;
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{ Coldfire supports byte/word compares only starting with ISA_B,
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!!see remark about Qemu weirdness in tcg68k.a_cmp_const_reg_label }
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if (opsize<>S_L) and (current_settings.cputype in cpu_coldfire{-[cpu_isa_b,cpu_isa_c]}) then
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begin
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{ 1) Extension is needed for LOC_REFERENCE, but what about LOC_REGISTER ? Perhaps after fixing cg we can assume
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that high bits of registers are correct.
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2) Assuming that extension depends only on source signedness --> destination OS_32 is acceptable. }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(OS_32),false);
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if (right.location.loc<>LOC_CONSTANT) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,cgsize_orddef(OS_32),false);
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opsize:=S_L;
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end
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else if not (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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begin
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if not (right.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true)
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else
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begin
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end;
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end;
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{ left is now in register }
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case right.location.loc of
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LOC_CONSTANT:
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,opsize,
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longint(right.location.value),left.location.register));
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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href:=right.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_CMP,opsize,href,
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left.location.register));
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end;
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LOC_REGISTER,
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LOC_CREGISTER:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,opsize,
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right.location.register,left.location.register));
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else
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,opsize,
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right.location.register,left.location.register));
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end;
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{ update location because sides could have been swapped }
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location.resflags:=getresflags(unsigned);
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end;
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{*****************************************************************************
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64-bit
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*****************************************************************************}
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procedure t68kaddnode.second_cmp64bit;
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var
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truelabel,
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falselabel: tasmlabel;
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hlab: tasmlabel;
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unsigned : boolean;
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href: treference;
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procedure firstjmp64bitcmp;
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var
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oldnodetype : tnodetype;
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begin
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case nodetype of
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ltn,gtn:
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begin
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if (hlab<>location.truelabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
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{ cheat a little bit for the negative test }
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toggleflag(nf_swapped);
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if (hlab<>location.falselabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
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toggleflag(nf_swapped);
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end;
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lten,gten:
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begin
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oldnodetype:=nodetype;
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if nodetype=lten then
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nodetype:=ltn
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else
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nodetype:=gtn;
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if (hlab<>location.truelabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
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{ cheat for the negative test }
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if nodetype=ltn then
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nodetype:=gtn
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else
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nodetype:=ltn;
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if (hlab<>location.falselabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
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nodetype:=oldnodetype;
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end;
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equaln:
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
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unequaln:
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
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end;
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end;
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procedure secondjmp64bitcmp;
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begin
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case nodetype of
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ltn,gtn,lten,gten:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.truelabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
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end;
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equaln:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,location.truelabel);
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end;
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unequaln:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
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end;
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end;
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end;
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begin
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truelabel:=nil;
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falselabel:=nil;
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{ This puts constant operand (if any) to the right }
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pass_left_right;
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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current_asmdata.getjumplabel(truelabel);
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current_asmdata.getjumplabel(falselabel);
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location_reset_jump(location,truelabel,falselabel);
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{ Relational compares against constants having low dword=0 can omit the
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second compare based on the fact that any unsigned value is >=0 }
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hlab:=nil;
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if (right.location.loc=LOC_CONSTANT) and
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(lo(right.location.value64)=0) then
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begin
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case getresflags(true) of
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F_AE: hlab:=location.truelabel;
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F_B: hlab:=location.falselabel;
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end;
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end;
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if (right.location.loc=LOC_CONSTANT) and (right.location.value64=0) and
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(nodetype in [equaln,unequaln]) then
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begin
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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href:=left.location.reference;
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tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_TST,S_L,href));
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firstjmp64bitcmp;
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|
inc(href.offset,4);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_TST,S_L,href));
|
|
secondjmp64bitcmp;
|
|
location_freetemp(current_asmdata.CurrAsmList,left.location);
|
|
end;
|
|
else
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,S_L,left.location.register64.reglo));
|
|
firstjmp64bitcmp;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,S_L,left.location.register64.reghi));
|
|
secondjmp64bitcmp;
|
|
end;
|
|
exit;
|
|
end;
|
|
|
|
{ left and right no register? }
|
|
{ then one must be demanded }
|
|
if not (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
begin
|
|
if not (right.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true)
|
|
else
|
|
begin
|
|
location_swap(left.location,right.location);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
end;
|
|
|
|
{ left is now in register }
|
|
case right.location.loc of
|
|
LOC_REGISTER,LOC_CREGISTER:
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register64.reghi,left.location.register64.reghi));
|
|
firstjmp64bitcmp;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,S_L,right.location.register64.reglo,left.location.register64.reglo));
|
|
secondjmp64bitcmp;
|
|
end;
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
begin
|
|
href:=right.location.reference;
|
|
tcg68k(cg).fixref(current_asmdata.CurrAsmList,href);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_CMP,S_L,href,left.location.register64.reghi));
|
|
firstjmp64bitcmp;
|
|
inc(href.offset,4);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_CMP,S_L,href,left.location.register64.reglo));
|
|
secondjmp64bitcmp;
|
|
location_freetemp(current_asmdata.CurrAsmList,right.location);
|
|
end;
|
|
LOC_CONSTANT:
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,aint(hi(right.location.value64)),left.location.register64.reghi));
|
|
firstjmp64bitcmp;
|
|
if assigned(hlab) then
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,hlab)
|
|
else
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,aint(lo(right.location.value64)),left.location.register64.reglo));
|
|
secondjmp64bitcmp;
|
|
end;
|
|
end;
|
|
else
|
|
InternalError(2014072501);
|
|
end;
|
|
end;
|
|
|
|
|
|
begin
|
|
caddnode:=t68kaddnode;
|
|
end.
|