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https://gitlab.com/freepascal.org/fpc/source.git
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+ RTL support: o VFP exceptions are disabled by default on Darwin, because they cause kernel panics on iPhoneOS 2.2.1 at least o all denormals are truncated to 0 on Darwin, because disabling that also causes kernel panics on iPhoneOS 2.2.1 (probably because otherwise denormals can also cause exceptions) * set softfloat rounding mode correctly for non-wince/darwin/vfp targets + compiler support: only half the number of single precision registers is available due to limitations of the register allocator + added a number of comments about why the stackframe on ARM is set up the way it is by the compiler + added regtype and subregtype info to regsets, because they're also used for VFP registers (+ support in assembler reader) + various generic support routines for dealing with floating point values located in integer registers that have to be transferred to mm registers (needed for VFP) * renamed use_sse() to use_vectorfpu() and also use it for ARM/vfp support o only superficially tested for Linux (compiler compiled with -Cpvfpv6 -Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least the fpu exception handler still needs to be implemented), Darwin has been tested more thoroughly + added ARMv6 cpu type and made it default for Darwin/ARM + ARMv6+ implementations of atomic operations using ldrex/strex * don't use r9 on Darwin/ARM, as it's reserved under certain circumstances (don't know yet which ones) * changed C-test object files for ARM/Darwin to ARMv6 versions * check in assembler reader that regsets are not empty, because instructions with a regset operand have undefined behaviour in that case * fixed resultdef of tarmtypeconvnode.first_int_to_real in case of int64->single type conversion * fixed constant pool locations in case 64 bit constants are generated, and/or when vfp instructions with limited reach are present WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all code with -Cparmv6 (or higher), or you will get crashes. The reason is that storing/restoring multiple VFP registers must happen using different instructions on pre/post-ARMv6. git-svn-id: trunk@14317 -
309 lines
10 KiB
ObjectPascal
309 lines
10 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate x86 code for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx86mat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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tx86unaryminusnode = class(tcgunaryminusnode)
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;override;
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{$endif SUPPORT_MMX}
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procedure second_float;override;
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function pass_1:tnode;override;
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end;
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tx86notnode = class(tcgnotnode)
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procedure second_boolean;override;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;override;
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{$endif SUPPORT_MMX}
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end;
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implementation
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uses
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globtype,
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systems,
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cutils,verbose,globals,
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symconst,symdef,
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aasmbase,aasmtai,aasmdata,defutil,
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cgbase,pass_1,pass_2,
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ncon,
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cpubase,procinfo,
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cga,ncgutil,cgobj,cgx86,cgutils;
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{*****************************************************************************
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TI386UNARYMINUSNODE
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*****************************************************************************}
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function tx86unaryminusnode.pass_1 : tnode;
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begin
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result:=nil;
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firstpass(left);
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if codegenerror then
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exit;
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if (left.resultdef.typ=floatdef) then
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begin
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if use_vectorfpu(left.resultdef) then
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expectloc:=LOC_MMREGISTER
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else
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expectloc:=LOC_FPUREGISTER;
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end
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{$ifdef SUPPORT_MMX}
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else
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if (cs_mmx in current_settings.localswitches) and
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is_mmx_able_array(left.resultdef) then
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begin
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expectloc:=LOC_MMXREGISTER;
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end
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{$endif SUPPORT_MMX}
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else
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inherited pass_1;
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end;
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{$ifdef SUPPORT_MMX}
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procedure tx86unaryminusnode.second_mmx;
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var
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op : tasmop;
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hreg : tregister;
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begin
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secondpass(left);
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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hreg:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_PXOR,S_NO,hreg,hreg);
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case left.location.loc of
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LOC_MMXREGISTER:
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begin
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location.register:=left.location.register;
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end;
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LOC_CMMXREGISTER:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
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end;
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else
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internalerror(200203225);
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end;
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if cs_mmx_saturation in current_settings.localswitches then
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case mmx_type(resultdef) of
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mmxs8bit:
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op:=A_PSUBSB;
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mmxu8bit:
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op:=A_PSUBUSB;
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mmxs16bit,mmxfixed16:
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op:=A_PSUBSW;
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mmxu16bit:
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op:=A_PSUBUSW;
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end
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else
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case mmx_type(resultdef) of
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mmxs8bit,mmxu8bit:
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op:=A_PSUBB;
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mmxs16bit,mmxu16bit,mmxfixed16:
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op:=A_PSUBW;
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mmxs32bit,mmxu32bit:
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op:=A_PSUBD;
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end;
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emit_reg_reg(op,S_NO,location.register,hreg);
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emit_reg_reg(A_MOVQ,S_NO,hreg,location.register);
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end;
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{$endif SUPPORT_MMX}
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procedure tx86unaryminusnode.second_float;
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var
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reg : tregister;
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href : treference;
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l1 : tasmlabel;
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begin
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secondpass(left);
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if expectloc=LOC_MMREGISTER then
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begin
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location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,false);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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{ make life of register allocator easier }
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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cg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),def_cgsize(resultdef),left.location.register,location.register,mms_movescalar);
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reg:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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current_asmdata.getdatalabel(l1);
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current_asmdata.asmlists[al_typedconsts].concat(Tai_label.Create(l1));
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case def_cgsize(resultdef) of
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OS_F32:
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current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(longint(1 shl 31)));
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OS_F64:
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begin
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current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(0));
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current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(-(1 shl 31)));
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end
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else
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internalerror(2004110215);
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end;
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reference_reset_symbol(href,l1,0,resultdef.alignment);
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cg.a_loadmm_ref_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),def_cgsize(resultdef),href,reg,mms_movescalar);
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cg.a_opmm_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.location.size,reg,location.register,nil);
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end
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else
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=NR_ST;
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
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left.location.size,location.size,
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left.location.reference,location.register);
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emit_none(A_FCHS,S_NO);
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end;
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LOC_FPUREGISTER,
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LOC_CFPUREGISTER:
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begin
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{ "load st,st" is ignored by the code generator }
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cg.a_loadfpu_reg_reg(current_asmdata.CurrAsmList,left.location.size,location.size,left.location.register,NR_ST);
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location.register:=NR_ST;
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emit_none(A_FCHS,S_NO);
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end;
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else
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internalerror(200312241);
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end;
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end;
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end;
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{*****************************************************************************
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TX86NOTNODE
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*****************************************************************************}
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procedure tx86notnode.second_boolean;
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var
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hl : tasmlabel;
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opsize : tcgsize;
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begin
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opsize:=def_cgsize(resultdef);
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if left.expectloc=LOC_JUMP then
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begin
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location_reset(location,LOC_JUMP,OS_NO);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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secondpass(left);
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maketojumpbool(current_asmdata.CurrAsmList,left,lr_load_regvars);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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end
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else
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begin
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{ the second pass could change the location of left }
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{ if it is a register variable, so we've to do }
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{ this before the case statement }
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secondpass(left);
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case left.expectloc of
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LOC_FLAGS :
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=left.location.resflags;
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inverse_flags(location.resflags);
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end;
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LOC_CONSTANT,
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LOC_REGISTER,
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LOC_CREGISTER,
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LOC_REFERENCE,
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LOC_CREFERENCE,
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LOC_SUBSETREG,
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LOC_CSUBSETREG,
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LOC_SUBSETREF,
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LOC_CSUBSETREF :
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begin
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location_force_reg(current_asmdata.CurrAsmList,left.location,opsize,true);
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emit_reg_reg(A_TEST,TCGSize2Opsize[opsize],left.location.register,left.location.register);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_E;
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end;
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else
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internalerror(200203224);
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end;
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end;
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end;
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{$ifdef SUPPORT_MMX}
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procedure tx86notnode.second_mmx;
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var hreg,r:Tregister;
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begin
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secondpass(left);
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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r:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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emit_const_reg(A_MOV,S_L,longint($ffffffff),r);
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{ load operand }
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case left.location.loc of
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LOC_MMXREGISTER:
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location_copy(location,left.location);
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LOC_CMMXREGISTER:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
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end;
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end;
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{ load mask }
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hreg:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_MOVD,S_NO,r,hreg);
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{ lower 32 bit }
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emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
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{ shift mask }
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emit_const_reg(A_PSLLQ,S_B,32,hreg);
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{ higher 32 bit }
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emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
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end;
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{$endif SUPPORT_MMX}
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end.
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