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https://gitlab.com/freepascal.org/fpc/source.git
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403 lines
13 KiB
ObjectPascal
403 lines
13 KiB
ObjectPascal
{
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Copyright (c) 2014 Jonas Maebe
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Code generation for add nodes on AArch64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpuadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgadd,cpubase;
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type
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taarch64addnode = class(tcgaddnode)
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private
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function GetResFlags(unsigned:Boolean):TResFlags;
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function GetFPUResFlags:TResFlags;
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protected
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpboolean;override;
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procedure second_cmpsmallset;override;
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procedure second_cmpordinal;override;
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procedure second_addordinal;override;
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procedure second_add64bit; override;
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procedure second_cmp64bit; override;
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public
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function use_generic_mul32to64: boolean; override;
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end;
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implementation
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uses
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systems,
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cutils,verbose,
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paramgr,procinfo,
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aasmtai,aasmdata,aasmcpu,defutil,
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cgbase,cgcpu,cgutils,
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cpupara,
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ncon,nset,nadd,
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hlcgobj, ncgutil,cgobj;
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{*****************************************************************************
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taarch64addnode
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*****************************************************************************}
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function taarch64addnode.GetResFlags(unsigned:Boolean):TResFlags;
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begin
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case NodeType of
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equaln:
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GetResFlags:=F_EQ;
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unequaln:
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GetResFlags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case NodeType of
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ltn:
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GetResFlags:=F_GT;
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lten:
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GetResFlags:=F_GE;
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gtn:
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GetResFlags:=F_LT;
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gten:
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GetResFlags:=F_LE;
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else
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internalerror(2014082010);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LT;
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lten:
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GetResFlags:=F_LE;
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gtn:
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GetResFlags:=F_GT;
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gten:
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GetResFlags:=F_GE;
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else
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internalerror(2014082011);
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end;
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end
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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GetResFlags:=F_HI;
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lten:
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GetResFlags:=F_HS;
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gtn:
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GetResFlags:=F_LO;
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gten:
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GetResFlags:=F_LS;
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else
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internalerror(2014082012);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LO;
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lten:
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GetResFlags:=F_LS;
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gtn:
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GetResFlags:=F_HI;
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gten:
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GetResFlags:=F_HS;
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else
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internalerror(2014082013);
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end;
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end;
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end;
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end;
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function taarch64addnode.GetFPUResFlags:TResFlags;
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begin
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case NodeType of
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equaln:
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result:=F_EQ;
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unequaln:
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result:=F_NE;
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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result:=F_GT;
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lten:
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result:=F_GE;
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gtn:
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result:=F_LO;
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gten:
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result:=F_LS;
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else
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internalerror(2014082014);
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end
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else
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case NodeType of
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ltn:
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result:=F_LO;
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lten:
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result:=F_LS;
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gtn:
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result:=F_GT;
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gten:
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result:=F_GE;
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else
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internalerror(2014082015);
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end;
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end;
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end;
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end;
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procedure taarch64addnode.second_addfloat;
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var
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op : TAsmOp;
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begin
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pass_left_right;
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if nf_swapped in flags then
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swapleftright;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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case nodetype of
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addn :
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begin
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op:=A_FADD;
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end;
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muln :
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begin
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op:=A_FMUL;
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end;
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subn :
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begin
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op:=A_FSUB;
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end;
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slashn :
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begin
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op:=A_FDIV;
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end;
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else
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internalerror(200306014);
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,
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location.register,left.location.register,right.location.register));
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end;
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procedure taarch64addnode.second_cmpfloat;
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begin
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pass_left_right;
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if nf_swapped in flags then
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swapleftright;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getfpuresflags;
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{ signalling compare so we can get exceptions }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FCMPE,
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left.location.register,right.location.register));
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end;
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procedure taarch64addnode.second_cmpboolean;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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if right.location.loc=LOC_CONSTANT then
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begin
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if right.location.value>=0 then
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Tcgaarch64(cg).handle_reg_imm12_reg(current_asmdata.CurrAsmList,A_CMP,left.location.size,left.location.register,right.location.value,NR_XZR,NR_NO,false,false)
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else
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{ avoid overflow if value=low(int64) }
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{$push}{$r-}{$q-}
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Tcgaarch64(cg).handle_reg_imm12_reg(current_asmdata.CurrAsmList,A_CMN,left.location.size,left.location.register,-right.location.value,NR_XZR,NR_NO,false,false)
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{$pop}
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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end;
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procedure taarch64addnode.second_cmpsmallset;
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var
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tmpreg : tregister;
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op: tasmop;
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begin
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pass_left_right;
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location_reset(location,LOC_FLAGS,OS_NO);
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force_reg_left_right(true,true);
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if right.location.loc=LOC_CONSTANT then
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begin
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{ when doing a cmp/cmn on 32 bit, we care whether the *lower 32 bit*
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is a positive/negative value -> sign extend }
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if not(right.location.size in [OS_64,OS_S64]) then
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right.location.value:=longint(right.location.value);
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if right.location.value>=0 then
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op:=A_CMP
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else
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op:=A_CMN;
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end
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else
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{ for DFA }
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op:=A_NONE;
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case nodetype of
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equaln,
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unequaln:
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begin
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if right.location.loc=LOC_CONSTANT then
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tcgaarch64(cg).handle_reg_imm12_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),left.location.register,abs(right.location.value),NR_XZR,NR_NO,false,false)
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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location.resflags:=getresflags(true);
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end;
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lten,
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gten:
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begin
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if (not(nf_swapped in flags) and
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(nodetype=lten)) or
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((nf_swapped in flags) and
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(nodetype=gten)) then
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swapleftright;
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{ we can't handle left as a constant yet }
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if left.location.loc=LOC_CONSTANT then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,left.location.size);
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if right.location.loc=LOC_CONSTANT then
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begin
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hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_AND,resultdef,right.location.value,left.location.register,tmpreg);
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tcgaarch64(cg).handle_reg_imm12_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),tmpreg,abs(right.location.value),NR_XZR,NR_NO,false,false)
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end
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else
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_AND,tmpreg,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,tmpreg,right.location.register));
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end;
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2012042701);
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end;
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end;
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procedure taarch64addnode.second_cmpordinal;
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var
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unsigned : boolean;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if right.location.loc = LOC_CONSTANT then
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begin
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if right.location.value>=0 then
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Tcgaarch64(cg).handle_reg_imm12_reg(current_asmdata.CurrAsmList,A_CMP,left.location.size,left.location.register,right.location.value,NR_XZR,NR_NO,false,false)
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else
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{$push}{$r-}{$q-}
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Tcgaarch64(cg).handle_reg_imm12_reg(current_asmdata.CurrAsmList,A_CMN,left.location.size,left.location.register,-right.location.value,NR_XZR,NR_NO,false,false)
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{$pop}
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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end;
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procedure taarch64addnode.second_addordinal;
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const
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multops: array[boolean] of TAsmOp = (A_SMULL,A_UMULL);
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var
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unsigned: boolean;
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begin
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{ 32x32->64 multiplication }
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if (nodetype=muln) and
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is_32bit(left.resultdef) and
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is_32bit(right.resultdef) and
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is_64bit(resultdef) then
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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pass_left_right;
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force_reg_left_right(true,true);
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{ force_reg_left_right can leave right as a LOC_CONSTANT (we can't
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say "a constant register is okay, but an ordinal constant isn't) }
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if right.location.loc=LOC_CONSTANT then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(multops[unsigned],location.register,left.location.register,right.location.register));
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end
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else
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inherited second_addordinal;
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end;
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procedure taarch64addnode.second_add64bit;
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begin
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second_addordinal;
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end;
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procedure taarch64addnode.second_cmp64bit;
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begin
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second_cmpordinal;
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end;
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function taarch64addnode.use_generic_mul32to64: boolean;
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begin
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result:=false;
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end;
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begin
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caddnode:=taarch64addnode;
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end.
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