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686 lines
30 KiB
ObjectPascal
686 lines
30 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
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Development Team
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This unit implements the ARM optimizer object
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit aoptcpu;
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{$i fpcdefs.inc}
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Interface
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uses cpubase, aasmtai, aopt, aoptcpub;
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Type
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TCpuAsmOptimizer = class(TAsmOptimizer)
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{ uses the same constructor as TAopObj }
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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procedure PeepHoleOptPass2;override;
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End;
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TCpuPreRegallocScheduler = class(TAsmOptimizer)
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function PeepHoleOptPass1Cpu(var p: tai): boolean;override;
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end;
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TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
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{ uses the same constructor as TAopObj }
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procedure PeepHoleOptPass2;override;
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End;
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Implementation
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uses
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cutils,
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verbose,
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cgbase,cgutils,
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aasmbase,aasmdata,aasmcpu;
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function CanBeCond(p : tai) : boolean;
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begin
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result:=
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(p.typ=ait_instruction) and
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(taicpu(p).condition=C_None) and
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((taicpu(p).opcode<>A_BLX) or
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(taicpu(p).oper[0]^.typ=top_reg));
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end;
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function RefsEqual(const r1, r2: treference): boolean;
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begin
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refsequal :=
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(r1.offset = r2.offset) and
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(r1.base = r2.base) and
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(r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
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(r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
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(r1.relsymbol = r2.relsymbol) and
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(r1.signindex = r2.signindex) and
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(r1.shiftimm = r2.shiftimm) and
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(r1.addressmode = r2.addressmode) and
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(r1.shiftmode = r2.shiftmode);
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end;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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begin
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result :=
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(instr.typ = ait_instruction) and
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(taicpu(instr).opcode = op) and
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((cond = []) or (taicpu(instr).condition in cond)) and
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((postfix = []) or (taicpu(instr).oppostfix in postfix));
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end;
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function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
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begin
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result := (oper1.typ = oper2.typ) and
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(
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((oper1.typ = top_const) and (oper1.val = oper2.val)) or
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((oper1.typ = top_reg) and (oper1.reg = oper2.reg)) or
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((oper1.typ = top_conditioncode) and (oper1.cc = oper2.cc))
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);
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end;
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function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
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begin
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result := (oper.typ = top_reg) and (oper.reg = reg);
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end;
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procedure RemoveRedundantMove(const cmpp: tai; movp: tai; asml: TAsmList) ;
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begin
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if (taicpu(movp).condition = C_EQ) and
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(taicpu(cmpp).oper[0]^.reg = taicpu(movp).oper[0]^.reg) and
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(taicpu(cmpp).oper[1]^.val = taicpu(movp).oper[1]^.val) then
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begin
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asml.insertafter(tai_comment.Create(strpnew('Peephole CmpMovMov - Removed redundant moveq')), movp);
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asml.remove(movp);
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movp.free;
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end;
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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hp1,hp2: tai;
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i: longint;
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begin
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result := false;
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case p.typ of
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ait_instruction:
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begin
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(* optimization proved not to be safe, see tw4768.pp
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{
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change
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<op> reg,x,y
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cmp reg,#0
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into
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<op>s reg,x,y
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}
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{ this optimization can applied only to the currently enabled operations because
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the other operations do not update all flags and FPC does not track flag usage }
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if (taicpu(p).opcode in [A_ADC,A_ADD,A_SUB {A_UDIV,A_SDIV,A_MUL,A_MVN,A_MOV,A_ORR,A_EOR,A_AND}]) and
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(taicpu(p).oppostfix = PF_None) and
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(taicpu(p).condition = C_None) and
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GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_CMP, [C_None], [PF_None]) and
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(taicpu(hp1).oper[1]^.typ = top_const) and
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(taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
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(taicpu(hp1).oper[1]^.val = 0) { and
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GetNextInstruction(hp1, hp2) and
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(tai(hp2).typ = ait_instruction) and
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// be careful here, following instructions could use other flags
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// however after a jump fpc never depends on the value of flags
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(taicpu(hp2).opcode = A_B) and
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(taicpu(hp2).condition in [C_EQ,C_NE,C_MI,C_PL])} then
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begin
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taicpu(p).oppostfix:=PF_S;
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asml.remove(hp1);
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hp1.free;
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end
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else
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*)
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case taicpu(p).opcode of
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A_STR:
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begin
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{ change
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str reg1,ref
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ldr reg2,ref
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into
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str reg1,ref
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mov reg2,reg1
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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GetNextInstruction(p,hp1) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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(taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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begin
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if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
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begin
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asml.remove(hp1);
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hp1.free;
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end
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else
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole StrLdr2StrMov done')), hp1);
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taicpu(hp1).opcode:=A_MOV;
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taicpu(hp1).oppostfix:=PF_None;
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taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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end;
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result := true;
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end;
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end;
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A_LDR:
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begin
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{ change
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ldr reg1,ref
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ldr reg2,ref
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into
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ldr reg1,ref
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mov reg2,reg1
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}
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if (taicpu(p).oper[1]^.ref^.addressmode=AM_OFFSET) and
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GetNextInstruction(p,hp1) and
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MatchInstruction(hp1, A_LDR, [taicpu(p).condition, C_None], [PF_None]) and
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RefsEqual(taicpu(p).oper[1]^.ref^,taicpu(hp1).oper[1]^.ref^) and
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(taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.index) and
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(taicpu(p).oper[0]^.reg<>taicpu(hp1).oper[1]^.ref^.base) and
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(taicpu(hp1).oper[1]^.ref^.addressmode=AM_OFFSET) then
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begin
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if taicpu(hp1).oper[0]^.reg=taicpu(p).oper[0]^.reg then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2Ldr done')), hp1);
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asml.remove(hp1);
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hp1.free;
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end
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else
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole LdrLdr2LdrMov done')), hp1);
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taicpu(hp1).opcode:=A_MOV;
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taicpu(hp1).oppostfix:=PF_None;
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taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
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end;
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result := true;
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end;
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end;
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A_MOV:
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begin
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{ fold
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mov reg1,reg0, shift imm1
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mov reg1,reg1, shift imm2
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to
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mov reg1,reg0, shift imm1+imm2
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}
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if (taicpu(p).ops=3) and
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(taicpu(p).oper[2]^.typ = top_shifterop) and
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(taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
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getnextinstruction(p,hp1) and
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MatchInstruction(hp1, A_MOV, [taicpu(p).condition], [PF_None]) and
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(taicpu(hp1).ops=3) and
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MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[2]^.typ = top_shifterop) and
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(taicpu(hp1).oper[2]^.shifterop^.rs = NR_NO) and
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(taicpu(p).oper[2]^.shifterop^.shiftmode=taicpu(hp1).oper[2]^.shifterop^.shiftmode) then
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begin
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inc(taicpu(p).oper[2]^.shifterop^.shiftimm,taicpu(hp1).oper[2]^.shifterop^.shiftimm);
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{ avoid overflows }
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if taicpu(p).oper[2]^.shifterop^.shiftimm>31 then
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case taicpu(p).oper[2]^.shifterop^.shiftmode of
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SM_ROR:
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taicpu(p).oper[2]^.shifterop^.shiftimm:=taicpu(p).oper[2]^.shifterop^.shiftimm and 31;
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SM_ASR:
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taicpu(p).oper[2]^.shifterop^.shiftimm:=31;
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SM_LSR,
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SM_LSL:
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begin
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hp1:=taicpu.op_reg_const(A_MOV,taicpu(p).oper[0]^.reg,0);
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InsertLLItem(p.previous, p.next, hp1);
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p.free;
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p:=hp1;
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end;
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else
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internalerror(2008072803);
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end;
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asml.insertbefore(tai_comment.Create(strpnew('Peephole ShiftShift2Shift done')), p);
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asml.remove(hp1);
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hp1.free;
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result := true;
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end;
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{
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This changes the very common
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mov r0, #0
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str r0, [...]
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mov r0, #0
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str r0, [...]
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and removes all superfluous mov instructions
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}
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if (taicpu(p).ops = 2) and
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(taicpu(p).oper[1]^.typ = top_const) and
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GetNextInstruction(p,hp1) then
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begin
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while MatchInstruction(hp1, A_STR, [], []) and
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MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) and
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GetNextInstruction(hp1, hp2) and
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MatchInstruction(hp2, A_MOV, [taicpu(p).condition], [taicpu(p).oppostfix]) and
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(taicpu(hp2).ops = 2) and
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MatchOperand(taicpu(hp2).oper[0]^, taicpu(p).oper[0]^) and
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MatchOperand(taicpu(hp2).oper[1]^, taicpu(p).oper[1]^) do
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole MovStrMov done')), hp2);
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GetNextInstruction(hp2,hp1);
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asml.remove(hp2);
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hp2.free;
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if not assigned(hp1) then break;
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end;
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end;
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{
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change
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mov r1, r0
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add r1, r1, #1
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to
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add r1, r0, #1
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}
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if (taicpu(p).ops = 2) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oppostfix = PF_NONE) and
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GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode in [A_ADD, A_ADC, A_RSB, A_RSC, A_SUB, A_SBC,
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A_AND, A_BIC, A_EOR, A_ORR]) and
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(taicpu(hp1).condition in [C_NONE, taicpu(hp1).condition]) and
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MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) and
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(taicpu(hp1).oper[1]^.typ = top_reg) and
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(taicpu(hp1).oper[2]^.typ in [top_reg, top_const]) then
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begin
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{ When we get here we still don't know if the registers match}
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for I:=1 to 2 do
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{
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If the first loop was successful p will be replaced with hp1.
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The checks will still be ok, because all required information
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will also be in hp1 then.
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}
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if MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[I]^.reg) then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole RedundantMovProcess done ')), hp1);
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taicpu(hp1).oper[I]^.reg := taicpu(p).oper[1]^.reg;
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if p<>hp1 then
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begin
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asml.remove(p);
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p.free;
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p:=hp1;
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end;
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end;
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end;
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end;
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A_AND:
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begin
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{
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change
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and reg2,reg1,const1
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and reg2,reg2,const2
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to
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and reg2,reg1,(const1 and const2)
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}
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if (taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ = top_const) and
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GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_AND, [taicpu(p).condition], [PF_None]) and
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MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^.reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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(taicpu(hp1).oper[2]^.typ = top_const) then
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begin
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asml.insertbefore(tai_comment.Create(strpnew('Peephole AndAnd2And done')), p);
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taicpu(p).loadConst(2,taicpu(p).oper[2]^.val and taicpu(hp1).oper[2]^.val);
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taicpu(p).oppostfix:=taicpu(hp1).oppostfix;
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asml.remove(hp1);
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hp1.free;
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end;
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end;
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A_CMP:
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begin
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{
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change
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cmp reg,const1
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moveq reg,const1
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movne reg,const2
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to
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cmp reg,const1
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movne reg,const2
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}
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if (taicpu(p).oper[1]^.typ = top_const) and
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GetNextInstruction(p, hp1) and
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MatchInstruction(hp1, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
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(taicpu(hp1).oper[1]^.typ = top_const) and
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GetNextInstruction(hp1, hp2) and
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MatchInstruction(hp2, A_MOV, [C_EQ, C_NE], [PF_NONE]) and
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(taicpu(hp1).oper[1]^.typ = top_const) then
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begin
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RemoveRedundantMove(p, hp1, asml);
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RemoveRedundantMove(p, hp2, asml);
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end;
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end;
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end;
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end;
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end;
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end;
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{ instructions modifying the CPSR can be only the last instruction }
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function MustBeLast(p : tai) : boolean;
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begin
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Result:=(p.typ=ait_instruction) and
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((taicpu(p).opcode in [A_BL,A_BLX,A_CMP,A_CMN,A_SWI,A_TEQ,A_TST,A_CMF,A_CMFE {,A_MSR}]) or
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((taicpu(p).ops>=1) and (taicpu(p).oper[0]^.typ=top_reg) and (taicpu(p).oper[0]^.reg=NR_PC)) or
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(taicpu(p).oppostfix=PF_S));
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end;
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procedure TCpuAsmOptimizer.PeepHoleOptPass2;
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var
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p,hp1,hp2: tai;
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l : longint;
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condition : tasmcond;
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hp3: tai;
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WasLast: boolean;
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{ UsedRegs, TmpUsedRegs: TRegSet; }
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begin
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p := BlockStart;
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{ UsedRegs := []; }
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while (p <> BlockEnd) Do
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begin
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{ UpdateUsedRegs(UsedRegs, tai(p.next)); }
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case p.Typ Of
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Ait_Instruction:
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begin
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case taicpu(p).opcode Of
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A_B:
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if taicpu(p).condition<>C_None then
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begin
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{ check for
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Bxx xxx
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<several instructions>
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xxx:
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}
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l:=0;
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WasLast:=False;
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GetNextInstruction(p, hp1);
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while assigned(hp1) and
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(l<=4) and
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CanBeCond(hp1) and
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{ stop on labels }
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not(hp1.typ=ait_label) do
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begin
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inc(l);
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if MustBeLast(hp1) then
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begin
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WasLast:=True;
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GetNextInstruction(hp1,hp1);
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break;
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end
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else
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GetNextInstruction(hp1,hp1);
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end;
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if assigned(hp1) then
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begin
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if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
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begin
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if (l<=4) and (l>0) then
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begin
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condition:=inverse_cond(taicpu(p).condition);
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hp2:=p;
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GetNextInstruction(p,hp1);
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p:=hp1;
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repeat
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if hp1.typ=ait_instruction then
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taicpu(hp1).condition:=condition;
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if MustBeLast(hp1) then
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begin
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GetNextInstruction(hp1,hp1);
|
|
break;
|
|
end
|
|
else
|
|
GetNextInstruction(hp1,hp1);
|
|
until not(assigned(hp1)) or
|
|
not(CanBeCond(hp1)) or
|
|
(hp1.typ=ait_label);
|
|
{ wait with removing else GetNextInstruction could
|
|
ignore the label if it was the only usage in the
|
|
jump moved away }
|
|
tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
|
|
asml.remove(hp2);
|
|
hp2.free;
|
|
continue;
|
|
end;
|
|
end
|
|
else
|
|
{ do not perform further optimizations if there is inctructon
|
|
in block #1 which can not be optimized.
|
|
}
|
|
if not WasLast then
|
|
begin
|
|
{ check further for
|
|
Bcc xxx
|
|
<several instructions 1>
|
|
B yyy
|
|
xxx:
|
|
<several instructions 2>
|
|
yyy:
|
|
}
|
|
{ hp2 points to jmp yyy }
|
|
hp2:=hp1;
|
|
{ skip hp1 to xxx }
|
|
GetNextInstruction(hp1, hp1);
|
|
if assigned(hp2) and
|
|
assigned(hp1) and
|
|
(l<=3) and
|
|
(hp2.typ=ait_instruction) and
|
|
(taicpu(hp2).is_jmp) and
|
|
(taicpu(hp2).condition=C_None) and
|
|
{ real label and jump, no further references to the
|
|
label are allowed }
|
|
(tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
|
|
FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
|
|
begin
|
|
l:=0;
|
|
{ skip hp1 to <several moves 2> }
|
|
GetNextInstruction(hp1, hp1);
|
|
while assigned(hp1) and
|
|
CanBeCond(hp1) do
|
|
begin
|
|
inc(l);
|
|
GetNextInstruction(hp1, hp1);
|
|
end;
|
|
{ hp1 points to yyy: }
|
|
if assigned(hp1) and
|
|
FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
|
|
begin
|
|
condition:=inverse_cond(taicpu(p).condition);
|
|
GetNextInstruction(p,hp1);
|
|
hp3:=p;
|
|
p:=hp1;
|
|
repeat
|
|
if hp1.typ=ait_instruction then
|
|
taicpu(hp1).condition:=condition;
|
|
GetNextInstruction(hp1,hp1);
|
|
until not(assigned(hp1)) or
|
|
not(CanBeCond(hp1));
|
|
{ hp2 is still at jmp yyy }
|
|
GetNextInstruction(hp2,hp1);
|
|
{ hp2 is now at xxx: }
|
|
condition:=inverse_cond(condition);
|
|
GetNextInstruction(hp1,hp1);
|
|
{ hp1 is now at <several movs 2> }
|
|
repeat
|
|
taicpu(hp1).condition:=condition;
|
|
GetNextInstruction(hp1,hp1);
|
|
until not(assigned(hp1)) or
|
|
not(CanBeCond(hp1)) or
|
|
(hp1.typ=ait_label);
|
|
{
|
|
asml.remove(hp1.next)
|
|
hp1.next.free;
|
|
asml.remove(hp1);
|
|
hp1.free;
|
|
}
|
|
{ remove Bcc }
|
|
tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
|
|
asml.remove(hp3);
|
|
hp3.free;
|
|
{ remove jmp }
|
|
tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
|
|
asml.remove(hp2);
|
|
hp2.free;
|
|
continue;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
p := tai(p.next)
|
|
end;
|
|
end;
|
|
|
|
const
|
|
{ set of opcode which might or do write to memory }
|
|
{ TODO : extend armins.dat to contain r/w info }
|
|
opcode_could_mem_write = [A_B,A_BL,A_BLX,A_BKPT,A_BX,A_STR,A_STRB,A_STRBT,
|
|
A_STRH,A_STRT,A_STF,A_SFM,A_STM,A_FSTS,A_FSTD];
|
|
|
|
function TCpuPreRegallocScheduler.PeepHoleOptPass1Cpu(var p: tai): boolean;
|
|
{ TODO : schedule also forward }
|
|
{ TODO : schedule distance > 1 }
|
|
var
|
|
hp1,hp2,hp3,hp4,hp5 : tai;
|
|
list : TAsmList;
|
|
begin
|
|
result:=true;
|
|
list:=TAsmList.Create;
|
|
p := BlockStart;
|
|
{ UsedRegs := []; }
|
|
while (p <> BlockEnd) Do
|
|
begin
|
|
if (p.typ=ait_instruction) and
|
|
GetNextInstruction(p,hp1) and
|
|
(hp1.typ=ait_instruction) and
|
|
{ for now we don't reschedule if the previous instruction changes potentially a memory location }
|
|
( (not(taicpu(p).opcode in opcode_could_mem_write) and
|
|
not(RegModifiedByInstruction(NR_PC,p)) and
|
|
(taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH])
|
|
) or
|
|
((taicpu(p).opcode in [A_STM,A_STRB,A_STRH,A_STR]) and
|
|
(taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
|
|
((taicpu(hp1).oper[1]^.ref^.base=NR_PC) or
|
|
(assigned(taicpu(hp1).oper[1]^.ref^.symboldata) and
|
|
(taicpu(hp1).oper[1]^.ref^.offset=0)
|
|
)
|
|
) or
|
|
{ try to prove that the memory accesses don't overlapp }
|
|
((taicpu(p).opcode in [A_STRB,A_STRH,A_STR]) and
|
|
(taicpu(hp1).opcode in [A_LDR,A_LDRB,A_LDRH,A_LDRSB,A_LDRSH]) and
|
|
(taicpu(p).oper[1]^.ref^.base=taicpu(hp1).oper[1]^.ref^.base) and
|
|
(taicpu(p).oppostfix=PF_None) and
|
|
(taicpu(hp1).oppostfix=PF_None) and
|
|
(taicpu(p).oper[1]^.ref^.index=NR_NO) and
|
|
(taicpu(hp1).oper[1]^.ref^.index=NR_NO) and
|
|
{ get operand sizes and check if the offset distance is large enough to ensure no overlapp }
|
|
(abs(taicpu(p).oper[1]^.ref^.offset-taicpu(hp1).oper[1]^.ref^.offset)>=max(tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)],tcgsize2size[reg_cgsize(taicpu(hp1).oper[0]^.reg)]))
|
|
)
|
|
)
|
|
) and
|
|
GetNextInstruction(hp1,hp2) and
|
|
(hp2.typ=ait_instruction) and
|
|
{ loaded register used by next instruction? }
|
|
(RegInInstruction(taicpu(hp1).oper[0]^.reg,hp2)) and
|
|
{ loaded register not used by previous instruction? }
|
|
not(RegInInstruction(taicpu(hp1).oper[0]^.reg,p)) and
|
|
{ same condition? }
|
|
(taicpu(p).condition=taicpu(hp1).condition) and
|
|
{ first instruction might not change the register used as base }
|
|
((taicpu(hp1).oper[1]^.ref^.base=NR_NO) or
|
|
not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.base,p))
|
|
) and
|
|
{ first instruction might not change the register used as index }
|
|
((taicpu(hp1).oper[1]^.ref^.index=NR_NO) or
|
|
not(RegModifiedByInstruction(taicpu(hp1).oper[1]^.ref^.index,p))
|
|
) then
|
|
begin
|
|
hp3:=tai(p.Previous);
|
|
hp5:=tai(p.next);
|
|
asml.Remove(p);
|
|
{ if there is a reg. dealloc instruction associated with p, move it together with p }
|
|
|
|
{ before the instruction? }
|
|
while assigned(hp3) and (hp3.typ<>ait_instruction) do
|
|
begin
|
|
if (hp3.typ=ait_regalloc) and (tai_regalloc(hp3).ratype in [ra_dealloc]) and
|
|
RegInInstruction(tai_regalloc(hp3).reg,p) then
|
|
begin
|
|
hp4:=hp3;
|
|
hp3:=tai(hp3.Previous);
|
|
asml.Remove(hp4);
|
|
list.Concat(hp4);
|
|
end
|
|
else
|
|
hp3:=tai(hp3.Previous);
|
|
end;
|
|
list.Concat(p);
|
|
{ after the instruction? }
|
|
while assigned(hp5) and (hp5.typ<>ait_instruction) do
|
|
begin
|
|
if (hp5.typ=ait_regalloc) and (tai_regalloc(hp5).ratype in [ra_dealloc]) and
|
|
RegInInstruction(tai_regalloc(hp5).reg,p) then
|
|
begin
|
|
hp4:=hp5;
|
|
hp5:=tai(hp5.next);
|
|
asml.Remove(hp4);
|
|
list.Concat(hp4);
|
|
end
|
|
else
|
|
hp5:=tai(hp5.Next);
|
|
end;
|
|
|
|
asml.Remove(hp1);
|
|
{$ifdef DEBUG_PREREGSCHEDULER}
|
|
asml.InsertBefore(tai_comment.Create(strpnew('Rescheduled')),hp2);
|
|
{$endif DEBUG_PREREGSCHEDULER}
|
|
asml.InsertBefore(hp1,hp2);
|
|
asml.InsertListBefore(hp2,list);
|
|
end;
|
|
p := tai(p.next)
|
|
end;
|
|
list.Free;
|
|
end;
|
|
|
|
|
|
procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
|
|
begin
|
|
{ TODO: Add optimizer code }
|
|
end;
|
|
|
|
begin
|
|
casmoptimizer:=TCpuAsmOptimizer;
|
|
cpreregallocscheduler:=TCpuPreRegallocScheduler;
|
|
End.
|