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29bae2297f
Also override the code that uses this for LLVM with a variant that does not need it for LLVM versions that do not support the freeze instruction.
98 lines
3.3 KiB
ObjectPascal
98 lines
3.3 KiB
ObjectPascal
{
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Copyright (c) 2019 by Jonas Maebe
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Generate LLVM bytecode for set/case nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nllvmset;
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{$i fpcdefs.inc}
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interface
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uses
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nset, ncgset,
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symtype,
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cgbase;
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type
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tllvminnode = class(tcginnode)
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protected
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procedure in_reg_const(uopdef: tdef; opsize: tcgsize); override;
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end;
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tllvmcasenode = class(tcgcasenode)
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protected
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procedure genlinearlist(hp: pcaselabel); override;
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end;
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implementation
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uses
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globals,
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aasmbase, aasmdata,
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hlcgobj,
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llvminfo;
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procedure tllvminnode.in_reg_const(uopdef: tdef; opsize: tcgsize);
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var
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hl,hlend: TAsmLabel;
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begin
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if not(llvmflag_no_freeze in llvmversion_properties[current_settings.llvmversion]) then
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begin
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{ if we have the freeze instruction, we can mark the poison value
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potentially generated by the shift as "replace with a fixed value
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if it's poison, we don't care since we'll mask it anyway" }
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inherited;
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exit;
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end;
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{ don't perform the bit test if the register's value can be >=
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"number of bits in right.location", because that generates a poison
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value in LLVM (and even anding it will 0 will keep it a poison value),
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and calculations using poison as input result in undefined behaviour }
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current_asmdata.getjumplabel(hl);
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current_asmdata.getjumplabel(hlend);
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hlcg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,uopdef,OC_AE,
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right.resultdef.packedbitsize,left.location.register,hl);
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hlcg.a_bit_test_reg_loc_reg(current_asmdata.CurrAsmList,
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uopdef,right.resultdef,uopdef,
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left.location.register,right.location,location.register);
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hlcg.a_jmp_always(current_asmdata.CurrAsmList,hlend);
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hlcg.a_label(current_asmdata.CurrAsmList,hl);
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hlcg.a_load_const_reg(current_asmdata.CurrAsmList,uopdef,0,location.register);
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hlcg.a_label(current_asmdata.CurrAsmList,hlend);
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end;
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procedure tllvmcasenode.genlinearlist(hp: pcaselabel);
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begin
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{ genlinearlist constantly updates the case value in the register,
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which causes tons of spilling with LLVM due to the need to bring
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it back into SSA form. LLVM will recognise and optimise the linear
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cmp list just as well (or even better), while the code that FPC
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has to generate is much smaller (no spilling) }
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genlinearcmplist(hp);
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end;
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begin
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cinnode:=tllvminnode;
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ccasenode:=tllvmcasenode;
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end.
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