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https://gitlab.com/freepascal.org/fpc/source.git
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361 lines
11 KiB
ObjectPascal
361 lines
11 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate x86 code for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx86mat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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tx86unaryminusnode = class(tcgunaryminusnode)
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;override;
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{$endif SUPPORT_MMX}
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procedure second_float;override;
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function pass_1:tnode;override;
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end;
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tx86notnode = class(tcgnotnode)
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procedure second_boolean;override;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;override;
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{$endif SUPPORT_MMX}
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end;
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implementation
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uses
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systems,
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cutils,verbose,globals,
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symconst,aasmbase,aasmtai,defutil,
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cgbase,pass_1,pass_2,
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ncon,
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cpubase,
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cga,ncgutil,cgobj,cgx86,cgutils;
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{*****************************************************************************
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TI386UNARYMINUSNODE
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*****************************************************************************}
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function tx86unaryminusnode.pass_1 : tnode;
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begin
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result:=nil;
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firstpass(left);
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if codegenerror then
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exit;
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if (left.resulttype.def.deftype=floatdef) then
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begin
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if use_sse(left.resulttype.def) then
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begin
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if (registersmm < 1) then
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registersmm := 1;
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expectloc:=LOC_MMREGISTER;
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end
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else
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begin
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if (registersfpu < 1) then
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registersfpu := 1;
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expectloc:=LOC_FPUREGISTER;
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end;
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end
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{$ifdef SUPPORT_MMX}
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else
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if (cs_mmx in aktlocalswitches) and
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is_mmx_able_array(left.resulttype.def) then
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begin
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registersint:=left.registersint;
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registersfpu:=left.registersfpu;
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registersmmx:=left.registersmmx;
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if (left.location.loc<>LOC_MMXREGISTER) and
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(registersmmx<1) then
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registersmmx:=1;
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end
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{$endif SUPPORT_MMX}
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else
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inherited pass_1;
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end;
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{$ifdef SUPPORT_MMX}
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procedure tx86unaryminusnode.second_mmx;
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var
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op : tasmop;
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hreg : tregister;
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begin
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secondpass(left);
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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hreg:=cg.getmmxregister(exprasmlist,OS_M64);
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emit_reg_reg(A_PXOR,S_NO,hreg,hreg);
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case left.location.loc of
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LOC_MMXREGISTER:
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begin
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location.register:=left.location.register;
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end;
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LOC_CMMXREGISTER:
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begin
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location.register:=cg.getmmxregister(exprasmlist,OS_M64);
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emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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reference_release(exprasmlist,left.location.reference);
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location.register:=cg.getmmxregister(exprasmlist,OS_M64);
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emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
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end;
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else
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internalerror(200203225);
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end;
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if cs_mmx_saturation in aktlocalswitches then
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case mmx_type(resulttype.def) of
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mmxs8bit:
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op:=A_PSUBSB;
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mmxu8bit:
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op:=A_PSUBUSB;
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mmxs16bit,mmxfixed16:
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op:=A_PSUBSW;
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mmxu16bit:
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op:=A_PSUBUSW;
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end
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else
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case mmx_type(resulttype.def) of
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mmxs8bit,mmxu8bit:
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op:=A_PSUBB;
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mmxs16bit,mmxu16bit,mmxfixed16:
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op:=A_PSUBW;
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mmxs32bit,mmxu32bit:
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op:=A_PSUBD;
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end;
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emit_reg_reg(op,S_NO,location.register,hreg);
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cg.ungetregister(exprasmlist,hreg);
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emit_reg_reg(A_MOVQ,S_NO,hreg,location.register);
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end;
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{$endif SUPPORT_MMX}
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procedure tx86unaryminusnode.second_float;
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var
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reg : tregister;
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href : treference;
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l1 : tasmlabel;
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begin
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secondpass(left);
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if expectloc=LOC_MMREGISTER then
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begin
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location_force_mmregscalar(exprasmlist,left.location,false);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resulttype.def));
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{ make life of register allocator easier }
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location.register:=cg.getmmregister(exprasmlist,OS_M128);
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cg.a_loadmm_reg_reg(exprasmlist,def_cgsize(resulttype.def),def_cgsize(resulttype.def),left.location.register,location.register,mms_movescalar);
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reg:=cg.getmmregister(exprasmlist,OS_M128);
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objectlibrary.getdatalabel(l1);
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consts.concat(Tai_label.Create(l1));
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case def_cgsize(resulttype.def) of
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OS_F32:
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consts.concat(tai_const.create_32bit(longint(1 shl 31)));
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OS_F64:
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begin
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consts.concat(tai_const.create_32bit(0));
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consts.concat(tai_const.create_32bit(-(1 shl 31)));
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end
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else
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internalerror(2004110215);
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end;
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reference_reset_symbol(href,l1,0);
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cg.a_loadmm_ref_reg(exprasmlist,def_cgsize(resulttype.def),def_cgsize(resulttype.def),href,reg,mms_movescalar);
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cg.a_opmm_reg_reg(exprasmlist,OP_XOR,left.location.size,reg,location.register,nil);
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end
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else
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=NR_ST;
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cg.a_loadfpu_ref_reg(exprasmlist,
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def_cgsize(left.resulttype.def),
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left.location.reference,location.register);
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emit_none(A_FCHS,S_NO);
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end;
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LOC_FPUREGISTER,
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LOC_CFPUREGISTER:
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begin
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{ "load st,st" is ignored by the code generator }
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cg.a_loadfpu_reg_reg(exprasmlist,left.location.size,left.location.register,NR_ST);
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location.register:=NR_ST;
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emit_none(A_FCHS,S_NO);
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end;
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else
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internalerror(200312241);
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end;
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end;
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end;
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{*****************************************************************************
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TX86NOTNODE
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*****************************************************************************}
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procedure tx86notnode.second_boolean;
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var
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hl : tasmlabel;
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opsize : tcgsize;
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begin
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opsize:=def_cgsize(resulttype.def);
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if left.expectloc=LOC_JUMP then
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begin
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location_reset(location,LOC_JUMP,OS_NO);
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hl:=truelabel;
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truelabel:=falselabel;
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falselabel:=hl;
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secondpass(left);
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maketojumpbool(exprasmlist,left,lr_load_regvars);
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hl:=truelabel;
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truelabel:=falselabel;
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falselabel:=hl;
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end
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else
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begin
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{ the second pass could change the location of left }
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{ if it is a register variable, so we've to do }
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{ this before the case statement }
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secondpass(left);
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case left.expectloc of
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LOC_FLAGS :
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=left.location.resflags;
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inverse_flags(location.resflags);
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end;
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LOC_CONSTANT,
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LOC_REGISTER,
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LOC_CREGISTER,
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LOC_REFERENCE,
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LOC_CREFERENCE :
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begin
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location_force_reg(exprasmlist,left.location,opsize,true);
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emit_reg_reg(A_TEST,TCGSize2Opsize[opsize],left.location.register,left.location.register);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_E;
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end;
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else
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internalerror(200203224);
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end;
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end;
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end;
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{$ifdef SUPPORT_MMX}
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procedure tx86notnode.second_mmx;
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var hreg,r:Tregister;
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begin
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secondpass(left);
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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r:=cg.getintregister(exprasmlist,OS_INT);
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emit_const_reg(A_MOV,S_L,longint($ffffffff),r);
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{ load operand }
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case left.location.loc of
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LOC_MMXREGISTER:
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location_copy(location,left.location);
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LOC_CMMXREGISTER:
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begin
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location.register:=cg.getmmxregister(exprasmlist,OS_M64);
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emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location_release(exprasmlist,left.location);
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location.register:=cg.getmmxregister(exprasmlist,OS_M64);
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emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
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end;
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end;
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{ load mask }
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hreg:=cg.getmmxregister(exprasmlist,OS_M64);
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emit_reg_reg(A_MOVD,S_NO,r,hreg);
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cg.ungetregister(exprasmlist,r);
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{ lower 32 bit }
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emit_reg_reg(A_PXOR,S_D,hreg,location.register);
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{ shift mask }
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emit_const_reg(A_PSLLQ,S_NO,32,hreg);
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{ higher 32 bit }
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cg.ungetregister(exprasmlist,hreg);
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emit_reg_reg(A_PXOR,S_D,hreg,location.register);
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end;
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{$endif SUPPORT_MMX}
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end.
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{
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$Log$
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Revision 1.9 2004-11-03 10:11:13 peter
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* fix possible range error
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Revision 1.8 2004/11/02 18:23:16 florian
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* fixed -<sse register>
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* information about simple moves for sse is given to the register allocator
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Revision 1.7 2004/10/31 21:45:04 peter
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* generic tlocation
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* move tlocation to cgutils
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Revision 1.6 2004/09/25 14:23:55 peter
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* ungetregister is now only used for cpuregisters, renamed to
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ungetcpuregister
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* renamed (get|unget)explicitregister(s) to ..cpuregister
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* removed location-release/reference_release
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Revision 1.5 2004/06/20 08:55:32 florian
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* logs truncated
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Revision 1.4 2004/06/16 20:07:11 florian
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* dwarf branch merged
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Revision 1.3.2.1 2004/04/27 18:18:26 peter
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* aword -> aint
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Revision 1.3 2004/02/03 22:32:54 peter
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* renamed xNNbittype to xNNinttype
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* renamed registers32 to registersint
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* replace some s32bit,u32bit with torddef([su]inttype).def.typ
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Revision 1.2 2004/01/20 12:59:37 florian
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* common addnode code for x86-64 and i386
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}
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