mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-05-01 00:53:44 +02:00
387824c1ee
Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions. Fixed emission of regsets of S and D registers above 15. Fixed assembler reader for RRX shiftmode. There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader. git-svn-id: branches/laksen/armiw@29277 -
1119 lines
30 KiB
Plaintext
1119 lines
30 KiB
Plaintext
;
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; Table of assembler instructions for Free Pascal
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; adapted from Netwide Assembler by Florian Klaempfl
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;
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;
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; The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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; Julian Hall. All rights reserved. The software is
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; redistributable under the licence given in the file "Licence"
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; distributed in the NASM archive.
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;
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; Format of file: all four fields must be present on every functional
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; line. Hence `void' for no-operand instructions, and `\0' for such
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; as EQU. If the last three fields are all `ignore', no action is
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; taken except to register the opcode as being present.
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;
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;
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; 'ignore' means no instruc
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; 'void' means instruc with zero operands
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;
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; Third field has a first byte indicating how to
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; put together the bits, and then some codes
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; that may be used at will (see assemble.c)
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;
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; \1 - 24 bit pc-rel offset [B, BL]
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; \2 - 24 bit imm value [SWI]
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; \3 - 3 byte code [BX]
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;
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; \4 - reg,reg,reg [AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC]
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; \5 - reg,reg,reg,<shift>reg [-"-]
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; \6 - reg,reg,reg,<shift>#imm [-"-]
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; \7 - reg,reg,#imm [-"-]
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;
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; \x8 - reg,reg [MOV,MVN]
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; \x9 - reg,reg,<shift>reg [-"-]
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; \xA - reg,reg,<shift>#imm [-"-]
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; \xB - reg,#imm [-"-]
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;
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; \xC - reg,reg [CMP,CMN,TEQ,TST]
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; \xD - reg,reg,<shift>reg [-"-]
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; \xE - reg,reg,<shift>#imm [-"-]
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; \xF - reg,#imm [-"-]
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;
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; \xFx - floating point instructions
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; Floating point instruction format information, taken from the linux kernel,
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; for detailed tables, see aasmcpu.pas
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;
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; ARM Floating Point Instruction Classes
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; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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; |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
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; |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
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; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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; |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
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; |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
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; |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
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; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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;
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; CPDT data transfer instructions
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; LDF, STF, LFM (copro 2), SFM (copro 2)
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;
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; CPDO dyadic arithmetic instructions
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; ADF, MUF, SUF, RSF, DVF, RDF,
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; POW, RPW, RMF, FML, FDV, FRD, POL
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;
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; CPDO monadic arithmetic instructions
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; MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
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; SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
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;
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; CPRT joint arithmetic/data transfer instructions
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; FIX (arithmetic followed by load/store)
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; FLT (load/store followed by arithmetic)
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; CMF, CNF CMFE, CNFE (comparisons)
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; WFS, RFS (write/read floating point status register)
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; WFC, RFC (write/read floating point control register)
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; \xF0 - CPDT
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; code 1: copro (1/2)
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; code 2: load/store bit
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; \xF1 - CPDO
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; \xF2 - CPDO monadic
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; \xF3 - CPRT
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; \xF4 - CPRT comparison
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;
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; \xFF - fix me
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;
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[NONE]
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void void none
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[ADCcc]
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reg32,reg32,reg32 \4\x0\xA0 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\xA0 ARM32,ARMv4
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reg32,reg32,immshifter \7\x2\xA0 ARM32,ARMv4
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[ADDcc]
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reg32,reg32,reg32 \4\x0\x80 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\x80 ARM32,ARMv4
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reg32,reg32,immshifter \7\x2\x80 ARM32,ARMv4
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[ADFcc]
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[ADRcc]
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;reg32,immshifter \x33\x2\x0F ARM32,ARMv4
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;reg32,imm32 \x33\x2\x0F ARM32,ARMv4
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reg32,memam2 \x33\x2\x0F ARM32,ARMv4
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[ANDcc]
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reg32,reg32,reg32 \x4\x0\x00 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \x6\x0\x00 ARM32,ARMv4
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reg32,reg32,immshifter \x7\x2\x00 ARM32,ARMv4
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[Bcc]
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imm24 \x1\x0A ARM32,ARMv4
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mem32 \x1\x0A ARM32,ARMv4
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[BICcc]
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reg32,reg32,reg32 \x6\x1\xC0 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \x6\x1\xC0 ARM32,ARMv4
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reg32,reg32,immshifter \x7\x3\xC0 ARM32,ARMv4
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[BLcc]
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imm24 \x1\x0B ARM32,ARMv4
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mem32 \x1\x0B ARM32,ARMv4
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[BLX]
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imm24 \x28\xB ARM32,ARMv5T
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mem32 \x28\xB ARM32,ARMv5T
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reg32 \3\x01\x2F\xFF\x30 ARM32,ARMv5T
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[BKPTcc]
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imm \x31\x1\x20\x70 ARM32,ARMv5T
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immshifter \x31\x1\x20\x70 ARM32,ARMv5T
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[BXcc]
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reg32 \3\x01\x2F\xFF\x10 ARM32,ARMv4T
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[CDP]
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reg8,reg8 \300\1\x10\101 ARM32,ARMv4
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[CMNcc]
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reg32,reg32 \xC\x1\x60 ARM32,ARMv4
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reg32,reg32,shifterop \xE\x1\x60 ARM32,ARMv4
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reg32,immshifter \xF\x1\x60 ARM32,ARMv4
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[CMPcc]
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reg32,reg32 \xC\x1\x40 ARM32,ARMv4
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reg32,reg32,shifterop \xE\x1\x40 ARM32,ARMv4
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reg32,immshifter \xF\x3\x40 ARM32,ARMv4
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[CMFcc]
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[CMFEcc]
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[STFcc]
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[LDFcc]
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[LFMcc]
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reg32,imm8,fpureg \xF0\x02\x01 FPA
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[CLZcc]
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reg32,reg32 \x32\x01\x6F\xF\x10 ARM32,ARMv4
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[CPS]
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[CPSID]
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[CPSIE]
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[EORcc]
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reg32,reg32,reg32 \4\x0\x20 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\x20 ARM32,ARMv4
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reg32,reg32,immshifter \7\x2\x20 ARM32,ARMv4
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[LDC]
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reg32,reg32 \321\300\1\x11\101 ARM32,ARMv4
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[LDMcc]
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memam4,reglist \x26\x81 ARM32,ARMv4
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reg32,reglist \x26\x81 ARM32,ARMv4
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[LDRBTcc]
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reg32,memam2 \x17\x04\x70 ARM32,ARMv4
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reg32,immshifter \x17\x04\x70 ARM32,ARMv4
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[LDRBcc]
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reg32,memam2 \x17\x04\x50 ARM32,ARMv4
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[LDRcc]
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reg32,memam2 \x17\x04\x10 ARM32,ARMv4
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[LDRHcc]
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reg32,memam2 \x22\x10\xB0 ARM32,ARMv4
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[LDRSBcc]
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reg32,memam2 \x22\x10\xD0 ARM32,ARMv4
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reg32,reg32 \x23\x50\xD0 ARM32,ARMv4
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reg32,reg32,imm32 \x24\x50\xD0 ARM32,ARMv4
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reg32,reg32,reg32 \x25\x10\xD0 ARM32,ARMv4
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[LDRSHcc]
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reg32,memam2 \x22\x10\xF0 ARM32,ARMv4
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[LDRTcc]
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reg32,memam2 \x17\x04\x30 ARM32,ARMv4
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[MCRcc]
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regf,immshifter,reg32,regf,regf \x1C\xE\x0\x1 ARM32,ARMv4
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regf,immshifter,reg32,regf,regf,immshifter \x1C\xE\x0\x1 ARM32,ARMv4
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[MCR2cc]
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regf,immshifter,reg32,regf,regf \x1C\xFE\x0\x1 ARM32,ARMv5T
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regf,immshifter,reg32,regf,regf,immshifter \x1C\xFE\x0\x1 ARM32,ARMv5T
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[MRCcc]
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regf,immshifter,reg32,regf,regf \x1C\xE\x10\x1 ARM32,ARMv4
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regf,immshifter,reg32,regf,regf,immshifter \x1C\xE\x10\x1 ARM32,ARMv4
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[MRC2cc]
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regf,immshifter,reg32,regf,regf \x1C\xFE\x10\x1 ARM32,ARMv5T
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regf,immshifter,reg32,regf,regf,immshifter \x1C\xFE\x10\x1 ARM32,ARMv5T
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[MCRRcc]
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regf,immshifter,reg32,reg32,regf \x1D\xC\x40\x0 ARM32,ARMv5TE
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[MCRR2cc]
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regf,immshifter,reg32,reg32,regf \x1D\xFC\x40\x0 ARM32,ARMv6
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[MRRCcc]
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regf,immshifter,reg32,reg32,regf \x1D\xC\x50\x0 ARM32,ARMv5TE
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[MRRC2cc]
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regf,immshifter,reg32,reg32,regf \x1D\xFC\x50\x0 ARM32,ARMv6
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[MLAcc]
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reg32,reg32,reg32,reg32 \x15\x00\x20\x9 ARM32,ARMv4
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[MOVcc]
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reg32,shifterop \x8\x1\xA0 ARM32,ARMv4
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reg32,reg32,shifterop \xA\x1\xA0 ARM32,ARMv4
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reg32,immshifter \xB\x1\xA0 ARM32,ARMv4
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[MRScc]
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reg32,regf \x10\x01\x0F ARM32,ARMv4
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[MSRcc]
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regf,reg32 \x12\x01\x28\xF0 ARM32,ARMv4
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regf,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
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[MULcc]
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reg32,reg32,reg32 \x14\x00\x00\x90 ARM32,ARMv4
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[MVFcc]
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fpureg,fpureg \xF2 FPA
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fpureg,immfpu \xF2 FPA
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[MVNcc]
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reg32,reg32 \x8\x1\xE0 ARM32,ARMv4
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reg32,reg32,shifterop \xA\x1\xE0 ARM32,ARMv4
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reg32,immshifter \xB\x1\xE0 ARM32,ARMv4
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[VMOVcc]
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vreg,vreg \x40\xE\xB0\xA\x40 ARM32,VFPv2
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reg32,vreg \x40\xE\x10\xA\x10 ARM32,VFPv2
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vreg,reg32 \x40\xE\x00\xA\x10 ARM32,VFPv2
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reg32,reg32,vreg,vreg \x40\xC\x50\xA\x10 ARM32,VFPv2
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vreg,vreg,reg32,reg32 \x40\xC\x40\xA\x10 ARM32,VFPv2
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reg32,reg32,vreg \x40\xC\x50\xB\x10 ARM32,VFPv2
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vreg,reg32,reg32 \x40\xC\x40\xB\x10 ARM32,VFPv2
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[NOP]
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void \x2F\x03\x20\xF0\x0 ARM32,ARMv6K
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[ORRcc]
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reg32,reg32,reg32 \4\x1\x80 ARM32,ARMv4
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reg32,reg32,reg32,reg32 \5\x1\x80 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x1\x80 ARM32,ARMv4
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reg32,reg32,immshifter \7\x3\x80 ARM32,ARMv4
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[RSBcc]
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reg32,reg32,reg32 \6\x0\x60 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\x60 ARM32,ARMv4
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reg32,reg32,immshifter \7\x0\x60 ARM32,ARMv4
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[RSCcc]
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reg32,reg32,reg32 \4\x0\xE0 ARM32,ARMv4
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reg32,reg32,reg32,reg32 \5\x0\xE0 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\xE0 ARM32,ARMv4
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reg32,reg32,immshifter \7\x2\xE0 ARM32,ARMv4
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[SBCcc]
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reg32,reg32,reg32 \4\x0\xC0 ARM32,ARMv4
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reg32,reg32,reg32,reg32 \5\x0\xC0 ARM32,ARMv4
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reg32,reg32,reg32,imm \6\x0\xC0 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\xC0 ARM32,ARMv4
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reg32,reg32,immshifter \7\x2\xC0 ARM32,ARMv4
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[SFMcc]
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reg32,imm8,fpureg \xF0\x02\x00 FPA
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[SINcc]
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[SMLALcc]
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reg32,reg32,reg32,reg32 \x16\x00\xE0\x9 ARM32,ARMv4
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[SMULLcc]
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reg32,reg32,reg32,reg32 \x16\x00\xC0\x9 ARM32,ARMv4
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[STMcc]
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memam4,reglist \x26\x80 ARM32,ARMv4
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reg32,reglist \x26\x80 ARM32,ARMv4
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[STRcc]
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reg32,memam2 \x17\x04\x00 ARM32,ARMv4
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[STRBcc]
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reg32,memam2 \x17\x04\x40 ARM32,ARMv4
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[STRBTcc]
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reg32,memam2 \x17\x04\x60 ARM32,ARMv4
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reg32,immshifter \x17\x04\x60 ARM32,ARMv4
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[STRHcc]
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reg32,memam2 \x22\x00\xB0 ARM32,ARMv4
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[STRTcc]
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reg32,memam2 \x17\x04\x20 ARM32,ARMv4
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[SUBcc]
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reg32,reg32,shifterop \x4\x0\x40 ARM32,ARMv4
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reg32,reg32,immshifter \x4\x0\x40 ARM32,ARMv4
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reg32,reg32,reg32 \x4\x0\x40 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \x6\x0\x40 ARM32,ARMv4
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[SWIcc]
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imm \x2\x0F ARM32,ARMv4
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immshifter \x2\x0F ARM32,ARMv4
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[SWPcc]
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reg32,reg32,memam2 \x27\x10\x09 ARM32,ARMv4
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[SWPBcc]
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reg32,reg32,memam2 \x27\x14\x09 ARM32,ARMv4
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[TEQcc]
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reg32,reg32 \xC\x1\x20 ARM32,ARMv4
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reg32,reg32,reg32 \xD\x1\x20 ARM32,ARMv4
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reg32,reg32,shifterop \xE\x1\x20 ARM32,ARMv4
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reg32,immshifter \xF\x3\x20 ARM32,ARMv4
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[TSTcc]
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reg32,reg32 \xC\x1\x00 ARM32,ARMv4
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reg32,reg32,reg32 \xD\x1\x00 ARM32,ARMv4
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reg32,reg32,shifterop \xE\x1\x00 ARM32,ARMv4
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reg32,immshifter \xF\x3\x00 ARM32,ARMv4
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[UMLALcc]
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reg32,reg32,reg32,reg32 \x16\x00\xA0\x9 ARM32,ARMv4
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[UMULLcc]
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reg32,reg32,reg32,reg32 \x16\x00\x80\x9 ARM32,ARMv4
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[WFScc]
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; EDSP instructions
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[LDRDcc]
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reg32,reg32,memam2 \x19\x0\x0\x0\xD0 ARM32,ARMv4
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[PLD]
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memam2 \x25\xF5\x50\xF0\x0 ARM32,ARMv5TE
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[PLDW]
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memam2 \x25\xF5\x10\xF0\x0 ARM32,ARMv7
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[QADDcc]
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reg32,reg32,reg32 \x1A\x01\x00\x05 ARM32,ARMv5TE
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[QDADDcc]
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reg32,reg32,reg32 \x1A\x01\x40\x05 ARM32,ARMv5TE
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[QDSUBcc]
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reg32,reg32,reg32 \x1A\x01\x60\x05 ARM32,ARMv5TE
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[QSUBcc]
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reg32,reg32,reg32 \x1A\x01\x20\x05 ARM32,ARMv5TE
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[SMLABBcc]
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reg32,reg32,reg32,reg32 \x15\x01\x00\x8 ARM32,ARMv5TE
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[SMLABTcc]
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reg32,reg32,reg32,reg32 \x15\x01\x00\xC ARM32,ARMv5TE
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[SMLATBcc]
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reg32,reg32,reg32,reg32 \x15\x01\x00\xA ARM32,ARMv5TE
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[SMLATTcc]
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reg32,reg32,reg32,reg32 \x15\x01\x00\xE ARM32,ARMv5TE
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[SMLALBBcc]
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reg32,reg32,reg32,reg32 \x16\x01\x40\x8 ARM32,ARMv5TE
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[SMLALBTcc]
|
|
reg32,reg32,reg32,reg32 \x16\x01\x40\xC ARM32,ARMv5TE
|
|
|
|
[SMLALTBcc]
|
|
reg32,reg32,reg32,reg32 \x16\x01\x40\xA ARM32,ARMv5TE
|
|
|
|
[SMLALTTcc]
|
|
reg32,reg32,reg32,reg32 \x16\x01\x40\xE ARM32,ARMv5TE
|
|
|
|
[SMLAWBcc]
|
|
|
|
[SMLAWTcc]
|
|
|
|
[VLDMcc]
|
|
memam4,reglist \x44\xC\x10\xA ARM32,VFPv2
|
|
reg32,reglist \x44\xC\x10\xA ARM32,VFPv2
|
|
|
|
[VSTMcc]
|
|
memam4,reglist \x44\xC\x00\xA ARM32,VFPv2
|
|
reg32,reglist \x44\xC\x00\xA ARM32,VFPv2
|
|
|
|
[VPOP]
|
|
reglist \x44\xC\xBD\xA ARM32,VFPv2
|
|
|
|
[VPUSH]
|
|
reglist \x44\xD\x2D\xA ARM32,VFPv2
|
|
|
|
[VLDRcc]
|
|
vreg,memam2 \x45\xD\x10\xA ARM32,VFPv2
|
|
|
|
[VSTRcc]
|
|
vreg,memam2 \x45\xD\x0\xA ARM32,VFPv2
|
|
|
|
[SMULBBcc]
|
|
reg32,reg32,reg32 \x15\x01\x60\x8\x0 ARM32,ARMv5TE
|
|
|
|
[SMULBTcc]
|
|
reg32,reg32,reg32 \x15\x01\x60\xC\x0 ARM32,ARMv5TE
|
|
|
|
[SMULTBcc]
|
|
reg32,reg32,reg32 \x15\x01\x60\xA\x0 ARM32,ARMv5TE
|
|
|
|
[SMULTTcc]
|
|
reg32,reg32,reg32 \x15\x01\x60\xE\x0 ARM32,ARMv5TE
|
|
|
|
[SMULWBcc]
|
|
reg32,reg32,reg32 \x14\x1\x20\xA0 ARM32,ARMv5TE
|
|
|
|
[SMULWTcc]
|
|
reg32,reg32,reg32 \x14\x1\x20\xE0 ARM32,ARMv5TE
|
|
|
|
[STRDcc]
|
|
reg32,reg32,memam2 \x19\x0\x0\x0\xF0 ARM32,ARMv4
|
|
|
|
[LDRHTcc]
|
|
reg32,memam2 \x19\x0\x30\x0\xB0 ARM32,ARMv4
|
|
|
|
[STRHTcc]
|
|
reg32,memam2 \x1E\x0\x20\x0\xB0 ARM32,ARMv4
|
|
|
|
[LDRSBTcc]
|
|
reg32,memam2 \x1E\x0\x30\x0\xD0 ARM32,ARMv4
|
|
|
|
[STRSBTcc]
|
|
reg32,memam2 \x1E\x0\x30\x0\xD0 ARM32,ARMv4
|
|
|
|
[LDRSHTcc]
|
|
reg32,memam2 \x1E\x0\x30\x0\xF0 ARM32,ARMv4
|
|
|
|
[STRSHTcc]
|
|
reg32,memam2 \x1E\x0\x30\x0\xF0 ARM32,ARMv4
|
|
|
|
[FSTDcc]
|
|
|
|
[FSTMcc]
|
|
|
|
[FSTScc]
|
|
|
|
; ARMv6
|
|
|
|
[BFCcc]
|
|
reg32,immshifter,immshifter \x2D\x7\xC0\x0\x1F ARM32,ARMv4
|
|
reg32,immshifter,imm32 \x2D\x7\xC0\x0\x1F ARM32,ARMv4
|
|
|
|
[BFIcc]
|
|
reg32,reg32,immshifter,immshifter \x2D\x7\xC0\x0\x10 ARM32,ARMv4
|
|
reg32,reg32,immshifter,imm32 \x2D\x7\xC0\x0\x10 ARM32,ARMv4
|
|
|
|
[CLREX]
|
|
void \x2F\xF5\x7F\xF0\x1F ARM32,ARMv6K
|
|
|
|
[LDREXcc]
|
|
reg32,memam6 \x18\x01\x90\x0F\x9F ARM32,ARMv4
|
|
[LDREXBcc]
|
|
reg32,memam6 \x18\x01\xD0\x0F\x9F ARM32,ARMv4
|
|
[LDREXDcc]
|
|
reg32,reg32,memam6 \x18\x01\xB0\x0F\x9F ARM32,ARMv4
|
|
[LDREXHcc]
|
|
reg32,memam6 \x18\x01\xF0\x0F\x9F ARM32,ARMv4
|
|
|
|
[STREXcc]
|
|
reg32,reg32,memam6 \x18\x01\x80\x0F\x90 ARM32,ARMv4
|
|
[STREXBcc]
|
|
reg32,reg32,memam6 \x18\x01\xC0\x0F\x90 ARM32,ARMv4
|
|
[STREXDcc]
|
|
reg32,reg32,reg32,memam6 \x18\x01\xA0\x0F\x90 ARM32,ARMv4
|
|
[STREXHcc]
|
|
reg32,reg32,memam6 \x18\x01\xE0\x0F\x90 ARM32,ARMv4
|
|
|
|
[MLScc]
|
|
reg32,reg32,reg32,reg32 \x15\x00\x60\x9 ARM32,ARMv6T2
|
|
|
|
[PKHBTcc]
|
|
reg32,reg32,reg32 \x16\x6\x80\x1 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x6\x80\x1 ARM32,ARMv6
|
|
|
|
[PKHTBcc]
|
|
reg32,reg32,reg32 \x16\x6\x80\x1 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x6\x80\x5 ARM32,ARMv6
|
|
|
|
[PLI]
|
|
memam2 \x25\xF4\x50\xF0\x0 ARM32,ARMv7
|
|
|
|
[QADD16cc]
|
|
reg32,reg32,reg32 \x16\x06\x20\xF1 ARM32,ARMv6
|
|
[QADD8cc]
|
|
reg32,reg32,reg32 \x16\x06\x20\xF9 ARM32,ARMv6
|
|
[QASXcc]
|
|
reg32,reg32,reg32 \x16\x06\x20\xF3 ARM32,ARMv6
|
|
[QSAXcc]
|
|
reg32,reg32,reg32 \x16\x06\x20\xF5 ARM32,ARMv6
|
|
[QSUB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x20\xF7 ARM32,ARMv6
|
|
[QSUB8cc]
|
|
reg32,reg32,reg32 \x16\x06\x20\xFF ARM32,ARMv6
|
|
|
|
[RBITcc]
|
|
reg32,reg32 \x32\x6\xFF\xF\x30 ARM32,ARMv6T2
|
|
|
|
[REVcc]
|
|
reg32,reg32 \x32\x6\xBF\xF\x30 ARM32,ARMv6
|
|
|
|
[REV16cc]
|
|
reg32,reg32 \x32\x6\xBF\xF\xB0 ARM32,ARMv6
|
|
|
|
[REVSHcc]
|
|
reg32,reg32 \x32\x6\xFF\xF\xB0 ARM32,ARMv6
|
|
|
|
[SADD16cc]
|
|
reg32,reg32,reg32 \x16\x06\x10\xF1 ARM32,ARMv6
|
|
|
|
[SADD8cc]
|
|
reg32,reg32,reg32 \x16\x06\x10\xF9 ARM32,ARMv6
|
|
|
|
[SASXcc]
|
|
reg32,reg32,reg32 \x16\x06\x10\xF3 ARM32,ARMv6
|
|
|
|
[SBFXcc]
|
|
reg32,reg32,immshifter,immshifter \x2D\x7\xA0\x0\x50 ARM32,ARMv6T2
|
|
|
|
[SELcc]
|
|
reg32,reg32,reg32 \x16\x06\x80\xFB ARM32,ARMv6
|
|
|
|
[SETEND]
|
|
immshifter \x2B\xF1\x01\x0\x0 ARM32,ARMv6
|
|
|
|
[SEVcc]
|
|
void \x2F\x3\x20\xF0\x4 ARM32,ARMv6K
|
|
|
|
[ASRcc]
|
|
reg32,reg32,reg32 \x30\x1\xA0\x0\x50 ARM32,ARMv4
|
|
reg32,reg32,immshifter \x30\x1\xA0\x0\x40 ARM32,ARMv4
|
|
|
|
[LSRcc]
|
|
reg32,reg32,reg32 \x30\x1\xA0\x0\x30 ARM32,ARMv4
|
|
reg32,reg32,immshifter \x30\x1\xA0\x0\x20 ARM32,ARMv4
|
|
|
|
[LSLcc]
|
|
reg32,reg32,reg32 \x30\x1\xA0\x0\x10 ARM32,ARMv4
|
|
reg32,reg32,immshifter \x30\x1\xA0\x0\x00 ARM32,ARMv4
|
|
|
|
[RORcc]
|
|
reg32,reg32,reg32 \x30\x1\xA0\x0\x70 ARM32,ARMv4
|
|
reg32,reg32,immshifter \x30\x1\xA0\x0\x60 ARM32,ARMv4
|
|
|
|
[RRXcc]
|
|
reg32,reg32 \x30\x1\xA0\x0\x60 ARM32,ARMv4
|
|
|
|
[UMAALcc]
|
|
reg32,reg32,reg32,reg32 \x16\x0\x40\x9 ARM32,ARMv6
|
|
|
|
[SHADD16cc]
|
|
reg32,reg32,reg32 \x16\x06\x30\xF1 ARM32,ARMv6
|
|
|
|
[SHADD8cc]
|
|
reg32,reg32,reg32 \x16\x06\x30\xF9 ARM32,ARMv6
|
|
|
|
[SHASXcc]
|
|
reg32,reg32,reg32 \x16\x06\x30\xF3 ARM32,ARMv6
|
|
|
|
[SHSAXcc]
|
|
reg32,reg32,reg32 \x16\x06\x30\xF5 ARM32,ARMv6
|
|
|
|
[SHSUB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x30\xF7 ARM32,ARMv6
|
|
|
|
[SHSUB8cc]
|
|
reg32,reg32,reg32 \x16\x06\x30\xFF ARM32,ARMv6
|
|
|
|
[SMLADcc]
|
|
reg32,reg32,reg32,reg32 \x15\x7\x00\x1 ARM32,ARMv6
|
|
|
|
[SMLALDcc]
|
|
reg32,reg32,reg32,reg32 \x16\x7\x40\x1 ARM32,ARMv4
|
|
|
|
[SMLSDcc]
|
|
reg32,reg32,reg32,reg32 \x15\x7\x00\x5 ARM32,ARMv6
|
|
|
|
[SMLSLDcc]
|
|
reg32,reg32,reg32,reg32 \x16\x7\x40\x5 ARM32,ARMv6
|
|
|
|
[SMMLAcc]
|
|
reg32,reg32,reg32,reg32 \x15\x7\x50\x1 ARM32,ARMv6
|
|
|
|
[SMMLScc]
|
|
reg32,reg32,reg32,reg32 \x15\x7\x50\xD ARM32,ARMv6
|
|
|
|
[SMMULcc]
|
|
reg32,reg32,reg32 \x15\x7\x50\x1\xF ARM32,ARMv6
|
|
|
|
[SMUADcc]
|
|
reg32,reg32,reg32 \x15\x7\x00\x1\xF ARM32,ARMv6
|
|
|
|
[SMUSDcc]
|
|
reg32,reg32,reg32 \x15\x7\x00\x5\xF ARM32,ARMv6
|
|
|
|
[SRScc]
|
|
|
|
[SSATcc]
|
|
reg32,immshifter,reg32 \x2A\x6\xA0\x0\x10 ARM32,ARMv6
|
|
reg32,immshifter,reg32,shifterop \x2A\x6\xA0\x0\x10 ARM32,ARMv6
|
|
|
|
[SSAT16cc]
|
|
reg32,immshifter,reg32 \x2A\x6\xA0\xF\x30 ARM32,ARMv6
|
|
|
|
[SSAXcc]
|
|
reg32,reg32,reg32 \x16\x06\x10\xF5 ARM32,ARMv6
|
|
|
|
[SSUB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x10\xF7 ARM32,ARMv6
|
|
|
|
[SSUB8cc]
|
|
reg32,reg32,reg32 \x16\x06\x10\xFF ARM32,ARMv6
|
|
|
|
[SXTABcc]
|
|
reg32,reg32,reg32 \x16\x06\xA0\x07 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x06\xA0\x07 ARM32,ARMv6
|
|
|
|
[SXTAB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x80\x07 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x06\x80\x07 ARM32,ARMv6
|
|
|
|
[SXTAHcc]
|
|
reg32,reg32,reg32 \x16\x06\xB0\x07 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x06\xB0\x07 ARM32,ARMv6
|
|
|
|
[UBFXcc]
|
|
reg32,reg32,immshifter,immshifter \x2D\x7\xE0\x0\x50 ARM32,ARMv4
|
|
|
|
[UXTABcc]
|
|
reg32,reg32,reg32 \x16\x6\xE0\x7 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x6\xE0\x7 ARM32,ARMv6
|
|
|
|
[UXTAB16cc]
|
|
reg32,reg32,reg32 \x16\x6\xC0\x7 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x6\xC0\x7 ARM32,ARMv6
|
|
|
|
[UXTAHcc]
|
|
reg32,reg32,reg32 \x16\x6\xF0\x7 ARM32,ARMv6
|
|
reg32,reg32,reg32,shifterop \x16\x6\xF0\x7 ARM32,ARMv6
|
|
|
|
[SXTBcc]
|
|
reg32,reg32 \x1B\x6\xAF\x7 ARM32,ARMv6
|
|
reg32,reg32,shifterop \x1B\x6\xAF\x7 ARM32,ARMv6
|
|
|
|
[SXTB16cc]
|
|
reg32,reg32 \x1B\x6\x8F\x7 ARM32,ARMv6
|
|
reg32,reg32,shifterop \x1B\x6\x8F\x7 ARM32,ARMv6
|
|
|
|
[SXTHcc]
|
|
reg32,reg32 \x1B\x6\xBF\x7 ARM32,ARMv6
|
|
reg32,reg32,shifterop \x1B\x6\xBF\x7 ARM32,ARMv6
|
|
|
|
[UXTBcc]
|
|
reg32,reg32 \x1B\x6\xEF\x7 ARM32,ARMv6
|
|
reg32,reg32,shifterop \x1B\x6\xEF\x7 ARM32,ARMv6
|
|
|
|
[UXTB16cc]
|
|
reg32,reg32 \x1B\x6\xCF\x7 ARM32,ARMv6
|
|
reg32,reg32,shifterop \x1B\x6\xCF\x7 ARM32,ARMv6
|
|
|
|
[UXTHcc]
|
|
reg32,reg32 \x1B\x6\xFF\x7 ARM32,ARMv6
|
|
reg32,reg32,shifterop \x1B\x6\xFF\x7 ARM32,ARMv6
|
|
|
|
[UADD16cc]
|
|
reg32,reg32,reg32 \x16\x06\x50\xF1 ARM32,ARMv6
|
|
|
|
[UADD8cc]
|
|
reg32,reg32,reg32 \x16\x06\x50\xF9 ARM32,ARMv6
|
|
|
|
[UASXcc]
|
|
reg32,reg32,reg32 \x16\x06\x50\xF3 ARM32,ARMv6
|
|
|
|
[UHADD16cc]
|
|
reg32,reg32,reg32 \x16\x06\x70\xF1 ARM32,ARMv6
|
|
|
|
[UHADD8cc]
|
|
reg32,reg32,reg32 \x16\x06\x70\xF9 ARM32,ARMv6
|
|
|
|
[UHASXcc]
|
|
reg32,reg32,reg32 \x16\x06\x70\xF3 ARM32,ARMv6
|
|
|
|
[UHSAXcc]
|
|
reg32,reg32,reg32 \x16\x06\x70\xF5 ARM32,ARMv6
|
|
|
|
[UHSUB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x70\xF7 ARM32,ARMv6
|
|
|
|
[UHSUB8cc]
|
|
reg32,reg32,reg32 \x16\x06\x70\xFF ARM32,ARMv6
|
|
|
|
[UQADD16cc]
|
|
reg32,reg32,reg32 \x16\x06\x60\xF1 ARM32,ARMv6
|
|
|
|
[UQADD8]
|
|
reg32,reg32,reg32 \x16\x06\x60\xF9 ARM32,ARMv6
|
|
|
|
[UQASXcc]
|
|
reg32,reg32,reg32 \x16\x06\x60\xF3 ARM32,ARMv6
|
|
|
|
[UQSAXcc]
|
|
reg32,reg32,reg32 \x16\x06\x60\xF5 ARM32,ARMv6
|
|
|
|
[UQSUB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x60\xF7 ARM32,ARMv6
|
|
|
|
[UQSUB8cc]
|
|
reg32,reg32,reg32 \x16\x06\x60\xFF ARM32,ARMv6
|
|
|
|
[USAD8cc]
|
|
reg32,reg32,reg32 \x15\x07\x80\x01\xF ARM32,ARMv6
|
|
|
|
[USADA8cc]
|
|
reg32,reg32,reg32,reg32 \x15\x07\x80\x01 ARM32,ARMv6
|
|
|
|
[USATcc]
|
|
reg32,immshifter,reg32 \x2A\x6\xE0\x0\x10 ARM32,ARMv6
|
|
reg32,immshifter,reg32,shifterop \x2A\x6\xE0\x0\x10 ARM32,ARMv6
|
|
|
|
[USAT16cc]
|
|
reg32,immshifter,reg32 \x2A\x6\xE0\xF\x30 ARM32,ARMv6
|
|
|
|
[USAXcc]
|
|
reg32,reg32,reg32 \x16\x06\x50\xF5 ARM32,ARMv6
|
|
|
|
[USUB16cc]
|
|
reg32,reg32,reg32 \x16\x06\x50\xF7 ARM32,ARMv6
|
|
|
|
[USUB8cc]
|
|
reg32,reg32,reg32 \x16\x06\x50\xFF ARM32,ARMv6
|
|
|
|
[WFEcc]
|
|
void \x2F\x3\x20\xF0\x2 ARM32,ARMv6K
|
|
|
|
[WFIcc]
|
|
void \x2F\x3\x20\xF0\x3 ARM32,ARMv6K
|
|
|
|
[YIELDcc]
|
|
void \x2F\x3\x20\xF0\x1 ARM32,ARMv6K
|
|
|
|
;
|
|
; vfp instructions
|
|
;
|
|
[FABSDcc]
|
|
|
|
[FABSScc]
|
|
|
|
[FADDDcc]
|
|
|
|
[FADDScc]
|
|
|
|
[FCMPDcc]
|
|
|
|
[FCMPEDcc]
|
|
|
|
[FCMPEScc]
|
|
|
|
[FCMPEZDcc]
|
|
|
|
[FCMPEZScc]
|
|
|
|
[FCMPScc]
|
|
|
|
[FCMPZDcc]
|
|
|
|
[FCMPZScc]
|
|
|
|
[FCPYDcc]
|
|
|
|
[FCPYScc]
|
|
|
|
[FCVTDScc]
|
|
|
|
[FCVTSDcc]
|
|
|
|
[FDIVDcc]
|
|
|
|
[FDIVScc]
|
|
|
|
[FLDDcc]
|
|
|
|
[FLDMcc]
|
|
|
|
[FLDScc]
|
|
|
|
[FMACDcc]
|
|
|
|
[FMACScc]
|
|
|
|
[FMDHRcc]
|
|
|
|
[FMDLRcc]
|
|
|
|
[FMRDHcc]
|
|
|
|
[FMRDLcc]
|
|
|
|
[FMRScc]
|
|
|
|
[FMRXcc]
|
|
|
|
[FMSCDcc]
|
|
|
|
[FMSCScc]
|
|
|
|
[FMSRcc]
|
|
|
|
[FMSTATcc]
|
|
|
|
[FMULDcc]
|
|
|
|
[FMULScc]
|
|
|
|
[FMXRcc]
|
|
|
|
[FNEGDcc]
|
|
|
|
[FNEGScc]
|
|
|
|
[FNMACDcc]
|
|
|
|
[FNMACScc]
|
|
|
|
[FNMSCDcc]
|
|
|
|
[FNMSCScc]
|
|
|
|
[FNMULDcc]
|
|
|
|
[FNMULScc]
|
|
|
|
[FSITODcc]
|
|
|
|
[FSITOScc]
|
|
|
|
[FSQRTDcc]
|
|
|
|
[FSQRTScc]
|
|
|
|
[FSUBDcc]
|
|
|
|
[FSUBScc]
|
|
|
|
[FTOSIDcc]
|
|
|
|
[FTOSIScc]
|
|
|
|
[FTOUIDcc]
|
|
|
|
[FTOUIScc]
|
|
|
|
[FUITODcc]
|
|
|
|
[FUITOScc]
|
|
|
|
[FMDRRcc]
|
|
|
|
[FMRRDcc]
|
|
|
|
; Thumb-2
|
|
|
|
[POP]
|
|
reglist \x26\x8B ARM32,ARMv4
|
|
|
|
[PUSH]
|
|
reglist \x26\x80 ARM32,ARMv4
|
|
|
|
[SDIVcc]
|
|
|
|
[UDIVcc]
|
|
|
|
[MOVTcc]
|
|
reg32,imm \x2C\x3\x40 ARM32,ARMv6T2
|
|
reg32,immshifter \x2C\x3\x40 ARM32,ARMv6T2
|
|
|
|
[IT]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITT]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITEE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITTE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITET]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITTT]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITEEE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITTEE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITETE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITTTE]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITEET]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITTET]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITETT]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[ITTTT]
|
|
condition \xFE ARM32,ARMv4
|
|
|
|
[TBB]
|
|
[TBH]
|
|
|
|
[MOVW]
|
|
reg32,imm \x2C\x3\x0 ARM32,ARMv6T2
|
|
reg32,immshifter \x2C\x3\x0 ARM32,ARMv6T2
|
|
|
|
[CBZ]
|
|
[CBNZ]
|
|
|
|
; VFP
|
|
[VABScc]
|
|
vreg,vreg \x42\xE\xB0\xA\xC0 ARM32,VFPv2
|
|
|
|
[VADDcc]
|
|
vreg,vreg,vreg \x42\xE\x30\xA\x0 ARM32,VFPv2
|
|
|
|
[VCMPcc]
|
|
vreg,vreg \x42\xE\xB4\xA\x40 ARM32,VFPv2
|
|
vreg,immshifter \x42\xE\xB5\xA\x40 ARM32,VFPv2
|
|
|
|
[VCMPEcc]
|
|
vreg,vreg \x42\xE\xB4\xA\xC0 ARM32,VFPv2
|
|
vreg,immshifter \x42\xE\xB5\xA\xC0 ARM32,VFPv2
|
|
|
|
[VCVTcc]
|
|
vreg,vreg \x43\xE\xB8\xA\xC0 ARM32,VFPv2
|
|
vreg,vreg,immshifter \x43\xE\xBA\xA\x40 ARM32,VFPv3
|
|
|
|
[VCVTRcc]
|
|
vreg,vreg \x43\xE\xB8\xA\x40 ARM32,VFPv2
|
|
|
|
[VDIVcc]
|
|
vreg,vreg,vreg \x42\xE\x80\xA\x0 ARM32,VFPv2
|
|
|
|
[VMRScc]
|
|
reg32,regf \x41\xE\xF0\xA\x10 ARM32,VFPv2
|
|
regf,regf \x41\xE\xF0\xA\x10 ARM32,VFPv2
|
|
|
|
[VMSRcc]
|
|
regf,reg32 \x41\xE\xE0\xA\x10 ARM32,VFPv2
|
|
|
|
[VMLAcc]
|
|
vreg,vreg,vreg \x42\xE\x0\xA\x00 ARM32,VFPv2
|
|
|
|
[VMLScc]
|
|
vreg,vreg,vreg \x42\xE\x0\xA\x40 ARM32,VFPv2
|
|
|
|
[VMULcc]
|
|
vreg,vreg,vreg \x42\xE\x20\xA\x0 ARM32,VFPv2
|
|
|
|
[VNMLAcc]
|
|
vreg,vreg,vreg \x42\xE\x10\xA\x40 ARM32,VFPv2
|
|
|
|
[VNMLScc]
|
|
vreg,vreg,vreg \x42\xE\x10\xA\x00 ARM32,VFPv2
|
|
|
|
[VNMULcc]
|
|
vreg,vreg,vreg \x42\xE\x20\xA\x40 ARM32,VFPv2
|
|
|
|
[VFMA]
|
|
[VFMS]
|
|
[VFNMA]
|
|
[VFNMS]
|
|
|
|
[VNEGcc]
|
|
vreg,vreg \x42\xE\xB1\xA\x40 ARM32,VFPv2
|
|
|
|
[VSQRT]
|
|
vreg,vreg \x42\xE\xB1\xA\xC0 ARM32,VFPv2
|
|
|
|
[VSUB]
|
|
vreg,vreg,vreg \x42\xE\x30\xA\x40 ARM32,VFPv2
|
|
|
|
[DMB]
|
|
immshifter \x2E\xF5\x7F\xF0\x50 ARM32,ARMv7
|
|
|
|
[ISB]
|
|
immshifter \x2E\xF5\x7F\xF0\x60 ARM32,ARMv7
|
|
|
|
[DSB]
|
|
immshifter \x2E\xF5\x7F\xF0\x40 ARM32,ARMv7
|
|
|
|
[SMC]
|
|
immshifter \x2E\x01\x60\x00\x70 ARM32,ARMv7
|
|
|
|
; Thumb armv6-m (gcc)
|
|
[NEG]
|
|
|
|
[SVC]
|
|
imm32 \x2\x0F ARM32,ARMv4
|
|
immshifter \x2\x0F ARM32,ARMv4
|
|
|
|
[BXJcc]
|
|
reg32 \x3\x01\x2F\xFF\x20 ARM32,ARMv5TEJ
|
|
|
|
; Undefined mnemonic
|
|
[UDF]
|
|
void void none
|
|
|
|
; FPA
|
|
|
|
|
|
[TANcc]
|
|
|
|
[SQTcc]
|
|
|
|
[SUFcc]
|
|
|
|
[RSFcc]
|
|
|
|
[RNDcc]
|
|
|
|
[POLcc]
|
|
|
|
[RDFcc]
|
|
|
|
[RFScc]
|
|
|
|
[RFCcc]
|
|
|
|
[RMFcc]
|
|
|
|
[RPWcc]
|
|
|
|
[MNFcc]
|
|
|
|
[MUFcc]
|
|
|
|
[ABScc]
|
|
|
|
[ACScc]
|
|
|
|
[ASNcc]
|
|
|
|
[ATNcc]
|
|
|
|
[CNFcc]
|
|
|
|
[COScc]
|
|
|
|
[DVFcc]
|
|
|
|
[EXPcc]
|
|
|
|
[FDVcc]
|
|
|
|
[FLTcc]
|
|
|
|
[FIXcc]
|
|
|
|
[FMLcc]
|
|
|
|
[FRDcc]
|
|
|
|
[LGNcc]
|
|
|
|
[LOGcc] |