mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-07-15 18:27:01 +02:00
684 lines
14 KiB
ObjectPascal
684 lines
14 KiB
ObjectPascal
{
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Register definitions and utility code for STM32F103
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Preliminary startup code - TODO: interrupt handler variables
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Created by Jeppe Johansen 2009 - jepjoh2@kom.aau.dk
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}
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unit stm32f103;
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{$goto on}
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{$define stm32f103}
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interface
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type
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TBitvector32 = bitpacked array[0..31] of 0..1;
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{$PACKRECORDS 2}
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const
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PeripheralBase = $40000000;
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FSMCBase = $60000000;
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APB1Base = PeripheralBase;
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APB2Base = PeripheralBase+$10000;
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AHBBase = PeripheralBase+$20000;
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SCS_BASE = $E000E000;
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{ FSMC }
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FSMCBank1NOR1 = FSMCBase+$00000000;
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FSMCBank1NOR2 = FSMCBase+$04000000;
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FSMCBank1NOR3 = FSMCBase+$08000000;
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FSMCBank1NOR4 = FSMCBase+$0C000000;
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FSMCBank1PSRAM1 = FSMCBase+$00000000;
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FSMCBank1PSRAM2 = FSMCBase+$04000000;
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FSMCBank1PSRAM3 = FSMCBase+$08000000;
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FSMCBank1PSRAM4 = FSMCBase+$0C000000;
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FSMCBank2NAND1 = FSMCBase+$10000000;
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FSMCBank3NAND2 = FSMCBase+$20000000;
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FSMCBank4PCCARD = FSMCBase+$30000000;
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type
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TTimerRegisters = record
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CR1, res1,
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CR2, res2,
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SMCR, res3,
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DIER, res4,
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SR, res5,
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EGR, res,
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CCMR1, res6,
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CCMR2, res7,
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CCER, res8,
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CNT, res9,
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PSC, res10,
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ARR, res11,
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RCR, res12,
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CCR1, res13,
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CCR2, res14,
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CCR3, res15,
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CCR4, res16,
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BDTR, res17,
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DCR, res18,
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DMAR, res19: Word;
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end;
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TRTCRegisters = record
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CRH, res1,
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CRL, res2,
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PRLH, res3,
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PRLL, res4,
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DIVH, res5,
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DIVL, res6,
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CNTH, res7,
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CNTL, res8,
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ALRH, res9,
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ALRL, res10: Word;
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end;
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TIWDGRegisters = record
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KR, res1,
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PR, res2,
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RLR, res3,
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SR, res4: word;
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end;
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TWWDGRegisters = record
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CR, res2,
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CFR, res3,
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SR, res4: word;
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end;
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TSPIRegisters = record
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CR1, res1,
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CR2, res2,
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SR, res3,
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DR, res4,
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CRCPR, res5,
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RXCRCR, res6,
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TXCRCR, res7,
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I2SCFGR, res8,
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I2SPR, res9: Word;
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end;
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TUSARTRegisters = record
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SR, res1,
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DR, res2,
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BRR, res3,
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CR1, res4,
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CR2, res5,
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CR3, res6,
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GTPR, res7: Word;
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end;
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TI2CRegisters = record
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CR1, res1,
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CR2, res2,
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OAR1, res3,
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OAR2, res4,
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DR, res5,
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SR1, res6,
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SR2, res7,
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CCR, res8: word;
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TRISE: byte;
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end;
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TUSBRegisters = record
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EPR: array[0..7] of DWord;
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res: array[0..7] of dword;
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CNTR, res1,
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ISTR, res2,
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FNR, res3: Word;
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DADDR: byte; res4: word; res5: byte;
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BTABLE: Word;
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end;
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TUSBMem = packed array[0..511] of byte;
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TCANMailbox = record
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IR,
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DTR,
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DLR,
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DHR: DWord;
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end;
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TCANRegisters = record
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MCR,
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MSR,
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TSR,
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RF0R,
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RF1R,
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IER,
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ESR,
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BTR: DWord;
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res5: array[$020..$17F] of byte;
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TX: array[0..2] of TCANMailbox;
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RX: array[0..2] of TCANMailbox;
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res6: array[$1D0..$1FF] of byte;
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FMR,
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FM1R,
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res9: DWord;
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FS1R, res10: word;
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res11: DWord;
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FFA1R, res12: word;
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res13: DWord;
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FA1R, res14: word;
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res15: array[$220..$23F] of byte;
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FOR1,
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FOR2: DWord;
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FB: array[1..13] of array[1..2] of DWord;
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end;
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TBKPRegisters = record
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DR: array[1..10] of record data, res: word; end;
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RTCCR,
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CR,
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CSR,
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res1,res2: DWord;
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DR2: array[11..42] of record data, res: word; end;
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end;
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TPwrRegisters = record
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CR, res: word;
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CSR: Word;
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end;
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TDACRegisters = record
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CR,
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SWTRIGR: DWord;
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DHR12R1, res2,
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DHR12L1, res3,
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DHR8R1, res4,
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DHR12R2, res5,
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DHR12L2, res6,
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DHR8R2, res7: word;
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DHR12RD,
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DHR12LD: DWord;
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DHR8RD, res8,
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DOR1, res9,
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DOR2, res10: Word;
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end;
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TAFIORegisters = record
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EVCR,
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MAPR: DWord;
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EXTICR: array[0..3] of DWord;
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end;
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TEXTIRegisters = record
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IMR,
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EMR,
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RTSR,
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FTSR,
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SWIER,
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PR: DWord;
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end;
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TPortRegisters = record
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CRL,
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CRH,
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IDR,
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ODR,
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BSRR,
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BRR,
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LCKR: DWord;
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end;
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TADCRegisters = record
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SR,
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CR1,
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CR2,
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SMPR1,
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SMPR2: DWord;
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JOFR1, res2,
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JOFR2, res3,
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JOFR3, res4,
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JOFR4, res5,
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HTR, res6,
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LTR, res7: word;
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SQR1,
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SQR2,
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SQR3,
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JSQR: DWord;
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JDR1, res8,
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JDR2, res9,
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JDR3, res10,
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JDR4, res11: Word;
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DR: DWord;
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end;
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TSDIORegisters = record
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POWER,
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CLKCR,
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ARG: DWord;
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CMD, res3,
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RESPCMD, res4: Word;
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RESP1,
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RESP2,
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RESP3,
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RESP4,
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DTIMER,
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DLEN: DWord;
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DCTRL, res5: word;
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DCOUNT,
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STA,
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ICR,
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MASK,
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FIFOCNT,
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FIFO: DWord;
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end;
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TDMAChannel = record
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CCR, res1,
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CNDTR, res2: word;
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CPAR,
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CMAR,
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res: DWord;
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end;
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TDMARegisters = record
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ISR,
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IFCR: DWord;
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Channel: array[0..7] of TDMAChannel;
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end;
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TRCCRegisters = record
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CR,
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CFGR,
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CIR,
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APB2RSTR,
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APB1RSTR,
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AHBENR,
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APB2ENR,
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APB1ENR,
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BDCR,
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CSR: DWord;
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end;
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TCRCRegisters = record
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DR: DWord;
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IDR: byte; res1: word; res2: byte;
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CR: byte;
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end;
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TFSMCRegisters = record
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nothingyet: byte;
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end;
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TFlashRegisters = record
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ACR,
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KEYR,
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OPTKEYR,
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SR,
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CR,
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AR,
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res,
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OBR,
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WRPR: DWord;
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end;
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TNVICRegisters = packed record
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ISER: array[0..7] of longword;
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reserved0: array[0..23] of longword;
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ICER: array[0..7] of longword;
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reserved1: array[0..23] of longword;
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ISPR: array[0..7] of longword;
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reserved2: array[0..23] of longword;
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ICPR: array[0..7] of longword;
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reserved3: array[0..23] of longword;
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IABR: array[0..7] of longword;
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reserved4: array[0..55] of longword;
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IP: array[0..239] of longword;
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reserved5: array[0..643] of longword;
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STIR: longword;
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end;
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TSCBRegisters = packed record
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CPUID, {!< CPU ID Base Register }
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ICSR, {!< Interrupt Control State Register }
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VTOR, {!< Vector Table Offset Register }
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AIRCR, {!< Application Interrupt / Reset Control Register }
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SCR, {!< System Control Register }
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CCR: longword; {!< Configuration Control Register }
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SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
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SHCSR, {!< System Handler Control and State Register }
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CFSR, {!< Configurable Fault Status Register }
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HFSR, {!< Hard Fault Status Register }
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DFSR, {!< Debug Fault Status Register }
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MMFAR, {!< Mem Manage Address Register }
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BFAR, {!< Bus Fault Address Register }
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AFSR: longword; {!< Auxiliary Fault Status Register }
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PFR: array[0..1] of longword; {!< Processor Feature Register }
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DFR, {!< Debug Feature Register }
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ADR: longword; {!< Auxiliary Feature Register }
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MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
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ISAR: array[0..4] of longword; {!< ISA Feature Register }
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end;
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TSysTickRegisters = packed record
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Ctrl,
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Load,
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Val,
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Calib: longword;
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end;
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{$ALIGN 2}
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var
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{ Timers }
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Timer1: TTimerRegisters absolute (APB2Base+$2C00);
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Timer2: TTimerRegisters absolute (APB1Base+$0000);
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Timer3: TTimerRegisters absolute (APB1Base+$0400);
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Timer4: TTimerRegisters absolute (APB1Base+$0800);
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Timer5: TTimerRegisters absolute (APB1Base+$0C00);
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Timer6: TTimerRegisters absolute (APB1Base+$1000);
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Timer7: TTimerRegisters absolute (APB1Base+$1400);
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Timer8: TTimerRegisters absolute (APB2Base+$3400);
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{ RTC }
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RTC: TRTCRegisters absolute (APB1Base+$2800);
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{ WDG }
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WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
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IWDG: TIWDGRegisters absolute (APB1Base+$3000);
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{ SPI }
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SPI1: TSPIRegisters absolute (APB2Base+$3000);
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SPI2: TSPIRegisters absolute (APB1Base+$3800);
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SPI3: TSPIRegisters absolute (APB1Base+$3C00);
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{ USART/UART }
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USART1: TUSARTRegisters absolute (APB2Base+$3800);
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USART2: TUSARTRegisters absolute (APB1Base+$4400);
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USART3: TUSARTRegisters absolute (APB1Base+$4800);
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UART4: TUSARTRegisters absolute (APB1Base+$4C00);
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UART5: TUSARTRegisters absolute (APB1Base+$5000);
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{ I2C }
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I2C1: TI2CRegisters absolute (APB1Base+$5400);
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I2C2: TI2CRegisters absolute (APB1Base+$5800);
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{ USB }
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USB: TUSBRegisters absolute (APB1Base+$5C00);
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USBMem: TUSBMem absolute (APB1Base+$6000);
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{ CAN }
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CAN: TCANRegisters absolute (APB1Base+$6800);
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{ BKP }
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BKP: TBKPRegisters absolute (APB1Base+$6C00);
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{ PWR }
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PWR: TPwrRegisters absolute (APB1Base+$7000);
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{ DAC }
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DAC: TDACRegisters absolute (APB1Base+$7400);
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{ GPIO }
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AFIO: TAFIORegisters absolute (APB2Base+$0);
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EXTI: TEXTIRegisters absolute (APB2Base+$0400);
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PortA: TPortRegisters absolute (APB2Base+$0800);
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PortB: TPortRegisters absolute (APB2Base+$0C00);
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PortC: TPortRegisters absolute (APB2Base+$1000);
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PortD: TPortRegisters absolute (APB2Base+$1400);
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PortE: TPortRegisters absolute (APB2Base+$1800);
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PortF: TPortRegisters absolute (APB2Base+$1C00);
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PortG: TPortRegisters absolute (APB2Base+$2000);
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{ ADC }
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ADC1: TADCRegisters absolute (APB2Base+$2400);
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ADC2: TADCRegisters absolute (APB2Base+$2800);
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ADC3: TADCRegisters absolute (APB2Base+$3C00);
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{ SDIO }
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SDIO: TSDIORegisters absolute (APB2Base+$8000);
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{ DMA }
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DMA1: TDMARegisters absolute (AHBBase+$0000);
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DMA2: TDMARegisters absolute (AHBBase+$0400);
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{ RCC }
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RCC: TRCCRegisters absolute (AHBBase+$1000);
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{ Flash }
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Flash: TFlashRegisters absolute (AHBBase+$2000);
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{ CRC }
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CRC: TCRCRegisters absolute (AHBBase+$3000);
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{ SCB }
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SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
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{ SysTick }
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SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
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{ NVIC }
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NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
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var
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NMI_Handler,
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HardFault_Handler,
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MemManage_Handler,
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BusFault_Handler,
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UsageFault_Handler,
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SWI_Handler,
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DebugMonitor_Handler,
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PendingSV_Handler,
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Systick_Handler: pointer;
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implementation
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var
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_data: record end; external name '_data';
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_edata: record end; external name '_edata';
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_etext: record end; external name '_etext';
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_bss_start: record end; external name '_bss_start';
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_bss_end: record end; external name '_bss_end';
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_stack_top: record end; external name '_stack_top';
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procedure PASCALMAIN; external name 'PASCALMAIN';
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procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
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asm
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.Lhalt:
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b .Lhalt
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end;
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procedure _FPC_start; assembler; nostackframe;
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label _start;
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asm
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.init
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.balign 16
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.long _stack_top // First entry in NVIC table is the new stack pointer
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.long _start+1
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//b _start // Reset
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.long _start+1
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//b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
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.long _start+1
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//b .LHardFault_Addr // All class of fault
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.long _start+1
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//b .LMemManage_Addr // Memory management
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.long _start+1
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//b .LBusFault_Addr // Pre-fetch fault, memory access fault
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.long _start+1
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//b .LUsageFault_Addr // Undefined instruction or illegal state
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.long _start+1
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//nop // Reserved
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.long _start+1
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//nop // Reserved
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.long _start+1
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//nop // Reserved
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.long _start+1
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//nop // Reserved
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.long _start+1
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//b .LSWI_Addr // Software Interrupt vector
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.long _start+1
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//b .LDebugMonitor_Addr // Debug Monitor
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.long _start+1
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//nop // Reserved
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.long _start+1
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//b .LPendingSV_Addr // Pendable request for system service
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.long _start+1
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//b .LSystick_Addr // System tick timer
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//17
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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//20
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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|
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
|
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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|
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.long .LDefaultHandler+1
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.LNMI_Addr:
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ldr r0,.L1
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ldr pc,[r0]
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.LHardFault_Addr:
|
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ldr r0,.L2
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ldr pc,[r0]
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.LMemManage_Addr:
|
|
ldr r0,.L3
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|
ldr pc,[r0]
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|
.LBusFault_Addr:
|
|
ldr r0,.L4
|
|
ldr pc,[r0]
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|
.LUsageFault_Addr:
|
|
ldr r0,.L5
|
|
ldr pc,[r0]
|
|
.LSWI_Addr:
|
|
ldr r0,.L6
|
|
ldr pc,[r0]
|
|
.LDebugMonitor_Addr:
|
|
ldr r0,.L7
|
|
ldr pc,[r0]
|
|
.LPendingSV_Addr:
|
|
ldr r0,.L8
|
|
ldr pc,[r0]
|
|
.LSystick_Addr:
|
|
ldr r0,.L9
|
|
ldr pc,[r0]
|
|
|
|
.L1:
|
|
.long NMI_Handler
|
|
.L2:
|
|
.long HardFault_Handler
|
|
.L3:
|
|
.long MemManage_Handler
|
|
.L4:
|
|
.long BusFault_Handler
|
|
.L5:
|
|
.long UsageFault_Handler
|
|
.L6:
|
|
.long SWI_Handler
|
|
.L7:
|
|
.long DebugMonitor_Handler
|
|
.L8:
|
|
.long PendingSV_Handler
|
|
.L9:
|
|
.long Systick_Handler
|
|
|
|
.globl _start
|
|
.text
|
|
_start:
|
|
|
|
// Copy initialized data to ram
|
|
ldr r1,.L_etext
|
|
ldr r2,.L_data
|
|
ldr r3,.L_edata
|
|
.Lcopyloop:
|
|
cmp r2,r3
|
|
ittt ls
|
|
ldrls r0,[r1],#4
|
|
strls r0,[r2],#4
|
|
bls .Lcopyloop
|
|
|
|
// clear onboard ram
|
|
ldr r1,.L_bss_start
|
|
ldr r2,.L_bss_end
|
|
mov r0,#0
|
|
.Lzeroloop:
|
|
cmp r1,r2
|
|
itt ls
|
|
strls r0,[r1],#4
|
|
bls .Lzeroloop
|
|
|
|
b PASCALMAIN
|
|
b _FPC_haltproc
|
|
|
|
.L_bss_start:
|
|
.long _bss_start
|
|
.L_bss_end:
|
|
.long _bss_end
|
|
.L_etext:
|
|
.long _etext
|
|
.L_data:
|
|
.long _data
|
|
.L_edata:
|
|
.long _edata
|
|
.LDefaultHandlerAddr:
|
|
.long .LDefaultHandler
|
|
// default irq handler just returns
|
|
.LDefaultHandler:
|
|
mov pc,r14
|
|
end;
|
|
|
|
end.
|
|
|