mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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274 lines
14 KiB
ObjectPascal
274 lines
14 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by the Free Pascal development team
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Basic Processor information for the MIPS
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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Unit CPUInfo;
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{$i fpcdefs.inc}
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Interface
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uses
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globtype;
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Type
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bestreal = double;
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bestrealrec = TDoubleRec;
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ts32real = single;
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ts64real = double;
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ts80real = type double;
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ts128real = type double;
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ts64comp = comp;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_mips1,
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cpu_mips2,
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cpu_mips3,
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cpu_mips4,
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cpu_mips5,
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cpu_mips32,
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cpu_mips32r2,
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cpu_pic32mx
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);
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tfputype =(fpu_none,fpu_soft,fpu_mips2,fpu_mips3);
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tabitype =
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(
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abi_none,
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abi_default,
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abi_o32,
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abi_n32,
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abi_o64,
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abi_n64,
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abi_eabi
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);
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Const
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{# Size of native extended floating point type }
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extended_size = 8;
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_stdcall,
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pocall_safecall,
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{ same as stdcall only different name mangling }
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pocall_cdecl,
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{ same as stdcall only different name mangling }
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pocall_cppdecl
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];
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{ cpu strings as accepted by
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GNU assembler in -arch=XXX option
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this ilist needs to be uppercased }
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cputypestr : array[tcputype] of string[8] = ('',
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{ cpu_mips1 } 'MIPS1',
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{ cpu_mips2 } 'MIPS2',
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{ cpu_mips3 } 'MIPS3',
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{ cpu_mips4 } 'MIPS4',
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{ cpu_mips5 } 'MIPS5',
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{ cpu_mips32 } 'MIPS32',
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{ cpu_mips32r2 } 'MIPS32R2',
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{ cpu_pic32mx } 'PIC32MX'
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);
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fputypestr : array[tfputype] of string[9] = (
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'NONE',
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'SOFT',
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'MIPS2','MIPS3'
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);
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{ abi strings as accepted by
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GNU assembler in -abi=XXX option }
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abitypestr : array[tabitype] of string[4] =
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({ abi_none } '',
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{ abi_default } '32',
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{ abi_o32 } '32',
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{ abi_n32 } 'n32',
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{ abi_o64 } 'o64',
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{ abi_n64 } '64',
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{ abi_eabi } 'eabi'
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);
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mips_abi : tabitype = abi_default;
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type
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tcpuflags=(
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CPUMIPS_HAS_CMOV, { conditional move instructions (mips4+) }
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CPUMIPS_HAS_ISA32R2 { mips32r2 instructions (also on PIC32) }
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);
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tcontrollerdatatype = record
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controllertypestr, controllerunitstr: string[20];
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cputype: tcputype; fputype: tfputype;
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flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
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end;
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags =
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( { cpu_none } [],
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{ cpu_mips1 } [],
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{ cpu_mips2 } [],
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{ cpu_mips3 } [],
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{ cpu_mips4 } [CPUMIPS_HAS_CMOV],
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{ cpu_mips5 } [CPUMIPS_HAS_CMOV],
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{ cpu_mips32 } [CPUMIPS_HAS_CMOV],
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{ cpu_mips32r2 } [CPUMIPS_HAS_CMOV,CPUMIPS_HAS_ISA32R2],
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{ cpu_pic32mx } [CPUMIPS_HAS_CMOV,CPUMIPS_HAS_ISA32R2]
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);
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{$ifndef MIPSEL}
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type
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tcontrollertype =
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(ct_none
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);
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Const
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{ Is there support for dealing with multiple microcontrollers available }
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{ for this platform? }
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ControllerSupport = false;
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{ We know that there are fields after sramsize
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but we don't care about this warning }
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{$PUSH}
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{$WARN 3177 OFF}
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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(
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(controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
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{$POP}
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{$ELSE MIPSEL}
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{ Is there support for dealing with multiple microcontrollers available }
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{ for this platform? }
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ControllerSupport = true;
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type
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tcontrollertype =
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(ct_none,
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{ pic32mx }
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ct_pic32mx110f016b,
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ct_pic32mx110f016c,
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ct_pic32mx110f016d,
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ct_pic32mx120f032b,
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ct_pic32mx120f032c,
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ct_pic32mx120f032d,
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ct_pic32mx130f064b,
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ct_pic32mx130f064c,
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ct_pic32mx130f064d,
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ct_pic32mx150f128b,
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ct_pic32mx150f128c,
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ct_pic32mx150f128d,
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ct_pic32mx210f016b,
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ct_pic32mx210f016c,
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ct_pic32mx210f016d,
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ct_pic32mx220f032b,
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ct_pic32mx220f032c,
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ct_pic32mx220f032d,
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ct_pic32mx230f064b,
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ct_pic32mx230f064c,
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ct_pic32mx230f064d,
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ct_pic32mx250f128b,
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ct_pic32mx250f128c,
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ct_pic32mx250f128d,
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ct_pic32mx775f256h,
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ct_pic32mx775f256l,
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ct_pic32mx775f512h,
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ct_pic32mx775f512l,
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ct_pic32mx795f512h,
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ct_pic32mx795f512l
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);
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{ We know that there are fields after sramsize
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but we don't care about this warning }
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{$WARN 3177 OFF}
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const
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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(
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(controllertypestr:''; controllerunitstr:''; cputype: cpu_none; fputype: fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0),
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{ PIC32MX1xx Series}
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(controllertypestr:'PIC32MX110F016B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX110F016C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX110F016D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX120F032B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX120F032C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX120F032D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX130F064B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX130F064C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX130F064D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX150F128B'; controllerunitstr:'PIC32MX1xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX150F128C'; controllerunitstr:'PIC32MX1xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX150F128D'; controllerunitstr:'PIC32MX1xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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{ PIC32MX2xx Series}
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(controllertypestr:'PIC32MX210F016B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX210F016C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX210F016D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00004000; srambase:$A0000000; sramsize:$00001000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX220F032B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX220F032C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX220F032D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00008000; srambase:$A0000000; sramsize:$00002000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX230F064B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX230F064C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX230F064D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00010000; srambase:$A0000000; sramsize:$00004000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX250F128B'; controllerunitstr:'PIC32MX2xxFxxxB'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX250F128C'; controllerunitstr:'PIC32MX2xxFxxxC'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$80000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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(controllertypestr:'PIC32MX250F128D'; controllerunitstr:'PIC32MX2xxFxxxD'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00020000; srambase:$A0000000; sramsize:$00008000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00000BEF),
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{ PIC32MX7x5 Series}
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(controllertypestr:'PIC32MX775F256H'; controllerunitstr:'PIC32MX7x5FxxxH'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00040000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
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(controllertypestr:'PIC32MX775F256L'; controllerunitstr:'PIC32MX7x5FxxxL'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00040000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
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(controllertypestr:'PIC32MX775F512H'; controllerunitstr:'PIC32MX7x5FxxxH'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
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(controllertypestr:'PIC32MX775F512L'; controllerunitstr:'PIC32MX7x5FxxxL'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00010000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
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(controllertypestr:'PIC32MX795F512H'; controllerunitstr:'PIC32MX7x5FxxxH'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00020000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF),
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(controllertypestr:'PIC32MX795F512L'; controllerunitstr:'PIC32MX7x5FxxxL'; cputype: cpu_pic32mx; fputype: fpu_soft; flashbase:$9d000000; flashsize:$00080000; srambase:$A0000000; sramsize:$00020000; eeprombase:0; eepromsize:0; bootbase:$BFC00000; bootsize:$00002FEF)
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);
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{$endif MIPSEL}
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_loopunroll,cs_opt_nodecse,
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cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = level1optimizerswitches + [{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_nodecse];
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level3optimizerswitches = level2optimizerswitches;
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
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function SetMipsABIType(const s : string) : boolean;
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Implementation
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uses
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cutils;
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function SetMipsABIType(const s : string) : boolean;
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var
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abi : tabitype;
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begin
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SetMipsABIType:=false;
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for abi := low(tabitype) to high(tabitype) do
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if (lower(s)=abitypestr[abi]) then
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begin
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mips_abi:=abi;
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SetMipsABIType:=true;
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break;
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end;
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end;
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end.
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