mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-06-26 00:58:17 +02:00
ddba821561
from cpubase unit to a method in the tcg class. The reason for doing that is that this is now a standard part of the 16-bit and 8-bit code generators and moving to the tcg class allows doing extra checks (not done yet, but for example, in the future, we can keep track of whether there was an extra register allocated with getintregister and halt with an internalerror in case GetNextReg() is called for registers, which weren't allocated as a part of a sequence, therefore catching a certain class of 8-bit and 16-bit code generator bugs at compile time, instead of generating wrong code). - removed GetLastReg() from avr's cpubase unit, because it isn't used for anything. It might be added to the tcg class, in case it's ever needed, but for now I've left it out. * GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit. git-svn-id: trunk@37180 -
1076 lines
41 KiB
ObjectPascal
1076 lines
41 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the i8086
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n8086add;
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{$i fpcdefs.inc}
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interface
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uses
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node,nadd,cpubase,nx86add;
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type
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{ ti8086addnode }
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ti8086addnode = class(tx86addnode)
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function simplify(forinline: boolean) : tnode;override;
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function use_generic_mul32to64: boolean; override;
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function first_addpointer: tnode; override;
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function first_addhugepointer: tnode;
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function first_cmppointer: tnode; override;
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function first_cmphugepointer: tnode;
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function first_cmpfarpointer: tnode;
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procedure second_addordinal; override;
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procedure second_add64bit;override;
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procedure second_addfarpointer;
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procedure second_cmp64bit;override;
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procedure second_cmp32bit;
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procedure second_cmpfarpointer;
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procedure second_cmpordinal;override;
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procedure second_mul(unsigned: boolean);
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,constexp,pass_1,
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symconst,symdef,symtype,symcpu,paramgr,defutil,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cgbase,procinfo,
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ncal,ncon,nset,cgutils,tgobj,
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cga,ncgutil,cgobj,cg64f32,cgx86,
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hlcgobj;
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{*****************************************************************************
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simplify
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*****************************************************************************}
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function ti8086addnode.simplify(forinline: boolean): tnode;
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var
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t : tnode;
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lt,rt: tnodetype;
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rd,ld: tdef;
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rv,lv,v: tconstexprint;
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begin
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{ load easier access variables }
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rd:=right.resultdef;
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ld:=left.resultdef;
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rt:=right.nodetype;
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lt:=left.nodetype;
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if (
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(lt = pointerconstn) and is_farpointer(ld) and
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is_constintnode(right) and
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(nodetype in [addn,subn])
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) or
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(
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(rt = pointerconstn) and is_farpointer(rd) and
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is_constintnode(left) and
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(nodetype=addn)
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) or
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(
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(lt in [pointerconstn,niln]) and is_farpointer(ld) and
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(rt in [pointerconstn,niln]) and is_farpointer(rd) and
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(nodetype in [ltn,lten,gtn,gten,equaln,unequaln])
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) then
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begin
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t:=nil;
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{ load values }
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case lt of
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ordconstn:
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lv:=tordconstnode(left).value;
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pointerconstn:
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lv:=tpointerconstnode(left).value;
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niln:
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lv:=0;
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else
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internalerror(2002080202);
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end;
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case rt of
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ordconstn:
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rv:=tordconstnode(right).value;
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pointerconstn:
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rv:=tpointerconstnode(right).value;
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niln:
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rv:=0;
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else
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internalerror(2002080203);
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end;
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case nodetype of
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addn:
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begin
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v:=lv+rv;
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if lt=pointerconstn then
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t := cpointerconstnode.create((qword(lv) and $FFFF0000) or word(qword(v)),resultdef)
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else if rt=pointerconstn then
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t := cpointerconstnode.create((qword(rv) and $FFFF0000) or word(qword(v)),resultdef)
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else
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internalerror(2014040604);
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end;
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subn:
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begin
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v:=lv-rv;
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if (lt=pointerconstn) then
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{ pointer-pointer results in an integer }
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if (rt=pointerconstn) then
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begin
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if not(nf_has_pointerdiv in flags) then
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internalerror(2008030101);
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{ todo: implement pointer-pointer as well }
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internalerror(2014040607);
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//t := cpointerconstnode.create(qword(v),resultdef);
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end
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else
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t := cpointerconstnode.create((qword(lv) and $FFFF0000) or word(qword(v)),resultdef)
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else
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internalerror(2014040606);
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end;
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ltn:
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t:=cordconstnode.create(ord(word(qword(lv))<word(qword(rv))),pasbool8type,true);
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lten:
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t:=cordconstnode.create(ord(word(qword(lv))<=word(qword(rv))),pasbool8type,true);
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gtn:
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t:=cordconstnode.create(ord(word(qword(lv))>word(qword(rv))),pasbool8type,true);
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gten:
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t:=cordconstnode.create(ord(word(qword(lv))>=word(qword(rv))),pasbool8type,true);
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equaln:
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t:=cordconstnode.create(ord(lv=rv),pasbool8type,true);
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unequaln:
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t:=cordconstnode.create(ord(lv<>rv),pasbool8type,true);
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else
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internalerror(2014040605);
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end;
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result:=t;
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exit;
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end
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else
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Result:=inherited simplify(forinline);
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end;
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{*****************************************************************************
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use_generic_mul32to64
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*****************************************************************************}
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function ti8086addnode.use_generic_mul32to64: boolean;
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begin
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result := True;
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end;
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{ handles all multiplications }
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procedure ti8086addnode.second_addordinal;
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var
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unsigned: boolean;
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if nodetype=muln then
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second_mul(unsigned)
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else if is_farpointer(left.resultdef) xor is_farpointer(right.resultdef) then
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second_addfarpointer
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else
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inherited second_addordinal;
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end;
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{*****************************************************************************
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Add64bit
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*****************************************************************************}
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procedure ti8086addnode.second_add64bit;
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var
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op : TOpCG;
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op1,op2 : TAsmOp;
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hregister,
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hregister2 : tregister;
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hl4 : tasmlabel;
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mboverflow,
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unsigned:boolean;
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r:Tregister;
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begin
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pass_left_right;
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op1:=A_NONE;
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op2:=A_NONE;
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mboverflow:=false;
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unsigned:=((left.resultdef.typ=orddef) and
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(torddef(left.resultdef).ordtype=u64bit)) or
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((right.resultdef.typ=orddef) and
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(torddef(right.resultdef).ordtype=u64bit));
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case nodetype of
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addn :
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begin
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op:=OP_ADD;
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mboverflow:=true;
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end;
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subn :
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begin
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op:=OP_SUB;
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op1:=A_SUB;
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op2:=A_SBB;
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mboverflow:=true;
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end;
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xorn:
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op:=OP_XOR;
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orn:
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op:=OP_OR;
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andn:
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op:=OP_AND;
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else
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begin
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{ everything should be handled in pass_1 (JM) }
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internalerror(200109051);
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end;
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end;
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{ left and right no register? }
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{ then one must be demanded }
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if (left.location.loc<>LOC_REGISTER) then
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begin
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if (right.location.loc<>LOC_REGISTER) then
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begin
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hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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hregister2:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg64.a_load64_loc_reg(current_asmdata.CurrAsmList,left.location,joinreg64(hregister,hregister2));
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location_reset(left.location,LOC_REGISTER,left.location.size);
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left.location.register64.reglo:=hregister;
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left.location.register64.reghi:=hregister2;
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end
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else
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begin
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end;
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end;
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{ at this point, left.location.loc should be LOC_REGISTER }
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if right.location.loc=LOC_REGISTER then
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begin
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{ when swapped another result register }
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if (nodetype=subn) and (nf_swapped in flags) then
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begin
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cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,op,location.size,
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left.location.register64,
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right.location.register64);
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end
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else
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begin
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cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,op,location.size,
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right.location.register64,
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left.location.register64);
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end;
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end
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else
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begin
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{ right.location<>LOC_REGISTER }
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if (nodetype=subn) and (nf_swapped in flags) then
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begin
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r:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg64.a_load64low_loc_reg(current_asmdata.CurrAsmList,right.location,r);
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emit_reg_reg(op1,S_W,left.location.register64.reglo,r);
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emit_reg_reg(op2,S_W,cg.GetNextReg(left.location.register64.reglo),cg.GetNextReg(r));
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emit_reg_reg(A_MOV,S_W,r,left.location.register64.reglo);
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emit_reg_reg(A_MOV,S_W,cg.GetNextReg(r),cg.GetNextReg(left.location.register64.reglo));
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cg64.a_load64high_loc_reg(current_asmdata.CurrAsmList,right.location,r);
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{ the carry flag is still ok }
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emit_reg_reg(op2,S_W,left.location.register64.reghi,r);
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emit_reg_reg(op2,S_W,cg.GetNextReg(left.location.register64.reghi),cg.GetNextReg(r));
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emit_reg_reg(A_MOV,S_W,r,left.location.register64.reghi);
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emit_reg_reg(A_MOV,S_W,cg.GetNextReg(r),cg.GetNextReg(left.location.register64.reghi));
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end
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else
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begin
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cg64.a_op64_loc_reg(current_asmdata.CurrAsmList,op,location.size,right.location,
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left.location.register64);
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end;
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location_freetemp(current_asmdata.CurrAsmList,right.location);
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end;
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{ only in case of overflow operations }
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{ produce overflow code }
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{ we must put it here directly, because sign of operation }
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{ is in unsigned VAR!! }
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if mboverflow then
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begin
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if cs_check_overflow in current_settings.localswitches then
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begin
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current_asmdata.getjumplabel(hl4);
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if unsigned then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_AE,hl4)
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else
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NO,hl4);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
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cg.a_label(current_asmdata.CurrAsmList,hl4);
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end;
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end;
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location_copy(location,left.location);
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end;
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function ti8086addnode.first_addpointer: tnode;
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begin
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if is_hugepointer(left.resultdef) or is_hugepointer(right.resultdef) then
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result:=first_addhugepointer
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else
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result:=inherited;
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end;
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function ti8086addnode.first_addhugepointer: tnode;
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var
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procname:string;
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begin
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result:=nil;
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if (nodetype=subn) and is_hugepointer(left.resultdef) and is_hugepointer(right.resultdef) then
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procname:='fpc_hugeptr_sub_hugeptr'
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else
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begin
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case nodetype of
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addn:
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procname:='fpc_hugeptr_add_longint';
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subn:
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procname:='fpc_hugeptr_sub_longint';
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else
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internalerror(2014070301);
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end;
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if cs_hugeptr_arithmetic_normalization in current_settings.localswitches then
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procname:=procname+'_normalized';
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end;
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if is_hugepointer(left.resultdef) then
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result := ccallnode.createintern(procname,
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ccallparanode.create(right,
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ccallparanode.create(left,nil)))
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else
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result := ccallnode.createintern(procname,
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ccallparanode.create(left,
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ccallparanode.create(right,nil)));
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left := nil;
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right := nil;
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firstpass(result);
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end;
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function ti8086addnode.first_cmppointer: tnode;
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begin
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if is_hugepointer(left.resultdef) or is_hugepointer(right.resultdef) then
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result:=first_cmphugepointer
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else if is_farpointer(left.resultdef) or is_farpointer(right.resultdef) then
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result:=first_cmpfarpointer
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else
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result:=inherited;
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end;
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function ti8086addnode.first_cmphugepointer: tnode;
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var
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procname:string;
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begin
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result:=nil;
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if not (cs_hugeptr_comparison_normalization in current_settings.localswitches) then
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begin
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expectloc:=LOC_JUMP;
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exit;
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end;
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case nodetype of
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equaln:
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procname:='fpc_hugeptr_cmp_normalized_e';
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unequaln:
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procname:='fpc_hugeptr_cmp_normalized_ne';
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ltn:
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procname:='fpc_hugeptr_cmp_normalized_b';
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lten:
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procname:='fpc_hugeptr_cmp_normalized_be';
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gtn:
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procname:='fpc_hugeptr_cmp_normalized_a';
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gten:
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procname:='fpc_hugeptr_cmp_normalized_ae';
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else
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internalerror(2014070401);
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end;
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result := ccallnode.createintern(procname,
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ccallparanode.create(right,
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ccallparanode.create(left,nil)));
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left := nil;
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right := nil;
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firstpass(result);
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end;
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function ti8086addnode.first_cmpfarpointer: tnode;
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begin
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{ = and <> are handled as a 32-bit comparison }
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if nodetype in [equaln,unequaln] then
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begin
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result:=nil;
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expectloc:=LOC_JUMP;
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end
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else
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begin
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result:=nil;
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expectloc:=LOC_FLAGS;
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end;
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end;
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|
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procedure ti8086addnode.second_addfarpointer;
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var
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tmpreg : tregister;
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pointernode: tnode;
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begin
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pass_left_right;
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force_reg_left_right(false,true);
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set_result_location_reg;
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if (left.resultdef.typ=pointerdef) and (right.resultdef.typ<>pointerdef) then
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pointernode:=left
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else if (left.resultdef.typ<>pointerdef) and (right.resultdef.typ=pointerdef) then
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pointernode:=right
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else
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internalerror(2014040601);
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|
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if not (nodetype in [addn,subn]) then
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internalerror(2014040602);
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if nodetype=addn then
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begin
|
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if (right.location.loc<>LOC_CONSTANT) then
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begin
|
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_ADD,OS_16,
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left.location.register,right.location.register,location.register);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,
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cg.GetNextReg(pointernode.location.register),cg.GetNextReg(location.register));
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end
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else
|
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begin
|
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if pointernode=left then
|
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begin
|
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{ farptr_reg + int_const }
|
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_ADD,OS_16,
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right.location.value,left.location.register,location.register);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,
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cg.GetNextReg(left.location.register),cg.GetNextReg(location.register));
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end
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else
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begin
|
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{ int_reg + farptr_const }
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_load_const_reg(current_asmdata.CurrAsmList,resultdef,
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right.location.value,tmpreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_ADD,OS_16,
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left.location.register,tmpreg,location.register);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,
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cg.GetNextReg(tmpreg),cg.GetNextReg(location.register));
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end;
|
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end;
|
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end
|
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else { subtract is a special case since its not commutative }
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begin
|
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if (nf_swapped in flags) then
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|
swapleftright;
|
|
{ left can only be a pointer in this case, since (int-pointer) is not supported }
|
|
if pointernode<>left then
|
|
internalerror(2014040603);
|
|
if left.location.loc<>LOC_CONSTANT then
|
|
begin
|
|
if right.location.loc<>LOC_CONSTANT then
|
|
begin
|
|
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_16,
|
|
right.location.register,left.location.register,location.register);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,
|
|
cg.GetNextReg(pointernode.location.register),cg.GetNextReg(location.register));
|
|
end
|
|
else
|
|
begin
|
|
{ farptr_reg - int_const }
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_16,
|
|
right.location.value,left.location.register,location.register);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,
|
|
cg.GetNextReg(left.location.register),cg.GetNextReg(location.register));
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
{ farptr_const - int_reg }
|
|
tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
|
|
hlcg.a_load_const_reg(current_asmdata.CurrAsmList,resultdef,
|
|
left.location.value,tmpreg);
|
|
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_16,
|
|
right.location.register,tmpreg,location.register);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_16,OS_16,
|
|
cg.GetNextReg(tmpreg),cg.GetNextReg(location.register));
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure ti8086addnode.second_cmp64bit;
|
|
var
|
|
truelabel,
|
|
falselabel : tasmlabel;
|
|
hregister,
|
|
hregister2 : tregister;
|
|
href : treference;
|
|
unsigned : boolean;
|
|
|
|
procedure firstjmp64bitcmp;
|
|
|
|
var
|
|
oldnodetype : tnodetype;
|
|
|
|
begin
|
|
{$ifdef OLDREGVARS}
|
|
load_all_regvars(current_asmdata.CurrAsmList);
|
|
{$endif OLDREGVARS}
|
|
{ the jump the sequence is a little bit hairy }
|
|
case nodetype of
|
|
ltn,gtn:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
|
|
{ cheat a little bit for the negative test }
|
|
toggleflag(nf_swapped);
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
lten,gten:
|
|
begin
|
|
oldnodetype:=nodetype;
|
|
if nodetype=lten then
|
|
nodetype:=ltn
|
|
else
|
|
nodetype:=gtn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
|
|
{ cheat for the negative test }
|
|
if nodetype=ltn then
|
|
nodetype:=gtn
|
|
else
|
|
nodetype:=ltn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
|
|
nodetype:=oldnodetype;
|
|
end;
|
|
equaln:
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
|
|
unequaln:
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
|
|
end;
|
|
end;
|
|
|
|
procedure middlejmp64bitcmp;
|
|
|
|
var
|
|
oldnodetype : tnodetype;
|
|
|
|
begin
|
|
{$ifdef OLDREGVARS}
|
|
load_all_regvars(current_asmdata.CurrAsmList);
|
|
{$endif OLDREGVARS}
|
|
{ the jump the sequence is a little bit hairy }
|
|
case nodetype of
|
|
ltn,gtn:
|
|
begin
|
|
{ the comparisaion of the low word have to be }
|
|
{ always unsigned! }
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.truelabel);
|
|
{ cheat a little bit for the negative test }
|
|
toggleflag(nf_swapped);
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.falselabel);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
lten,gten:
|
|
begin
|
|
oldnodetype:=nodetype;
|
|
if nodetype=lten then
|
|
nodetype:=ltn
|
|
else
|
|
nodetype:=gtn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.truelabel);
|
|
{ cheat for the negative test }
|
|
if nodetype=ltn then
|
|
nodetype:=gtn
|
|
else
|
|
nodetype:=ltn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.falselabel);
|
|
nodetype:=oldnodetype;
|
|
end;
|
|
equaln:
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
|
|
unequaln:
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
|
|
end;
|
|
end;
|
|
|
|
procedure lastjmp64bitcmp;
|
|
|
|
begin
|
|
{ the jump the sequence is a little bit hairy }
|
|
case nodetype of
|
|
ltn,gtn,lten,gten:
|
|
begin
|
|
{ the comparisaion of the low word have to be }
|
|
{ always unsigned! }
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.truelabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
|
|
end;
|
|
equaln:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.truelabel);
|
|
end;
|
|
unequaln:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
truelabel:=nil;
|
|
falselabel:=nil;
|
|
pass_left_right;
|
|
|
|
unsigned:=((left.resultdef.typ=orddef) and
|
|
(torddef(left.resultdef).ordtype=u64bit)) or
|
|
((right.resultdef.typ=orddef) and
|
|
(torddef(right.resultdef).ordtype=u64bit));
|
|
|
|
{ we have LOC_JUMP as result }
|
|
current_asmdata.getjumplabel(truelabel);
|
|
current_asmdata.getjumplabel(falselabel);
|
|
location_reset_jump(location,truelabel,falselabel);
|
|
|
|
{ left and right no register? }
|
|
{ then one must be demanded }
|
|
if (left.location.loc<>LOC_REGISTER) then
|
|
begin
|
|
if (right.location.loc<>LOC_REGISTER) then
|
|
begin
|
|
{ we can reuse a CREGISTER for comparison }
|
|
if (left.location.loc<>LOC_CREGISTER) then
|
|
begin
|
|
hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
hregister2:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
cg64.a_load64_loc_reg(current_asmdata.CurrAsmList,left.location,joinreg64(hregister,hregister2));
|
|
location_freetemp(current_asmdata.CurrAsmList,left.location);
|
|
location_reset(left.location,LOC_REGISTER,left.location.size);
|
|
left.location.register64.reglo:=hregister;
|
|
left.location.register64.reghi:=hregister2;
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
location_swap(left.location,right.location);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
end;
|
|
|
|
{ at this point, left.location.loc should be LOC_REGISTER }
|
|
if right.location.loc=LOC_REGISTER then
|
|
begin
|
|
emit_reg_reg(A_CMP,S_W,cg.GetNextReg(right.location.register64.reghi),cg.GetNextReg(left.location.register64.reghi));
|
|
firstjmp64bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,right.location.register64.reghi,left.location.register64.reghi);
|
|
middlejmp64bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,cg.GetNextReg(right.location.register64.reglo),cg.GetNextReg(left.location.register64.reglo));
|
|
middlejmp64bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,right.location.register64.reglo,left.location.register64.reglo);
|
|
lastjmp64bitcmp;
|
|
end
|
|
else
|
|
begin
|
|
case right.location.loc of
|
|
LOC_CREGISTER :
|
|
begin
|
|
emit_reg_reg(A_CMP,S_W,cg.GetNextReg(right.location.register64.reghi),cg.GetNextReg(left.location.register64.reghi));
|
|
firstjmp64bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,right.location.register64.reghi,left.location.register64.reghi);
|
|
middlejmp64bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,cg.GetNextReg(right.location.register64.reglo),cg.GetNextReg(left.location.register64.reglo));
|
|
middlejmp64bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,right.location.register64.reglo,left.location.register64.reglo);
|
|
lastjmp64bitcmp;
|
|
end;
|
|
LOC_CREFERENCE,
|
|
LOC_REFERENCE :
|
|
begin
|
|
tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,right.location.reference);
|
|
href:=right.location.reference;
|
|
inc(href.offset,6);
|
|
emit_ref_reg(A_CMP,S_W,href,cg.GetNextReg(left.location.register64.reghi));
|
|
firstjmp64bitcmp;
|
|
dec(href.offset,2);
|
|
emit_ref_reg(A_CMP,S_W,href,left.location.register64.reghi);
|
|
middlejmp64bitcmp;
|
|
dec(href.offset,2);
|
|
emit_ref_reg(A_CMP,S_W,href,cg.GetNextReg(left.location.register64.reglo));
|
|
middlejmp64bitcmp;
|
|
emit_ref_reg(A_CMP,S_W,right.location.reference,left.location.register64.reglo);
|
|
lastjmp64bitcmp;
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
|
|
location_freetemp(current_asmdata.CurrAsmList,right.location);
|
|
end;
|
|
LOC_CONSTANT :
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_W,aint((right.location.value64 shr 48) and $FFFF),cg.GetNextReg(left.location.register64.reghi)));
|
|
firstjmp64bitcmp;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_W,aint((right.location.value64 shr 32) and $FFFF),left.location.register64.reghi));
|
|
middlejmp64bitcmp;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_W,aint((right.location.value64 shr 16) and $FFFF),cg.GetNextReg(left.location.register64.reglo)));
|
|
middlejmp64bitcmp;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_W,aint(right.location.value64 and $FFFF),left.location.register64.reglo));
|
|
lastjmp64bitcmp;
|
|
end;
|
|
else
|
|
internalerror(200203282);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
procedure ti8086addnode.second_cmp32bit;
|
|
var
|
|
truelabel,
|
|
falselabel: tasmlabel;
|
|
hregister : tregister;
|
|
href : treference;
|
|
unsigned : boolean;
|
|
|
|
procedure firstjmp32bitcmp;
|
|
|
|
var
|
|
oldnodetype : tnodetype;
|
|
|
|
begin
|
|
{$ifdef OLDREGVARS}
|
|
load_all_regvars(current_asmdata.CurrAsmList);
|
|
{$endif OLDREGVARS}
|
|
{ the jump the sequence is a little bit hairy }
|
|
case nodetype of
|
|
ltn,gtn:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
|
|
{ cheat a little bit for the negative test }
|
|
toggleflag(nf_swapped);
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
lten,gten:
|
|
begin
|
|
oldnodetype:=nodetype;
|
|
if nodetype=lten then
|
|
nodetype:=ltn
|
|
else
|
|
nodetype:=gtn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
|
|
{ cheat for the negative test }
|
|
if nodetype=ltn then
|
|
nodetype:=gtn
|
|
else
|
|
nodetype:=ltn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
|
|
nodetype:=oldnodetype;
|
|
end;
|
|
equaln:
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
|
|
unequaln:
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
|
|
end;
|
|
end;
|
|
|
|
procedure secondjmp32bitcmp;
|
|
|
|
begin
|
|
{ the jump the sequence is a little bit hairy }
|
|
case nodetype of
|
|
ltn,gtn,lten,gten:
|
|
begin
|
|
{ the comparisaion of the low dword have to be }
|
|
{ always unsigned! }
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.truelabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
|
|
end;
|
|
equaln:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.truelabel);
|
|
end;
|
|
unequaln:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
truelabel:=nil;
|
|
falselabel:=nil;
|
|
pass_left_right;
|
|
|
|
unsigned:=((left.resultdef.typ=orddef) and
|
|
(torddef(left.resultdef).ordtype=u32bit)) or
|
|
((right.resultdef.typ=orddef) and
|
|
(torddef(right.resultdef).ordtype=u32bit)) or
|
|
is_hugepointer(left.resultdef);
|
|
|
|
{ we have LOC_JUMP as result }
|
|
current_asmdata.getjumplabel(truelabel);
|
|
current_asmdata.getjumplabel(falselabel);
|
|
location_reset_jump(location,truelabel,falselabel);
|
|
|
|
{ left and right no register? }
|
|
{ then one must be demanded }
|
|
if (left.location.loc<>LOC_REGISTER) then
|
|
begin
|
|
if (right.location.loc<>LOC_REGISTER) then
|
|
begin
|
|
{ we can reuse a CREGISTER for comparison }
|
|
if (left.location.loc<>LOC_CREGISTER) then
|
|
begin
|
|
hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
cg.a_load_loc_reg(current_asmdata.CurrAsmList,OS_32,left.location,hregister);
|
|
location_freetemp(current_asmdata.CurrAsmList,left.location);
|
|
location_reset(left.location,LOC_REGISTER,left.location.size);
|
|
left.location.register:=hregister;
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
location_swap(left.location,right.location);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
end;
|
|
|
|
{ at this point, left.location.loc should be LOC_REGISTER }
|
|
if right.location.loc=LOC_REGISTER then
|
|
begin
|
|
emit_reg_reg(A_CMP,S_W,cg.GetNextReg(right.location.register),cg.GetNextReg(left.location.register));
|
|
firstjmp32bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,right.location.register,left.location.register);
|
|
secondjmp32bitcmp;
|
|
end
|
|
else
|
|
begin
|
|
case right.location.loc of
|
|
LOC_CREGISTER :
|
|
begin
|
|
emit_reg_reg(A_CMP,S_W,cg.GetNextReg(right.location.register),cg.GetNextReg(left.location.register));
|
|
firstjmp32bitcmp;
|
|
emit_reg_reg(A_CMP,S_W,right.location.register,left.location.register);
|
|
secondjmp32bitcmp;
|
|
end;
|
|
LOC_CREFERENCE,
|
|
LOC_REFERENCE :
|
|
begin
|
|
tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,right.location.reference);
|
|
href:=right.location.reference;
|
|
inc(href.offset,2);
|
|
emit_ref_reg(A_CMP,S_W,href,cg.GetNextReg(left.location.register));
|
|
firstjmp32bitcmp;
|
|
dec(href.offset,2);
|
|
emit_ref_reg(A_CMP,S_W,href,left.location.register);
|
|
secondjmp32bitcmp;
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
|
|
location_freetemp(current_asmdata.CurrAsmList,right.location);
|
|
end;
|
|
LOC_CONSTANT :
|
|
begin
|
|
if (right.location.value=0) and (nodetype in [equaln,unequaln]) and (left.location.loc=LOC_REGISTER) then
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_OR,S_W,cg.GetNextReg(left.location.register),left.location.register));
|
|
secondjmp32bitcmp;
|
|
end
|
|
else
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_W,aint((right.location.value shr 16) and $FFFF),cg.GetNextReg(left.location.register)));
|
|
firstjmp32bitcmp;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_W,aint(right.location.value and $FFFF),left.location.register));
|
|
secondjmp32bitcmp;
|
|
end;
|
|
end;
|
|
else
|
|
internalerror(200203282);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure ti8086addnode.second_cmpfarpointer;
|
|
begin
|
|
{ handle = and <> as a 32-bit comparison }
|
|
if nodetype in [equaln,unequaln] then
|
|
begin
|
|
second_cmp32bit;
|
|
exit;
|
|
end;
|
|
|
|
pass_left_right;
|
|
|
|
{ <, >, <= and >= compare the 16-bit offset only }
|
|
if (right.location.loc=LOC_CONSTANT) and
|
|
(left.location.loc in [LOC_REFERENCE, LOC_CREFERENCE])
|
|
then
|
|
begin
|
|
emit_const_ref(A_CMP, S_W, word(right.location.value), left.location.reference);
|
|
location_freetemp(current_asmdata.CurrAsmList,left.location);
|
|
end
|
|
else
|
|
begin
|
|
{ left location is not a register? }
|
|
if left.location.loc<>LOC_REGISTER then
|
|
begin
|
|
{ if right is register then we can swap the locations }
|
|
if right.location.loc=LOC_REGISTER then
|
|
begin
|
|
location_swap(left.location,right.location);
|
|
toggleflag(nf_swapped);
|
|
end
|
|
else
|
|
begin
|
|
{ maybe we can reuse a constant register when the
|
|
operation is a comparison that doesn't change the
|
|
value of the register }
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,u16inttype,true);
|
|
end;
|
|
end;
|
|
|
|
emit_generic_code(A_CMP,OS_16,true,false,false);
|
|
location_freetemp(current_asmdata.CurrAsmList,right.location);
|
|
location_freetemp(current_asmdata.CurrAsmList,left.location);
|
|
end;
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
location.resflags:=getresflags(true);
|
|
end;
|
|
|
|
|
|
procedure ti8086addnode.second_cmpordinal;
|
|
begin
|
|
if is_farpointer(left.resultdef) then
|
|
second_cmpfarpointer
|
|
else if is_32bit(left.resultdef) or is_hugepointer(left.resultdef) or is_farprocvar(left.resultdef) then
|
|
second_cmp32bit
|
|
else
|
|
inherited second_cmpordinal;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
x86 MUL
|
|
*****************************************************************************}
|
|
|
|
procedure ti8086addnode.second_mul(unsigned: boolean);
|
|
|
|
var reg:Tregister;
|
|
ref:Treference;
|
|
use_ref:boolean;
|
|
hl4 : tasmlabel;
|
|
|
|
const
|
|
asmops: array[boolean] of tasmop = (A_IMUL, A_MUL);
|
|
|
|
begin
|
|
reg:=NR_NO;
|
|
reference_reset(ref,sizeof(pint),[]);
|
|
|
|
pass_left_right;
|
|
|
|
{ MUL is faster than IMUL on the 8086 & 8088 (and equal in speed on 286+),
|
|
but it's only safe to use in place of IMUL when overflow checking is off
|
|
and we're doing a 16-bit>16-bit multiplication }
|
|
if not (cs_check_overflow in current_settings.localswitches) and
|
|
(not is_32bitint(resultdef)) then
|
|
unsigned:=true;
|
|
|
|
{The location.register will be filled in later (JM)}
|
|
location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
|
|
{ Mul supports registers and references, so if not register/reference,
|
|
load the location into a register. }
|
|
use_ref:=false;
|
|
if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
|
|
reg:=left.location.register
|
|
else if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
|
|
begin
|
|
tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
|
|
ref:=left.location.reference;
|
|
use_ref:=true;
|
|
end
|
|
else
|
|
begin
|
|
{LOC_CONSTANT for example.}
|
|
reg:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,left.resultdef,osuinttype,left.location,reg);
|
|
end;
|
|
{Allocate AX.}
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,NR_AX);
|
|
{Load the right value.}
|
|
hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,NR_AX);
|
|
{Also allocate DX, since it is also modified by a mul (JM).}
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,NR_DX);
|
|
if use_ref then
|
|
emit_ref(asmops[unsigned],S_W,ref)
|
|
else
|
|
emit_reg(asmops[unsigned],S_W,reg);
|
|
if (cs_check_overflow in current_settings.localswitches) and
|
|
{ 16->32 bit cannot overflow }
|
|
(not is_32bitint(resultdef)) then
|
|
begin
|
|
current_asmdata.getjumplabel(hl4);
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_AE,hl4);
|
|
cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
|
|
cg.a_label(current_asmdata.CurrAsmList,hl4);
|
|
end;
|
|
{Free AX,DX}
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_DX);
|
|
if is_32bitint(resultdef) then
|
|
begin
|
|
{Allocate an imaginary 32-bit register, which consists of a pair of
|
|
16-bit registers and store DX:AX into it}
|
|
location.register := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_DX,cg.GetNextReg(location.register));
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_AX);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_AX,location.register);
|
|
end
|
|
else
|
|
begin
|
|
{Allocate a new register and store the result in AX in it.}
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_AX);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_AX,location.register);
|
|
end;
|
|
location_freetemp(current_asmdata.CurrAsmList,left.location);
|
|
location_freetemp(current_asmdata.CurrAsmList,right.location);
|
|
end;
|
|
|
|
|
|
begin
|
|
caddnode:=ti8086addnode;
|
|
end.
|