mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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3ee29eb219
Added LM4F120H5 controller type and startup code git-svn-id: branches/laksen/arm-embedded@22903 -
573 lines
23 KiB
ObjectPascal
573 lines
23 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate ARM assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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tarmmoddivnode = class(tmoddivnode)
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function first_moddivint: tnode;override;
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procedure pass_generate_code;override;
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end;
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tarmnotnode = class(tcgnotnode)
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procedure second_boolean;override;
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end;
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tarmunaryminusnode = class(tcgunaryminusnode)
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function pass_1: tnode; override;
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procedure second_float;override;
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end;
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tarmshlshrnode = class(tcgshlshrnode)
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procedure second_64bit;override;
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function first_shlshr64bitint: tnode; override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,constexp,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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symtype,symconst,symtable,
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cgbase,cgobj,hlcgobj,cgutils,
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pass_2,procinfo,
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ncon,ncnv,ncal,
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cpubase,cpuinfo,
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ncgutil,cgcpu,
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nadd,pass_1,symdef;
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{*****************************************************************************
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TARMMODDIVNODE
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*****************************************************************************}
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function tarmmoddivnode.first_moddivint: tnode;
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var
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power : longint;
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begin
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if (right.nodetype=ordconstn) and
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(nodetype=divn) and
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(ispowerof2(tordconstnode(right).value,power) or
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(tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1))
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) and
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not(is_64bitint(resultdef)) then
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result:=nil
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else if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) then
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result:=nil
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else if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
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(nodetype=modn) and
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not(is_64bitint(resultdef)) then
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begin
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if (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) and
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(tordconstnode(right).value<=256) and
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(tordconstnode(right).value>0) then
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result:=caddnode.create(andn,left,cordconstnode.create(tordconstnode(right).value-1,sinttype,false))
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else
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begin
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result:=caddnode.create(subn,left,caddnode.create(muln,right.getcopy, cmoddivnode.Create(divn,left.getcopy,right.getcopy)));
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right:=nil;
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end;
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left:=nil;
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end
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else
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result:=inherited first_moddivint;
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end;
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procedure tarmmoddivnode.pass_generate_code;
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var
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power : longint;
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numerator,
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helper1,
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helper2,
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resultreg : tregister;
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size : Tcgsize;
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so : tshifterop;
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procedure genOrdConstNodeDiv;
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begin
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if tordconstnode(right).value=0 then
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internalerror(2005061701)
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else if tordconstnode(right).value=1 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, numerator, resultreg)
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else if (tordconstnode(right).value = int64(-1)) then
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begin
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// note: only in the signed case possible..., may overflow
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if cs_check_overflow in current_settings.localswitches then
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MVN,
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resultreg,numerator),toppostfix(ord(cs_check_overflow in current_settings.localswitches)*ord(PF_S))));
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end
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else if ispowerof2(tordconstnode(right).value,power) then
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begin
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if (is_signed(right.resultdef)) then
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begin
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helper1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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helper2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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shifterop_reset(so);
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so.shiftmode:=SM_ASR;
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so.shiftimm:=31;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_shifterop(A_MOV,helper1,numerator,so));
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shifterop_reset(so);
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so.shiftmode:=SM_LSR;
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so.shiftimm:=32-power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,helper2,numerator,helper1,so));
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shifterop_reset(so);
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so.shiftmode:=SM_ASR;
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so.shiftimm:=power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_shifterop(A_MOV,resultreg,helper2,so));
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end
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,power,numerator,resultreg)
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end;
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end;
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{
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procedure genOrdConstNodeMod;
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var
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modreg, maskreg, tempreg : tregister;
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begin
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061702);
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end
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else if (abs(tordconstnode(right).value.svalue) = 1) then
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begin
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// x mod +/-1 is always zero
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, 0, resultreg);
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end
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else if (ispowerof2(tordconstnode(right).value, power)) then
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begin
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if (is_signed(right.resultdef)) then begin
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tempreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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maskreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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modreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, abs(tordconstnode(right).value.svalue)-1, modreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, 31, numerator, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, numerator, modreg, tempreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ANDC, maskreg, maskreg, modreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC, modreg, tempreg, 0));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBFE, modreg, modreg, modreg));
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, modreg, maskreg, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_INT, maskreg, tempreg, resultreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, tordconstnode(right).value.svalue-1, numerator, resultreg);
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end;
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end else begin
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genOrdConstNodeDiv();
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_MUL, OS_INT, tordconstnode(right).value.svalue, resultreg, resultreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, resultreg, numerator, resultreg);
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end;
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end;
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}
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begin
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secondpass(left);
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secondpass(right);
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if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
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(nodetype=divn) and
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not(is_64bitint(resultdef)) then
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begin
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size:=def_cgsize(left.resultdef);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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location_copy(location,left.location);
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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if (right.nodetype=ordconstn) and
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((tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1)) or
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(tordconstnode(right).value=0) or
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ispowerof2(tordconstnode(right).value,power)) then
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begin
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numerator:=left.location.register;
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genOrdConstNodeDiv;
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end
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else
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,left.resultdef,true);
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if is_signed(left.resultdef) or
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is_signed(right.resultdef) then
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_IDIV,OS_INT,right.location.register,left.location.register,location.register)
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else
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_DIV,OS_INT,right.location.register,left.location.register,location.register);
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end;
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end
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else
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begin
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resultdef);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,
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left.resultdef,left.resultdef,true);
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location_copy(location,left.location);
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numerator:=location.register;
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resultreg:=location.register;
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if location.loc=LOC_CREGISTER then
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begin
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg:=location.register;
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end
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else if (nodetype=modn) or (right.nodetype=ordconstn) then
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begin
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// for a modulus op, and for const nodes we need the result register
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// to be an extra register
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resultreg:=cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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if right.nodetype=ordconstn then
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begin
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if nodetype=divn then
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genOrdConstNodeDiv
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else
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// genOrdConstNodeMod;
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end;
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location.register:=resultreg;
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end;
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{ unsigned division/module can only overflow in case of division by zero }
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{ (but checking this overflow flag is more convoluted than performing a }
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{ simple comparison with 0) }
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if is_signed(right.resultdef) then
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cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
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end;
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{*****************************************************************************
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TARMNOTNODE
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*****************************************************************************}
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procedure tarmnotnode.second_boolean;
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var
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hl : tasmlabel;
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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}
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if left.expectloc=LOC_JUMP then
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begin
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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secondpass(left);
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if left.location.loc<>LOC_JUMP then
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internalerror(2012081305);
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maketojumpbool(current_asmdata.CurrAsmList,left,lr_load_regvars);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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location.loc:=LOC_JUMP;
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end
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else
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begin
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE,
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LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF :
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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{*****************************************************************************
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TARMUNARYMINUSNODE
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*****************************************************************************}
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function tarmunaryminusnode.pass_1: tnode;
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var
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procname: string[31];
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fdef : tdef;
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begin
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if (current_settings.fputype<>fpu_fpv4_s16) or
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(tfloatdef(resultdef).floattype=s32real) then
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exit(inherited pass_1);
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result:=nil;
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firstpass(left);
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if codegenerror then
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exit;
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if (left.resultdef.typ=floatdef) then
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begin
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case tfloatdef(resultdef).floattype of
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s64real:
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begin
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procname:='float64_sub';
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fdef:=search_system_type('FLOAT64').typedef;
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end;
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else
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internalerror(2005082801);
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end;
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result:=ctypeconvnode.create_internal(ccallnode.createintern(procname,ccallparanode.create(
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ctypeconvnode.create_internal(left,fDef),
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ccallparanode.create(ctypeconvnode.create_internal(crealconstnode.create(0,resultdef),fdef),nil))),resultdef);
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left:=nil;
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end
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else
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begin
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if (left.resultdef.typ=floatdef) then
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expectloc:=LOC_FPUREGISTER
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else if (left.resultdef.typ=orddef) then
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expectloc:=LOC_REGISTER;
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end;
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end;
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procedure tarmunaryminusnode.second_float;
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var
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op: tasmop;
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begin
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secondpass(left);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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location_force_fpureg(current_asmdata.CurrAsmList,left.location,false);
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location:=left.location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSF,
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location.register,left.location.register,0),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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end;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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begin
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location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
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location:=left.location;
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if (left.location.loc=LOC_CMMREGISTER) then
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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if (location.size=OS_F32) then
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op:=A_FNEGS
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else
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op:=A_FNEGD;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
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location.register,left.location.register));
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end;
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fpu_fpv4_s16:
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begin
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location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
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location:=left.location;
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if (left.location.loc=LOC_CMMREGISTER) then
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VNEG,
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location.register,left.location.register), PF_F32));
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end
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else
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internalerror(2009112602);
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end;
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end;
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function tarmshlshrnode.first_shlshr64bitint: tnode;
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begin
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if (current_settings.cputype in cpu_thumb2) then
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result:=inherited
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else
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result := nil;
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end;
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procedure tarmshlshrnode.second_64bit;
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var
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hreg64hi,hreg64lo,shiftreg:Tregister;
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v : TConstExprInt;
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l1,l2,l3:Tasmlabel;
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so: tshifterop;
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procedure emit_instr(p: tai);
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begin
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current_asmdata.CurrAsmList.concat(p);
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end;
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{Reg1 gets shifted and moved into reg2, and is set to zero afterwards}
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procedure shift_more_than_32(reg1, reg2: TRegister; shiftval: Byte ; sm: TShiftMode);
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begin
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shifterop_reset(so); so.shiftimm:=shiftval - 32; so.shiftmode:=sm;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so));
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emit_instr(taicpu.op_reg_const(A_MOV, reg1, 0));
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end;
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procedure shift_less_than_32(reg1, reg2: TRegister; shiftval: Byte; shiftright: boolean);
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begin
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shifterop_reset(so); so.shiftimm:=shiftval;
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
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if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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so.shiftimm:=32-shiftval;
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emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg1, reg1, reg2, so));
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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so.shiftimm:=shiftval;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so));
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end;
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procedure shift_by_variable(reg1, reg2, shiftval: TRegister; shiftright: boolean);
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var
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shiftval2:TRegister;
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begin
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shifterop_reset(so);
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shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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{Do we shift more than 32 bits?}
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emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval, 32), PF_S));
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{This part cares for 32 bits and more}
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emit_instr(setcondition(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval, 32), C_MI));
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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so.rs:=shiftval2;
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emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so), C_MI));
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{Less than 32 bits}
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so.rs:=shiftval;
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emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so), C_PL));
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if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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so.rs:=shiftval2;
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emit_instr(setcondition(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg2, reg2, reg1, so), C_PL));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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{Final adjustments}
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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so.rs:=shiftval;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
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end;
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begin
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if (current_settings.cputype in cpu_thumb2) then
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begin
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inherited;
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exit;
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end;
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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{ load left operator in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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location.register64.reghi:=hreg64hi;
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location.register64.reglo:=hreg64lo;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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v:=Tordconstnode(right).value and 63;
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{Single bit shift}
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if v = 1 then
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if nodetype=shln then
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begin
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{Shift left by one by 2 simple 32bit additions}
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, hreg64lo, hreg64lo, hreg64lo), PF_S));
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emit_instr(taicpu.op_reg_reg_reg(A_ADC, hreg64hi, hreg64hi, hreg64hi));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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end
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else
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begin
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{Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry}
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shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1;
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, hreg64hi, hreg64hi, so), PF_S));
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so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount}
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, hreg64lo, hreg64lo, so));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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end
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{A 32bit shift just replaces a register and clears the other}
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else if v = 32 then
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begin
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if nodetype=shln then
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emit_instr(taicpu.op_reg_const(A_MOV, hreg64hi, 0))
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else
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emit_instr(taicpu.op_reg_const(A_MOV, hreg64lo, 0));
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location.register64.reghi:=hreg64lo;
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location.register64.reglo:=hreg64hi;
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end
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{Shift LESS than 32}
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else if (v < 32) and (v > 1) then
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if nodetype=shln then
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shift_less_than_32(hreg64hi, hreg64lo, v.uvalue, false)
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else
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shift_less_than_32(hreg64lo, hreg64hi, v.uvalue, true)
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{More than 32}
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else if v > 32 then
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if nodetype=shln then
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shift_more_than_32(hreg64lo, hreg64hi, v.uvalue, SM_LSL)
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else
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shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR);
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end
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else
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begin
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{ force right operators in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,false);
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if nodetype = shln then
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shift_by_variable(hreg64lo,hreg64hi,right.location.register, false)
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else
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shift_by_variable(hreg64hi,hreg64lo,right.location.register, true);
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end;
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end;
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begin
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cmoddivnode:=tarmmoddivnode;
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cnotnode:=tarmnotnode;
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cunaryminusnode:=tarmunaryminusnode;
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cshlshrnode:=tarmshlshrnode;
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end.
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