mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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edd42aa42a
future use by high level code generator targets
o this in turn required that all a_load*_loc* methods are called via
hlcg rather than via cg, since a location can be a subsetref/reg and
and those are no longer handled in tcg
o that then required moving several force_location_* routines into
thlcg because they use a_load_loc*, but did not take tdef size
parameters (which are required by the thlcg a_load_loc* routines)
o the only practical consequence is that from now on, you have to
use hlcg.location_force_mem/reg() (fpureg not yet) and
hlcg.gen_load_loc_cgpara() instead of the removed versions from ncgutil,
and hlcg.a_load*loc*() instead of cg.a_load*loc* if a subsetref/reg
might be involved
git-svn-id: trunk@21287 -
127 lines
4.2 KiB
ObjectPascal
127 lines
4.2 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the x86-64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx64add;
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{$i fpcdefs.inc}
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interface
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uses
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node,nadd,cpubase,nx86add;
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type
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tx8664addnode = class(tx86addnode)
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procedure second_addordinal; override;
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procedure second_mul;
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end;
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implementation
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uses
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globtype,globals,
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aasmbase,aasmtai,aasmdata,
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symdef,defutil,
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cgbase,cgutils,cga,cgobj,hlcgobj,
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tgobj;
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{*****************************************************************************
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Addordinal
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*****************************************************************************}
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procedure tx8664addnode.second_addordinal;
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begin
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{ filter unsigned MUL opcode, which requires special handling }
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if (nodetype=muln) and
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(not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef))) then
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begin
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second_mul;
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exit;
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end;
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inherited second_addordinal;
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end;
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{*****************************************************************************
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MUL
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*****************************************************************************}
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procedure tx8664addnode.second_mul;
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var reg:Tregister;
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ref:Treference;
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use_ref:boolean;
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hl4 : tasmlabel;
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begin
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pass_left_right;
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{ The location.register will be filled in later (JM) }
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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{ Mul supports registers and references, so if not register/reference,
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load the location into a register}
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use_ref:=false;
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if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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reg:=left.location.register
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else if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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begin
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ref:=left.location.reference;
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use_ref:=true;
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end
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else
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begin
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{LOC_CONSTANT for example.}
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reg:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,left.resultdef,osuinttype,left.location,reg);
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end;
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{ Allocate RAX. }
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_RAX);
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{ Load the right value. }
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,NR_RAX);
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{ Also allocate RDX, since it is also modified by a mul (JM). }
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_RDX);
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if use_ref then
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emit_ref(A_MUL,S_Q,ref)
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else
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emit_reg(A_MUL,S_Q,reg);
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if cs_check_overflow in current_settings.localswitches then
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begin
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current_asmdata.getjumplabel(hl4);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_AE,hl4);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
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cg.a_label(current_asmdata.CurrAsmList,hl4);
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end;
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{ Free RDX,RAX }
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_RDX);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_RAX);
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{ Allocate a new register and store the result in RAX in it. }
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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emit_reg_reg(A_MOV,S_Q,NR_RAX,location.register);
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location_freetemp(current_asmdata.CurrAsmList,left.location);
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location_freetemp(current_asmdata.CurrAsmList,right.location);
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end;
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begin
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caddnode:=tx8664addnode;
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end.
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