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https://gitlab.com/freepascal.org/fpc/source.git
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b7fe6797bf
http://svn.freepascal.org/svn/fpc/branches/linker/compiler ........ r2921 | peter | 2006-03-15 08:35:00 +0100 (Wed, 15 Mar 2006) | 2 lines * pass ObjectWriter to ObjectOuput ........ r2922 | peter | 2006-03-15 12:40:30 +0100 (Wed, 15 Mar 2006) | 2 lines * refactor asmdata ........ r2925 | peter | 2006-03-15 16:09:39 +0100 (Wed, 15 Mar 2006) | 3 lines * add cfi to asmdata * move asmlist, asmcfi, asmdata to own unit ........ git-svn-id: trunk@2932 -
394 lines
14 KiB
ObjectPascal
394 lines
14 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate PowerPC assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nppcmat;
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{$I fpcdefs.inc}
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interface
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uses
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node, nmat;
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type
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tppcmoddivnode = class(tmoddivnode)
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function pass_1: tnode; override;
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procedure pass_2; override;
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end;
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tppcshlshrnode = class(tshlshrnode)
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procedure pass_2; override;
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end;
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tppcunaryminusnode = class(tunaryminusnode)
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procedure pass_2; override;
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end;
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tppcnotnode = class(tnotnode)
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procedure pass_2; override;
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end;
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implementation
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uses
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sysutils,
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globtype, systems,
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cutils, verbose, globals,
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symconst, symdef,
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aasmbase, aasmcpu, aasmtai,aasmdata,
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defutil,
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cgbase, cgutils, cgobj, pass_1, pass_2,
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ncon, procinfo,
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cpubase, cpuinfo,
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ncgutil, cgcpu, rgobj;
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{*****************************************************************************
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TPPCMODDIVNODE
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*****************************************************************************}
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function tppcmoddivnode.pass_1: tnode;
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begin
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result := inherited pass_1;
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if not assigned(result) then
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include(current_procinfo.flags, pi_do_call);
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end;
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procedure tppcmoddivnode.pass_2;
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const { signed overflow }
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divops: array[boolean, boolean] of tasmop =
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((A_DIVDU, A_DIVDU_),(A_DIVD, A_DIVDO_));
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divcgops : array[boolean] of TOpCG = (OP_DIV, OP_IDIV);
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zerocond: tasmcond = (dirhint: DH_Plus; simple: true; cond:C_NE; cr: RS_CR7);
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tcgsize2native : array[OS_8..OS_S128] of tcgsize = (
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OS_64, OS_64, OS_64, OS_64, OS_NO,
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OS_S64, OS_S64, OS_S64, OS_S64, OS_NO
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);
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var
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power : longint;
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op : tasmop;
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numerator, divider,
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resultreg : tregister;
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size : TCgSize;
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hl : tasmlabel;
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done: boolean;
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procedure genOrdConstNodeMod;
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var
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modreg, maskreg, tempreg : tregister;
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isNegPower : boolean;
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begin
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061702);
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end else if (abs(tordconstnode(right).value) = 1) then begin
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{ x mod +/-1 is always zero }
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, 0, resultreg);
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end else if (ispowerof2(tordconstnode(right).value, power)) then begin
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if (is_signed(right.resulttype.def)) then begin
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tempreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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maskreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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modreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, abs(tordconstnode(right).value)-1, modreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, 63, numerator, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, numerator, modreg, tempreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ANDC, maskreg, maskreg, modreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC, modreg, tempreg, 0));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBFE, modreg, modreg, modreg));
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, modreg, maskreg, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_INT, maskreg, tempreg, resultreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, tordconstnode(right).value-1, numerator,
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resultreg);
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end;
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, divCgOps[is_signed(right.resulttype.def)], OS_INT,
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tordconstnode(right).value, numerator, resultreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_MUL, OS_INT, tordconstnode(right).value, resultreg,
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resultreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, resultreg, numerator, resultreg);
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end;
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end;
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begin
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secondpass(left);
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secondpass(right);
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resulttype.def);
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location_force_reg(current_asmdata.CurrAsmList,left.location,
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size,true);
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location_copy(location,left.location);
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numerator := location.register;
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resultreg := location.register;
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if (location.loc = LOC_CREGISTER) then begin
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg := location.register;
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end else if (nodetype = modn) or (right.nodetype = ordconstn) then begin
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{ for a modulus op, and for const nodes we need the result register
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to be an extra register }
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resultreg := cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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done := false;
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if (cs_opt_level1 in aktoptimizerswitches) and (right.nodetype = ordconstn) then begin
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if (nodetype = divn) then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, divCgOps[is_signed(right.resulttype.def)],
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size, tordconstnode(right).value, numerator, resultreg)
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else
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genOrdConstNodeMod;
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done := true;
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end;
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if (not done) then begin
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{ load divider in a register if necessary }
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location_force_reg(current_asmdata.CurrAsmList,right.location,def_cgsize(right.resulttype.def),true);
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if (right.nodetype <> ordconstn) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_CMPDI, NR_CR7,
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right.location.register, 0))
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else begin
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if (tordconstnode(right).value = 0) then
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internalerror(2005100301);
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end;
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divider := right.location.register;
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{ select the correct opcode according to the sign of the result, whether we need
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overflow checking }
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op := divops[is_signed(right.resulttype.def), cs_check_overflow in aktlocalswitches];
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op, resultreg, numerator,
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divider));
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if (nodetype = modn) then begin
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{ multiply with the divisor again, taking care of the correct size }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULLD,resultreg,
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divider,resultreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUB,location.register,
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numerator,resultreg));
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resultreg := location.register;
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end;
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end;
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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if right.nodetype <> ordconstn then begin
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current_asmdata.getjumplabel(hl);
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current_asmdata.CurrAsmList.concat(taicpu.op_cond_sym(A_BC,zerocond,hl));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIVBYZERO');
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cg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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{ unsigned division/module can only overflow in case of division by zero
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(but checking this overflow flag is more convoluted than performing a
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simple comparison with 0) }
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if is_signed(right.resulttype.def) then
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cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resulttype.def);
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end;
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{*****************************************************************************
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TPPCSHLRSHRNODE
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*****************************************************************************}
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procedure tppcshlshrnode.pass_2;
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var
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resultreg, hregister1, hregister2 : tregister;
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op: topcg;
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asmop1, asmop2: tasmop;
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shiftval: aint;
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begin
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secondpass(left);
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secondpass(right);
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{ load left operators in a register }
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location_force_reg(current_asmdata.CurrAsmList, left.location,
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def_cgsize(left.resulttype.def), true);
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location_copy(location, left.location);
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resultreg := location.register;
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hregister1 := location.register;
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if (location.loc = LOC_CREGISTER) then begin
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location.loc := LOC_REGISTER;
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resultreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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location.register := resultreg;
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end;
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{ determine operator }
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if nodetype = shln then
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op := OP_SHL
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else
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op := OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype = ordconstn) then begin
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// result types with size < 32 bits have their shift values masked
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// differently... :/
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shiftval := tordconstnode(right).value and (tcgsize2size[def_cgsize(resulttype.def)] * 8 -1);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, def_cgsize(resulttype.def),
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shiftval, hregister1, resultreg)
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end else begin
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{ load shift count in a register if necessary }
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location_force_reg(current_asmdata.CurrAsmList, right.location,
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def_cgsize(right.resulttype.def), true);
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hregister2 := right.location.register;
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, op, def_cgsize(resulttype.def), hregister2,
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hregister1, resultreg);
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end;
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end;
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{*****************************************************************************
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TPPCUNARYMINUSNODE
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*****************************************************************************}
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procedure tppcunaryminusnode.pass_2;
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var
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src1: tregister;
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op: tasmop;
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begin
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secondpass(left);
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begin
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location_copy(location, left.location);
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location.loc := LOC_REGISTER;
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case left.location.loc of
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LOC_FPUREGISTER, LOC_REGISTER:
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begin
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src1 := left.location.register;
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location.register := src1;
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end;
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LOC_CFPUREGISTER, LOC_CREGISTER:
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begin
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src1 := left.location.register;
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if left.location.loc = LOC_CREGISTER then
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location.register := cg.getintregister(current_asmdata.CurrAsmList, OS_INT)
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else
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location.register := cg.getfpuregister(current_asmdata.CurrAsmList, location.size);
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end;
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LOC_REFERENCE, LOC_CREFERENCE:
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begin
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if (left.resulttype.def.deftype = floatdef) then begin
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src1 := cg.getfpuregister(current_asmdata.CurrAsmList,
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def_cgsize(left.resulttype.def));
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location.register := src1;
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
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def_cgsize(left.resulttype.def),
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left.location.reference, src1);
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end else begin
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src1 := cg.getintregister(current_asmdata.CurrAsmList, OS_64);
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location.register := src1;
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cg.a_load_ref_reg(current_asmdata.CurrAsmList, OS_64, OS_64,
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left.location.reference, src1);
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end;
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end;
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end;
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{ choose appropriate operand }
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if left.resulttype.def.deftype <> floatdef then begin
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if not (cs_check_overflow in aktlocalswitches) then
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op := A_NEG
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else
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op := A_NEGO_;
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location.loc := LOC_REGISTER;
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end else begin
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op := A_FNEG;
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location.loc := LOC_FPUREGISTER;
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end;
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{ emit operation }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op, location.register, src1));
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end;
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cg.g_overflowcheck(current_asmdata.CurrAsmList, location, resulttype.def);
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end;
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{*****************************************************************************
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TPPCNOTNODE
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*****************************************************************************}
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procedure tppcnotnode.pass_2;
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var
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hl: tasmlabel;
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begin
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if is_boolean(resulttype.def) then
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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}
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if left.expectloc = LOC_JUMP then
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begin
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hl := current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel := current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel := hl;
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secondpass(left);
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maketojumpbool(current_asmdata.CurrAsmList, left, lr_load_regvars);
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hl := current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel := current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel := hl;
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location.loc := LOC_JUMP;
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end
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else
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begin
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS:
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begin
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location_copy(location, left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_CREFERENCE:
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begin
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location_force_reg(current_asmdata.CurrAsmList, left.location,
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def_cgsize(left.resulttype.def), true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMPDI,
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left.location.register, 0));
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location_reset(location, LOC_FLAGS, OS_NO);
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location.resflags.cr := RS_CR0;
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location.resflags.flag := F_EQ;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end
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else
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begin
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secondpass(left);
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location_force_reg(current_asmdata.CurrAsmList, left.location,
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def_cgsize(left.resulttype.def), true);
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location_copy(location, left.location);
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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{ perform the NOT operation }
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cg.a_op_reg_reg(current_asmdata.CurrAsmList, OP_NOT, def_cgsize(resulttype.def),
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left.location.register,
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location.register);
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end;
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end;
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begin
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cmoddivnode := tppcmoddivnode;
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cshlshrnode := tppcshlshrnode;
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cunaryminusnode := tppcunaryminusnode;
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cnotnode := tppcnotnode;
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end.
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