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edd42aa42a
future use by high level code generator targets
o this in turn required that all a_load*_loc* methods are called via
hlcg rather than via cg, since a location can be a subsetref/reg and
and those are no longer handled in tcg
o that then required moving several force_location_* routines into
thlcg because they use a_load_loc*, but did not take tdef size
parameters (which are required by the thlcg a_load_loc* routines)
o the only practical consequence is that from now on, you have to
use hlcg.location_force_mem/reg() (fpureg not yet) and
hlcg.gen_load_loc_cgpara() instead of the removed versions from ncgutil,
and hlcg.a_load*loc*() instead of cg.a_load*loc* if a subsetref/reg
might be involved
git-svn-id: trunk@21287 -
258 lines
9.1 KiB
ObjectPascal
258 lines
9.1 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate m68k assembler for type converting nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n68kcnv;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncnv,ncgcnv,defcmp;
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type
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tm68ktypeconvnode = class(tcgtypeconvnode)
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protected
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function first_int_to_real: tnode; override;
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procedure second_int_to_real;override;
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procedure second_int_to_bool;override;
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// procedure pass_generate_code;override;
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end;
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implementation
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uses
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verbose,globals,systems,
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symconst,symdef,aasmbase,aasmtai,aasmdata,
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defutil,
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cgbase,pass_1,pass_2,
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ncon,ncal,
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ncgutil,
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cpubase,aasmcpu,
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rgobj,tgobj,cgobj,hlcgobj,cgutils,globtype,cgcpu;
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{*****************************************************************************
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FirstTypeConv
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*****************************************************************************}
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function tm68ktypeconvnode.first_int_to_real: tnode;
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var
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fname: string[32];
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begin
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{ In case we are in emulation mode, we must
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always call the helpers
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}
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if (cs_fp_emulation in current_settings.moduleswitches) then
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begin
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result := inherited first_int_to_real;
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exit;
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end
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else
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{ converting a 64bit integer to a float requires a helper }
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if is_64bitint(left.resultdef) then
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begin
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if is_signed(left.resultdef) then
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fname := 'fpc_int64_to_double'
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else
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fname := 'fpc_qword_to_double';
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result := ccallnode.createintern(fname,ccallparanode.create(
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left,nil));
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left:=nil;
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firstpass(result);
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exit;
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end
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else
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{ other integers are supposed to be 32 bit }
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begin
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if is_signed(left.resultdef) then
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inserttypeconv(left,s32inttype)
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else
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{ the fpu always considers 32-bit values as signed
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therefore we need to call the helper in case of
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a cardinal value.
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}
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begin
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fname := 'fpc_longword_to_double';
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result := ccallnode.createintern(fname,ccallparanode.create(
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left,nil));
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left:=nil;
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firstpass(result);
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exit;
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end;
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firstpass(left);
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end;
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result := nil;
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location.loc:=LOC_FPUREGISTER;
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end;
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{*****************************************************************************
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SecondTypeConv
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*****************************************************************************}
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procedure tm68ktypeconvnode.second_int_to_real;
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var
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tempconst: trealconstnode;
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ref: treference;
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valuereg, tempreg, leftreg, tmpfpureg: tregister;
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signed : boolean;
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scratch_used : boolean;
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opsize : tcgsize;
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begin
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scratch_used := false;
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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signed := is_signed(left.resultdef);
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opsize := def_cgsize(left.resultdef);
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{ has to be handled by a helper }
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if is_64bitint(left.resultdef) then
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internalerror(200110011);
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{ has to be handled by a helper }
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if not signed then
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internalerror(20020814);
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,opsize);
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if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,osuinttype,false);
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case left.location.loc of
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LOC_REGISTER, LOC_CREGISTER:
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begin
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leftreg := left.location.register;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FMOVE,TCGSize2OpSize[opsize],leftreg,
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location.register));
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_ref_reg(A_FMOVE,TCGSize2OpSize[opsize],
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left.location.reference,location.register));
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end
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else
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internalerror(200110012);
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end;
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end;
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procedure tm68ktypeconvnode.second_int_to_bool;
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var
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hreg1,
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hreg2 : tregister;
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resflags : tresflags;
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opsize : tcgsize;
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newsize : tcgsize;
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begin
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secondpass(left);
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{ TODO: needs LOC_JUMP support, because called for bool_to_bool from ncgcnv }
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{ Explicit typecasts from any ordinal type to a boolean type }
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{ must not change the ordinal value }
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if (nf_explicit in flags) and
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not(left.location.loc in [LOC_FLAGS,LOC_JUMP]) then
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begin
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location_copy(location,left.location);
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newsize:=def_cgsize(resultdef);
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{ change of size? change sign only if location is LOC_(C)REGISTER? Then we have to sign/zero-extend }
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if (tcgsize2size[newsize]<>tcgsize2size[left.location.size]) or
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((newsize<>left.location.size) and (location.loc in [LOC_REGISTER,LOC_CREGISTER])) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,true)
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else
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location.size:=newsize;
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{ ACTIVATE when loc_jump support is added
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current_procinfo.CurrTrueLabel:=oldTrueLabel;
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current_procinfo.CurrFalseLabel:=oldFalseLabel;
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}
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exit;
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end;
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location_reset(location,LOC_REGISTER,def_cgsize(left.resultdef));
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opsize := def_cgsize(left.resultdef);
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case left.location.loc of
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LOC_CREFERENCE,LOC_REFERENCE :
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begin
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{ can we optimize it, or do we need to fix the ref. ? }
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if isvalidrefoffset(left.location.reference) then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_TST,TCGSize2OpSize[opsize],
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left.location.reference));
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end
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else
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begin
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,opsize,opsize,
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left.location.reference,hreg2);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[opsize],hreg2));
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// cg.ungetcpuregister(current_asmdata.CurrAsmList,hreg2);
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end;
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// reference_release(current_asmdata.CurrAsmList,left.location.reference);
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resflags:=F_NE;
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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end;
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LOC_REGISTER,LOC_CREGISTER :
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begin
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hreg2:=left.location.register;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,TCGSize2OpSize[opsize],hreg2));
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// cg.ungetcpuregister(current_asmdata.CurrAsmList,hreg2);
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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resflags:=F_NE;
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end;
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LOC_FLAGS :
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begin
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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resflags:=left.location.resflags;
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end;
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else
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internalerror(200512182);
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end;
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cg.g_flags2reg(current_asmdata.CurrAsmList,location.size,resflags,hreg1);
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if (is_cbool(resultdef)) then
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,location.size,hreg1,hreg1);
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location.register := hreg1;
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end;
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{
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procedure tm68ktypeconvnode.pass_generate_code;
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{$ifdef TESTOBJEXT2}
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var
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r : preference;
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nillabel : plabel;
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{$endif TESTOBJEXT2}
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begin
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{ this isn't good coding, I think tc_bool_2_int, shouldn't be }
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{ type conversion (FK) }
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if not(convtype in [tc_bool_2_int,tc_bool_2_bool]) then
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begin
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secondpass(left);
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location_copy(location,left.location);
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if codegenerror then
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exit;
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end;
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second_call_helper(convtype);
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end;
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}
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begin
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ctypeconvnode:=tm68ktypeconvnode;
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end.
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