mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 06:31:34 +01:00
406 lines
15 KiB
ObjectPascal
406 lines
15 KiB
ObjectPascal
unit ATmega8HVA;
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interface
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var
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PINA: byte absolute $20; // Port A Input Pins
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DDRA: byte absolute $21; // Port A Data Direction Register
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PORTA: byte absolute $22; // Port A Data Register
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PINB: byte absolute $23; // Input Pins, Port B
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DDRB: byte absolute $24; // Data Direction Register, Port B
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PORTB: byte absolute $25; // Data Register, Port B
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PINC: byte absolute $26; // Port C Input Pins
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PORTC: byte absolute $28; // Port C Data Register
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TIFR0: byte absolute $35; // Timer/Counter Interrupt Flag register
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TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
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OSICSR: byte absolute $37; // Oscillator Sampling Interface Control and Status Register
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EIFR: byte absolute $3C; // External Interrupt Flag Register
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EIMSK: byte absolute $3D; // External Interrupt Mask Register
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GPIOR0: byte absolute $3E; // General Purpose IO Register 0
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EECR: byte absolute $3F; // EEPROM Control Register
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EEDR: byte absolute $40; // EEPROM Data Register
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EEAR: byte absolute $41; // EEPROM Read/Write Access
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GTCCR: byte absolute $43; // General Timer/Counter Control Register
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TCCR0A: byte absolute $44; // Timer/Counter0 Control Register
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TCCR0B: byte absolute $45; // Timer/Counter0 Control Register
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TCNT0: word absolute $46; // Timer Counter 0 Bytes
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TCNT0L: byte absolute $46; // Timer Counter 0 Bytes
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TCNT0H: byte absolute $47; // Timer Counter 0 Bytes;
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OCR0A: byte absolute $48; // Output compare Register A
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OCR0B: byte absolute $49; // Output compare Register B
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GPIOR1: byte absolute $4A; // General Purpose IO Register 1
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GPIOR2: byte absolute $4B; // General Purpose IO Register 2
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SPCR: byte absolute $4C; // SPI Control Register
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SPSR: byte absolute $4D; // SPI Status Register
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SPDR: byte absolute $4E; // SPI Data Register
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SMCR: byte absolute $53; // Sleep Mode Control Register
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MCUSR: byte absolute $54; // MCU Status Register
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MCUCR: byte absolute $55; // MCU Control Register
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SPMCSR: byte absolute $57; // Store Program Memory Control and Status Register
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SP: word absolute $5D; // Stack Pointer
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SPL: byte absolute $5D; // Stack Pointer
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SPH: byte absolute $5E; // Stack Pointer ;
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SREG: byte absolute $5F; // Status Register
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WDTCSR: byte absolute $60; // Watchdog Timer Control Register
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CLKPR: byte absolute $61; // Clock Prescale Register
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PRR0: byte absolute $64; // Power Reduction Register 0
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FOSCCAL: byte absolute $66; // Fast Oscillator Calibration Value
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EICRA: byte absolute $69; // External Interrupt Control Register
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TIMSK0: byte absolute $6E; // Timer/Counter Interrupt Mask Register
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TIMSK1: byte absolute $6F; // Timer/Counter Interrupt Mask Register
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VADC: word absolute $78; // VADC Data Register Bytes
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VADCL: byte absolute $78; // VADC Data Register Bytes
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VADCH: byte absolute $79; // VADC Data Register Bytes;
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VADCSR: byte absolute $7A; // The VADC Control and Status register
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VADMUX: byte absolute $7C; // The VADC multiplexer Selection Register
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DIDR0: byte absolute $7E; // Digital Input Disable Register
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TCCR1A: byte absolute $80; // Timer/Counter 1 Control Register A
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TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
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TCNT1: word absolute $84; // Timer Counter 1 Bytes
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TCNT1L: byte absolute $84; // Timer Counter 1 Bytes
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TCNT1H: byte absolute $85; // Timer Counter 1 Bytes;
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OCR1A: byte absolute $88; // Output Compare Register 1A
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OCR1B: byte absolute $89; // Output Compare Register B
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ROCR: byte absolute $C8; // Regulator Operating Condition Register
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BGCCR: byte absolute $D0; // Bandgap Calibration Register
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BGCRR: byte absolute $D1; // Bandgap Calibration of Resistor Ladder
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CADAC0: byte absolute $E0; // ADC Accumulate Current
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CADAC1: byte absolute $E1; // ADC Accumulate Current
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CADAC2: byte absolute $E2; // ADC Accumulate Current
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CADAC3: byte absolute $E3; // ADC Accumulate Current
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CADCSRA: byte absolute $E4; // CC-ADC Control and Status Register A
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CADCSRB: byte absolute $E5; // CC-ADC Control and Status Register B
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CADRC: byte absolute $E6; // CC-ADC Regular Current
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CADIC: word absolute $E8; // CC-ADC Instantaneous Current
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CADICL: byte absolute $E8; // CC-ADC Instantaneous Current
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CADICH: byte absolute $E9; // CC-ADC Instantaneous Current;
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FCSR: byte absolute $F0; // FET Control and Status Register
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BPIMSK: byte absolute $F2; // Battery Protection Interrupt Mask Register
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BPIFR: byte absolute $F3; // Battery Protection Interrupt Flag Register
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BPSCD: byte absolute $F5; // Battery Protection Short-Circuit Detection Level Register
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BPDOCD: byte absolute $F6; // Battery Protection Discharge-Over-current Detection Level Register
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BPCOCD: byte absolute $F7; // Battery Protection Charge-Over-current Detection Level Register
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BPDHCD: byte absolute $F8; // Battery Protection Discharge-High-current Detection Level Register
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BPCHCD: byte absolute $F9; // Battery Protection Charge-High-current Detection Level Register
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BPSCTR: byte absolute $FA; // Battery Protection Short-current Timing Register
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BPOCTR: byte absolute $FB; // Battery Protection Over-current Timing Register
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BPHCTR: byte absolute $FC; // Battery Protection Short-current Timing Register
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BPCR: byte absolute $FD; // Battery Protection Control Register
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BPPLR: byte absolute $FE; // Battery Protection Parameter Lock Register
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const
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// Port A Data Register
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PA0 = $00;
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PA1 = $01;
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// Data Register, Port B
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PB0 = $00;
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PB1 = $01;
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PB2 = $02;
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PB3 = $03;
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// Port C Data Register
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PC0 = $00;
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// Timer/Counter Interrupt Flag register
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TOV0 = $00;
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OCF0A = $01;
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OCF0B = $02;
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ICF0 = $03;
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// Timer/Counter Interrupt Flag register
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TOV1 = $00;
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OCF1A = $01;
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OCF1B = $02;
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ICF1 = $03;
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// Oscillator Sampling Interface Control and Status Register
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OSIEN = $00;
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OSIST = $01;
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OSISEL0 = $04;
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// External Interrupt Flag Register
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INTF0 = $00; // External Interrupt Flags
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INTF1 = $01; // External Interrupt Flags
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INTF2 = $02; // External Interrupt Flags
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// External Interrupt Mask Register
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INT0 = $00; // External Interrupt Request 2 Enable
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INT1 = $01; // External Interrupt Request 2 Enable
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INT2 = $02; // External Interrupt Request 2 Enable
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// EEPROM Control Register
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EERE = $00;
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EEPE = $01;
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EEMPE = $02;
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EERIE = $03;
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EEPM0 = $04;
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EEPM1 = $05;
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// General Timer/Counter Control Register
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PSRSYNC = $00;
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TSM = $07;
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// Timer/Counter0 Control Register
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WGM00 = $00;
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ICS0 = $03;
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ICES0 = $04;
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ICNC0 = $05;
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ICEN0 = $06;
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TCW0 = $07;
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// Timer/Counter0 Control Register
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CS00 = $00;
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CS01 = $01;
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CS02 = $02;
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// SPI Control Register
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SPR0 = $00; // SPI Clock Rate Selects
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SPR1 = $01; // SPI Clock Rate Selects
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CPHA = $02;
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CPOL = $03;
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MSTR = $04;
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DORD = $05;
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SPE = $06;
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SPIE = $07;
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// SPI Status Register
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SPI2X = $00;
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WCOL = $06;
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SPIF = $07;
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// Sleep Mode Control Register
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SE = $00;
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SM0 = $01; // Sleep Mode Select bits
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SM1 = $02; // Sleep Mode Select bits
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SM2 = $03; // Sleep Mode Select bits
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// MCU Status Register
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PORF = $00;
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EXTRF = $01;
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BODRF = $02;
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WDRF = $03;
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OCDRF = $04;
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// MCU Control Register
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PUD = $04;
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CKOE = $05;
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// Store Program Memory Control and Status Register
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SPMEN = $00;
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PGERS = $01;
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PGWRT = $02;
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RFLB = $03;
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CTPB = $04;
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SIGRD = $05;
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// Status Register
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C = $00;
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Z = $01;
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N = $02;
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V = $03;
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S = $04;
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H = $05;
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T = $06;
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I = $07;
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// Watchdog Timer Control Register
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WDE = $03;
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WDCE = $04;
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WDP0 = $00; // Watchdog Timer Prescaler Bits
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WDP1 = $01; // Watchdog Timer Prescaler Bits
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WDP2 = $02; // Watchdog Timer Prescaler Bits
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WDP3 = $05; // Watchdog Timer Prescaler Bits
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WDIE = $06;
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WDIF = $07;
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// Clock Prescale Register
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CLKPS0 = $00; // Clock Prescaler Select Bits
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CLKPS1 = $01; // Clock Prescaler Select Bits
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CLKPCE = $07;
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// Power Reduction Register 0
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PRVADC = $00;
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PRTIM0 = $01;
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PRTIM1 = $02;
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PRSPI = $03;
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PRVRM = $05;
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// External Interrupt Control Register
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ISC00 = $00; // External Interrupt Sense Control 0 Bits
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ISC01 = $01; // External Interrupt Sense Control 0 Bits
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ISC10 = $02; // External Interrupt Sense Control 1 Bits
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ISC11 = $03; // External Interrupt Sense Control 1 Bits
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ISC20 = $04; // External Interrupt Sense Control 2 Bits
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ISC21 = $05; // External Interrupt Sense Control 2 Bits
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// Timer/Counter Interrupt Mask Register
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TOIE0 = $00;
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OCIE0A = $01;
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OCIE0B = $02;
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ICIE0 = $03;
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// Timer/Counter Interrupt Mask Register
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TOIE1 = $00;
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OCIE1A = $01;
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OCIE1B = $02;
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ICIE1 = $03;
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// The VADC Control and Status register
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VADCCIE = $00;
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VADCCIF = $01;
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VADSC = $02;
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VADEN = $03;
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// The VADC multiplexer Selection Register
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VADMUX0 = $00; // Analog Channel and Gain Selection Bits
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VADMUX1 = $01; // Analog Channel and Gain Selection Bits
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VADMUX2 = $02; // Analog Channel and Gain Selection Bits
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VADMUX3 = $03; // Analog Channel and Gain Selection Bits
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// Digital Input Disable Register
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PA0DID = $00;
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PA1DID = $01;
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// Timer/Counter 1 Control Register A
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WGM10 = $00;
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ICS1 = $03;
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ICES1 = $04;
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ICNC1 = $05;
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ICEN1 = $06;
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TCW1 = $07;
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// Timer/Counter1 Control Register B
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CS10 = $00; // Clock Select1 bis
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CS11 = $01; // Clock Select1 bis
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CS12 = $02; // Clock Select1 bis
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// Regulator Operating Condition Register
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ROCWIE = $00;
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ROCWIF = $01;
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ROCS = $07;
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// Bandgap Calibration Register
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BGCC0 = $00; // BG Calibration of PTAT Current Bits
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BGCC1 = $01; // BG Calibration of PTAT Current Bits
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BGCC2 = $02; // BG Calibration of PTAT Current Bits
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BGCC3 = $03; // BG Calibration of PTAT Current Bits
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BGCC4 = $04; // BG Calibration of PTAT Current Bits
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BGCC5 = $05; // BG Calibration of PTAT Current Bits
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BGD = $07;
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// Bandgap Calibration of Resistor Ladder
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BGCR0 = $00; // Bandgap calibration bits
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BGCR1 = $01; // Bandgap calibration bits
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BGCR2 = $02; // Bandgap calibration bits
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BGCR3 = $03; // Bandgap calibration bits
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BGCR4 = $04; // Bandgap calibration bits
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BGCR5 = $05; // Bandgap calibration bits
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BGCR6 = $06; // Bandgap calibration bits
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BGCR7 = $07; // Bandgap calibration bits
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// CC-ADC Control and Status Register A
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CADSE = $00;
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CADSI0 = $01; // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
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CADSI1 = $02; // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
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CADAS0 = $03; // CC_ADC Accumulate Current Select Bits
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CADAS1 = $04; // CC_ADC Accumulate Current Select Bits
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CADUB = $05;
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CADPOL = $06;
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CADEN = $07;
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// CC-ADC Control and Status Register B
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CADICIF = $00;
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CADRCIF = $01;
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CADACIF = $02;
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CADICIE = $04;
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CADRCIE = $05;
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CADACIE = $06;
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// FET Control and Status Register
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CFE = $00;
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DFE = $01;
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CPS = $02;
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DUVRD = $03;
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// Battery Protection Interrupt Mask Register
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CHCIE = $00;
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DHCIE = $01;
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COCIE = $02;
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DOCIE = $03;
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SCIE = $04;
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// Battery Protection Interrupt Flag Register
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CHCIF = $00;
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DHCIF = $01;
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COCIF = $02;
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DOCIF = $03;
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SCIF = $04;
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// Battery Protection Control Register
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CHCD = $00;
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DHCD = $01;
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COCD = $02;
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DOCD = $03;
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SCD = $04;
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// Battery Protection Parameter Lock Register
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BPPL = $00;
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BPPLE = $01;
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
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procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1
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procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 6 Watchdog Timeout Interrupt
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procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 7 Timer 1 Input capture
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 8 Timer 1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 9 Timer 1 Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 10 Timer 1 overflow
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procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 11 Timer 0 Input Capture
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 12 Timer 0 Comapre Match A
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 13 Timer 0 Compare Match B
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 14 Timer 0 Overflow
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procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 15 SPI Serial transfer complete
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procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 16 Voltage ADC Conversion Complete
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procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 17 Coulomb Counter ADC Conversion Complete
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procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 18 Coloumb Counter ADC Regular Current
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procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 19 Coloumb Counter ADC Accumulator
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 20 EEPROM Ready
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp BPINT_ISR
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rjmp VREGMON_ISR
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp INT2_ISR
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rjmp WDT_ISR
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rjmp TIMER1_IC_ISR
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rjmp TIMER1_COMPA_ISR
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rjmp TIMER1_COMPB_ISR
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rjmp TIMER1_OVF_ISR
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rjmp TIMER0_IC_ISR
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rjmp TIMER0_COMPA_ISR
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rjmp TIMER0_COMPB_ISR
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rjmp TIMER0_OVF_ISR
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rjmp SPI_STC_ISR
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rjmp VADC_ISR
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rjmp CCADC_CONV_ISR
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rjmp CCADC_REG_CUR_ISR
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rjmp CCADC_ACC_ISR
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rjmp EE_READY_ISR
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.weak BPINT_ISR
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.weak VREGMON_ISR
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.weak INT0_ISR
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.weak INT1_ISR
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.weak INT2_ISR
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.weak WDT_ISR
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.weak TIMER1_IC_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_IC_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak TIMER0_OVF_ISR
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.weak SPI_STC_ISR
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.weak VADC_ISR
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.weak CCADC_CONV_ISR
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.weak CCADC_REG_CUR_ISR
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.weak CCADC_ACC_ISR
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.weak EE_READY_ISR
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.set BPINT_ISR, Default_IRQ_handler
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.set VREGMON_ISR, Default_IRQ_handler
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set INT2_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set TIMER1_IC_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_IC_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set SPI_STC_ISR, Default_IRQ_handler
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.set VADC_ISR, Default_IRQ_handler
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.set CCADC_CONV_ISR, Default_IRQ_handler
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.set CCADC_REG_CUR_ISR, Default_IRQ_handler
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.set CCADC_ACC_ISR, Default_IRQ_handler
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.set EE_READY_ISR, Default_IRQ_handler
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end;
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end.
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