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https://gitlab.com/freepascal.org/fpc/source.git
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662 lines
25 KiB
ObjectPascal
662 lines
25 KiB
ObjectPascal
unit ATtiny841;
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interface
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var
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ADCSRB: byte absolute $24; // ADC Control and Status Register B
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ADCSRA: byte absolute $25; // The ADC Control and Status register
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ADC: word absolute $26; // ADC Data Register Bytes
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ADCL: byte absolute $26; // ADC Data Register Bytes
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ADCH: byte absolute $27; // ADC Data Register Bytes;
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ADMUXB: byte absolute $28; // The ADC multiplexer Selection Register B
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ADMUXA: byte absolute $29; // The ADC multiplexer Selection Register A
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ACSR0A: byte absolute $2A; // Analog Comparator 0 Control And Status Register A
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ACSR0B: byte absolute $2B; // Analog Comparator 0 Control And Status Register B
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ACSR1A: byte absolute $2C; // Analog Comparator 1 Control And Status Register A
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ACSR1B: byte absolute $2D; // Analog Comparator 1 Control And Status Register B
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TIFR1: byte absolute $2E; // Timer/Counter Interrupt Flag register
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TIMSK1: byte absolute $2F; // Timer/Counter1 Interrupt Mask Register
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TIFR2: byte absolute $30; // Timer/Counter Interrupt Flag register
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TIMSK2: byte absolute $31; // Timer/Counter2 Interrupt Mask Register
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PCMSK0: byte absolute $32; // Pin Change Enable Mask 0
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GPIOR0: byte absolute $33; // General Purpose I/O Register 0
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GPIOR1: byte absolute $34; // General Purpose I/O Register 1
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GPIOR2: byte absolute $35; // General Purpose I/O Register 2
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PINB: byte absolute $36; // Port B Data register
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DDRB: byte absolute $37; // Data Direction Register, Port B
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PORTB: byte absolute $38; // Input Pins, Port B
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PINA: byte absolute $39; // Port A Input Pins
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DDRA: byte absolute $3A; // Data Direction Register, Port A
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PORTA: byte absolute $3B; // Port A Data Register
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EECR: byte absolute $3C; // EEPROM Control Register
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EEDR: byte absolute $3D; // EEPROM Data Register
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EEAR: word absolute $3E; // EEPROM Address Register Bytes
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EEARL: byte absolute $3E; // EEPROM Address Register Bytes
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EEARH: byte absolute $3F; // EEPROM Address Register Bytes;
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PCMSK1: byte absolute $40; // Pin Change Enable Mask 1
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WDTCSR: byte absolute $41; // Watchdog Timer Control and Status Register
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TCCR1C: byte absolute $42; // Timer/Counter1 Control Register C
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GTCCR: byte absolute $43; // General Timer/Counter Control Register
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ICR1: word absolute $44; // Timer/Counter1 Input Capture Register Bytes
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ICR1L: byte absolute $44; // Timer/Counter1 Input Capture Register Bytes
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ICR1H: byte absolute $45; // Timer/Counter1 Input Capture Register Bytes;
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OCR1B: word absolute $48; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BL: byte absolute $48; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BH: byte absolute $49; // Timer/Counter1 Output Compare Register B Bytes;
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OCR1A: word absolute $4A; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AL: byte absolute $4A; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AH: byte absolute $4B; // Timer/Counter1 Output Compare Register A Bytes;
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TCNT1: word absolute $4C; // Timer/Counter1 Bytes
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TCNT1L: byte absolute $4C; // Timer/Counter1 Bytes
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TCNT1H: byte absolute $4D; // Timer/Counter1 Bytes;
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TCCR1B: byte absolute $4E; // Timer/Counter1 Control Register B
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TCCR1A: byte absolute $4F; // Timer/Counter1 Control Register A
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TCCR0A: byte absolute $50; // Timer/Counter Control Register A
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TCNT0: byte absolute $52; // Timer/Counter0
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TCCR0B: byte absolute $53; // Timer/Counter Control Register B
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MCUSR: byte absolute $54; // MCU Status Register
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MCUCR: byte absolute $55; // MCU Control Register
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OCR0A: byte absolute $56; // Timer/Counter0 Output Compare Register A
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SPMCSR: byte absolute $57; // Store Program Memory Control and Status Register
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TIFR0: byte absolute $58; // Timer/Counter0 Interrupt Flag Register
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TIMSK0: byte absolute $59; // Timer/Counter Interrupt Mask Register
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GIFR: byte absolute $5A; // General Interrupt Flag register
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GIMSK: byte absolute $5B; // General Interrupt Mask Register
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OCR0B: byte absolute $5C; // Timer/Counter0 Output Compare Register B
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SP: word absolute $5D; // Stack Pointer
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SPL: byte absolute $5D; // Stack Pointer
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SPH: byte absolute $5E; // Stack Pointer ;
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SREG: byte absolute $5F; // Status Register
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DIDR0: byte absolute $60; // Digital Input Disable Register 0
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DIDR1: byte absolute $61; // Digital Input Disable Register 1
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PUEB: byte absolute $62; // Pull-up Enable Control Register
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PUEA: byte absolute $63; // Pull-up Enable Control Register
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PORTCR: byte absolute $64; // Port Control Register
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REMAP: byte absolute $65; // Remap Port Pins
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TOCPMCOE: byte absolute $66; // Timer Output Compare Pin Mux Channel Output Enable
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TOCPMSA0: byte absolute $67; // Timer Output Compare Pin Mux Selection 0
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TOCPMSA1: byte absolute $68; // Timer Output Compare Pin Mux Selection 1
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PHDE: byte absolute $6A; // Port High Drive Enable Register
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PRR: byte absolute $70; // Power Reduction Register
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CCP: byte absolute $71; // Configuration Change Protection
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CLKCR: byte absolute $72; // Clock Control Register
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CLKPR: byte absolute $73; // Clock Prescale Register
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OSCCAL0: byte absolute $74; // Oscillator Calibration Register 8MHz
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OSCTCAL0A: byte absolute $75; // Oscillator Temperature Calibration Register A
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OSCTCAL0B: byte absolute $76; // Oscillator Temperature Calibration Register B
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OSCCAL1: byte absolute $77; // Oscillator Calibration Register 32kHz
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UDR0: byte absolute $80; // USART I/O Data Register
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UBRR0: word absolute $81; // USART Baud Rate Register Bytes
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UBRR0L: byte absolute $81; // USART Baud Rate Register Bytes
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UBRR0H: byte absolute $82; // USART Baud Rate Register Bytes;
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UCSR0D: byte absolute $83; // USART Control and Status Register D
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UCSR0C: byte absolute $84; // USART Control and Status Register C
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UCSR0B: byte absolute $85; // USART Control and Status Register B
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UCSR0A: byte absolute $86; // USART Control and Status Register A
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UDR1: byte absolute $90; // USART I/O Data Register
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UBRR1: word absolute $91; // USART Baud Rate Register Bytes
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UBRR1L: byte absolute $91; // USART Baud Rate Register Bytes
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UBRR1H: byte absolute $92; // USART Baud Rate Register Bytes;
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UCSR1D: byte absolute $93; // USART Control and Status Register D
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UCSR1C: byte absolute $94; // USART Control and Status Register C
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UCSR1B: byte absolute $95; // USART Control and Status Register B
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UCSR1A: byte absolute $96; // USART Control and Status Register A
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TWSD: byte absolute $A0; // TWI Slave Data Register
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TWSAM: byte absolute $A1; // TWI Slave Address Mask Register
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TWSA: byte absolute $A2; // TWI Slave Address Register
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TWSSRA: byte absolute $A3; // TWI Slave Status Register A
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TWSCRB: byte absolute $A4; // TWI Slave Control Register B
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TWSCRA: byte absolute $A5; // TWI Slave Control Register A
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SPDR: byte absolute $B0; // SPI Data Register
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SPSR: byte absolute $B1; // SPI Status Register
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SPCR: byte absolute $B2; // SPI Control Register
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ICR2: word absolute $C0; // Timer/Counter2 Input Capture Register Bytes
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ICR2L: byte absolute $C0; // Timer/Counter2 Input Capture Register Bytes
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ICR2H: byte absolute $C1; // Timer/Counter2 Input Capture Register Bytes;
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OCR2B: word absolute $C2; // Timer/Counter2 Output Compare Register B Bytes
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OCR2BL: byte absolute $C2; // Timer/Counter2 Output Compare Register B Bytes
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OCR2BH: byte absolute $C3; // Timer/Counter2 Output Compare Register B Bytes;
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OCR2A: word absolute $C4; // Timer/Counter2 Output Compare Register A Bytes
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OCR2AL: byte absolute $C4; // Timer/Counter2 Output Compare Register A Bytes
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OCR2AH: byte absolute $C5; // Timer/Counter2 Output Compare Register A Bytes;
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TCNT2: word absolute $C6; // Timer/Counter2 Bytes
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TCNT2L: byte absolute $C6; // Timer/Counter2 Bytes
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TCNT2H: byte absolute $C7; // Timer/Counter2 Bytes;
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TCCR2C: byte absolute $C8; // Timer/Counter2 Control Register C
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TCCR2B: byte absolute $C9; // Timer/Counter2 Control Register B
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TCCR2A: byte absolute $CA; // Timer/Counter2 Control Register A
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const
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// ADC Control and Status Register B
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ADTS0 = $00; // ADC Auto Trigger Sources
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ADTS1 = $01; // ADC Auto Trigger Sources
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ADTS2 = $02; // ADC Auto Trigger Sources
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ADLAR = $03;
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// The ADC Control and Status register
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ADPS0 = $00; // ADC Prescaler Select Bits
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ADPS1 = $01; // ADC Prescaler Select Bits
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ADPS2 = $02; // ADC Prescaler Select Bits
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ADIE = $03;
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ADIF = $04;
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ADATE = $05;
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ADSC = $06;
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ADEN = $07;
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// The ADC multiplexer Selection Register B
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GSEL0 = $00; // Gain Selection Bits
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GSEL1 = $01; // Gain Selection Bits
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REFS0 = $05; // Reference Selection Bits
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REFS1 = $06; // Reference Selection Bits
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REFS2 = $07; // Reference Selection Bits
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// The ADC multiplexer Selection Register A
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MUX0 = $00; // Analog Channel and Gain Selection Bits
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MUX1 = $01; // Analog Channel and Gain Selection Bits
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MUX2 = $02; // Analog Channel and Gain Selection Bits
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MUX3 = $03; // Analog Channel and Gain Selection Bits
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MUX4 = $04; // Analog Channel and Gain Selection Bits
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MUX5 = $05; // Analog Channel and Gain Selection Bits
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// Analog Comparator 0 Control And Status Register A
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ACIS00 = $00; // Analog Comparator 0 Interrupt Mode Select bits
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ACIS01 = $01; // Analog Comparator 0 Interrupt Mode Select bits
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ACIC0 = $02;
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ACIE0 = $03;
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ACI0 = $04;
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ACO0 = $05;
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ACPMUX2 = $06;
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ACD0 = $07;
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// Analog Comparator 0 Control And Status Register B
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ACPMUX0 = $00; // Analog Comparator 0 Positive Input Multiplexer Bits 1:0
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ACPMUX1 = $01; // Analog Comparator 0 Positive Input Multiplexer Bits 1:0
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ACNMUX0 = $02; // Analog Comparator 0 Negative Input Multiplexer
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ACNMUX1 = $03; // Analog Comparator 0 Negative Input Multiplexer
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ACOE0 = $04;
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HLEV0 = $06;
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HSEL0 = $07;
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// Analog Comparator 1 Control And Status Register A
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ACIS10 = $00; // Analog Comparator 1 Interrupt Mode Select bits
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ACIS11 = $01; // Analog Comparator 1 Interrupt Mode Select bits
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ACIC1 = $02;
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ACIE1 = $03;
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ACI1 = $04;
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ACO1 = $05;
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ACBG1 = $06;
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ACD1 = $07;
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// Analog Comparator 1 Control And Status Register B
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ACME1 = $02;
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ACOE1 = $04;
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HLEV1 = $06;
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HSEL1 = $07;
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// Timer/Counter Interrupt Flag register
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TOV1 = $00;
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OCF1A = $01;
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OCF1B = $02;
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ICF1 = $05;
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// Timer/Counter1 Interrupt Mask Register
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TOIE1 = $00;
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OCIE1A = $01;
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OCIE1B = $02;
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ICIE1 = $05;
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// Timer/Counter Interrupt Flag register
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TOV2 = $00;
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OCF2A = $01;
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OCF2B = $02;
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ICF2 = $05;
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// Timer/Counter2 Interrupt Mask Register
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TOIE2 = $00;
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OCIE2A = $01;
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OCIE2B = $02;
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ICIE2 = $05;
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// Pin Change Enable Mask 0
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PCINT0 = $00;
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PCINT1 = $01;
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PCINT2 = $02;
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PCINT3 = $03;
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PCINT4 = $04;
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PCINT5 = $05;
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PCINT6 = $06;
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PCINT7 = $07;
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// Input Pins, Port B
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PB0 = $00;
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PB1 = $01;
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PB2 = $02;
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PB3 = $03;
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// Port A Data Register
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PA0 = $00;
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PA1 = $01;
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PA2 = $02;
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PA3 = $03;
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PA4 = $04;
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PA5 = $05;
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PA6 = $06;
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PA7 = $07;
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// EEPROM Control Register
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EERE = $00;
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EEPE = $01;
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EEMPE = $02;
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EERIE = $03;
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EEPM0 = $04; // EEPROM Programming Mode Bits
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EEPM1 = $05; // EEPROM Programming Mode Bits
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// Pin Change Enable Mask 1
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PCINT8 = $00;
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PCINT9 = $01;
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PCINT10 = $02;
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PCINT11 = $03;
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// Watchdog Timer Control and Status Register
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WDE = $03;
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WDP0 = $00; // Watchdog Timer Prescaler Bits
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WDP1 = $01; // Watchdog Timer Prescaler Bits
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WDP2 = $02; // Watchdog Timer Prescaler Bits
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WDP3 = $05; // Watchdog Timer Prescaler Bits
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WDIE = $06;
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WDIF = $07;
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// Timer/Counter1 Control Register C
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FOC1B = $06;
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FOC1A = $07;
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// General Timer/Counter Control Register
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PSR = $00;
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TSM = $07;
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// Timer/Counter1 Control Register B
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CS10 = $00; // Clock Select bits
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CS11 = $01; // Clock Select bits
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CS12 = $02; // Clock Select bits
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ICES1 = $06;
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ICNC1 = $07;
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// Timer/Counter1 Control Register A
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WGM10 = $00; // Pulse Width Modulator Select Bits
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WGM11 = $01; // Pulse Width Modulator Select Bits
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COM1B0 = $04; // Compare Output Mode 1B, bits
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COM1B1 = $05; // Compare Output Mode 1B, bits
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COM1A0 = $06; // Compare Output Mode 1A, bits
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COM1A1 = $07; // Compare Output Mode 1A, bits
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// Timer/Counter Control Register A
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WGM00 = $00; // Waveform Generation Mode bits
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WGM01 = $01; // Waveform Generation Mode bits
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COM0B0 = $04; // Compare Match Output B Mode bits
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COM0B1 = $05; // Compare Match Output B Mode bits
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COM0A0 = $06; // Compare Match Output A Mode bits
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COM0A1 = $07; // Compare Match Output A Mode bits
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// Timer/Counter Control Register B
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CS00 = $00; // Clock Select bits
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CS01 = $01; // Clock Select bits
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CS02 = $02; // Clock Select bits
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WGM02 = $03;
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FOC0B = $06;
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FOC0A = $07;
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// MCU Status Register
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PORF = $00;
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EXTRF = $01;
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BORF = $02;
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WDRF = $03;
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// MCU Control Register
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ISC00 = $00; // Interrupt Sense Control 0 bits
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ISC01 = $01; // Interrupt Sense Control 0 bits
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SM0 = $03; // Sleep Mode Select Bits
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SM1 = $04; // Sleep Mode Select Bits
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SE = $05;
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// Store Program Memory Control and Status Register
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SPMEN = $00;
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PGERS = $01;
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PGWRT = $02;
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RFLB = $03;
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CTPB = $04;
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RSIG = $05;
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// Timer/Counter0 Interrupt Flag Register
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TOV0 = $00;
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OCF0A = $01;
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OCF0B = $02;
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// Timer/Counter Interrupt Mask Register
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TOIE0 = $00;
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OCIE0A = $01;
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OCIE0B = $02;
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// General Interrupt Flag register
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PCIF0 = $04; // Pin Change Interrupt Flags
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PCIF1 = $05; // Pin Change Interrupt Flags
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INTF0 = $06;
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// General Interrupt Mask Register
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PCIE0 = $04; // Pin Change Interrupt Enables
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PCIE1 = $05; // Pin Change Interrupt Enables
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INT0 = $06;
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// Status Register
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C = $00;
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Z = $01;
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N = $02;
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V = $03;
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S = $04;
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H = $05;
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T = $06;
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I = $07;
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// Digital Input Disable Register 0
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ADC0D = $00;
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ADC1D = $01;
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ADC2D = $02;
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ADC3D = $03;
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ADC4D = $04;
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ADC5D = $05;
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ADC6D = $06;
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ADC7D = $07;
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// Digital Input Disable Register 1
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ADC11D = $00;
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ADC10D = $01;
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ADC8D = $02;
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ADC9D = $03;
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// Port Control Register
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BBMA = $00;
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BBMB = $01;
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// Remap Port Pins
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U0MAP = $00;
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SPIMAP = $01;
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// Timer Output Compare Pin Mux Channel Output Enable
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TOCC0OE = $00;
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TOCC1OE = $01;
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TOCC2OE = $02;
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TOCC3OE = $03;
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TOCC4OE = $04;
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TOCC5OE = $05;
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TOCC6OE = $06;
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TOCC7OE = $07;
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// Timer Output Compare Pin Mux Selection 0
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TOCC0S0 = $00; // Timer Output Compare Channel 0 Selection Bits
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TOCC0S1 = $01; // Timer Output Compare Channel 0 Selection Bits
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TOCC1S0 = $02; // Timer Output Compare Channel 1 Selection Bits
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TOCC1S1 = $03; // Timer Output Compare Channel 1 Selection Bits
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TOCC2S0 = $04; // Timer Output Compare Channel 2 Selection Bits
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TOCC2S1 = $05; // Timer Output Compare Channel 2 Selection Bits
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TOCC3S0 = $06; // Timer Output Compare Channel 3 Selection Bits
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TOCC3S1 = $07; // Timer Output Compare Channel 3 Selection Bits
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// Timer Output Compare Pin Mux Selection 1
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TOCC4S0 = $00; // Timer Output Compare Channel 4 Selection Bits
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TOCC4S1 = $01; // Timer Output Compare Channel 4 Selection Bits
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TOCC5S0 = $02; // Timer Output Compare Channel 5 Selection Bits
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TOCC5S1 = $03; // Timer Output Compare Channel 5 Selection Bits
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TOCC6S0 = $04; // Timer Output Compare Channel 6 Selection Bits
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TOCC6S1 = $05; // Timer Output Compare Channel 6 Selection Bits
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TOCC7S0 = $06; // Timer Output Compare Channel 7 Selection Bits
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TOCC7S1 = $07; // Timer Output Compare Channel 7 Selection Bits
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// Port High Drive Enable Register
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PHDEA0 = $00; // PortA High Drive Enable
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PHDEA1 = $01; // PortA High Drive Enable
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// Power Reduction Register
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PRADC = $00;
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PRTIM0 = $01;
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PRTIM1 = $02;
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PRTIM2 = $03;
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PRSPI = $04;
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PRUSART0 = $05;
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PRUSART1 = $06;
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PRTWI = $07;
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// Clock Control Register
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CKSEL0 = $00; // Clock Select Bits
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CKSEL1 = $01; // Clock Select Bits
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CKSEL2 = $02; // Clock Select Bits
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CKSEL3 = $03; // Clock Select Bits
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SUT = $04;
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CKOUTC = $05;
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CSTR = $06;
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OSCRDY = $07;
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// Clock Prescale Register
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CLKPS0 = $00; // Clock Prescaler Select Bits
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CLKPS1 = $01; // Clock Prescaler Select Bits
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CLKPS2 = $02; // Clock Prescaler Select Bits
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CLKPS3 = $03; // Clock Prescaler Select Bits
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// USART Control and Status Register D
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SFDE0 = $05;
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RXS0 = $06;
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RXSIE0 = $07;
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// USART Control and Status Register C
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UCPOL0 = $00;
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UCSZ00 = $01; // Character Size
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UCSZ01 = $02; // Character Size
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USBS0 = $03;
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UPM00 = $04; // Parity Mode Bits
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UPM01 = $05; // Parity Mode Bits
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UMSEL00 = $06; // USART Mode Select
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UMSEL01 = $07; // USART Mode Select
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// USART Control and Status Register B
|
|
TXB80 = $00;
|
|
RXB80 = $01;
|
|
UCSZ02 = $02;
|
|
TXEN0 = $03;
|
|
RXEN0 = $04;
|
|
UDRIE0 = $05;
|
|
TXCIE0 = $06;
|
|
RXCIE0 = $07;
|
|
// USART Control and Status Register A
|
|
MPCM0 = $00;
|
|
U2X0 = $01;
|
|
UPE0 = $02;
|
|
DOR0 = $03;
|
|
FE0 = $04;
|
|
UDRE0 = $05;
|
|
TXC0 = $06;
|
|
RXC0 = $07;
|
|
// USART Control and Status Register D
|
|
SFDE1 = $05;
|
|
RXS1 = $06;
|
|
RXSIE1 = $07;
|
|
// USART Control and Status Register C
|
|
UCPOL1 = $00;
|
|
UCSZ10 = $01; // Character Size
|
|
UCSZ11 = $02; // Character Size
|
|
USBS1 = $03;
|
|
UPM10 = $04; // Parity Mode Bits
|
|
UPM11 = $05; // Parity Mode Bits
|
|
UMSEL10 = $06; // USART Mode Select
|
|
UMSEL11 = $07; // USART Mode Select
|
|
// USART Control and Status Register B
|
|
TXB81 = $00;
|
|
RXB81 = $01;
|
|
UCSZ12 = $02;
|
|
TXEN1 = $03;
|
|
RXEN1 = $04;
|
|
UDRIE1 = $05;
|
|
TXCIE1 = $06;
|
|
RXCIE1 = $07;
|
|
// USART Control and Status Register A
|
|
MPCM1 = $00;
|
|
U2X1 = $01;
|
|
UPE1 = $02;
|
|
DOR1 = $03;
|
|
FE1 = $04;
|
|
UDRE1 = $05;
|
|
TXC1 = $06;
|
|
RXC1 = $07;
|
|
// TWI Slave Data Register
|
|
TWSD0 = $00; // TWI slave data bit
|
|
TWSD1 = $01; // TWI slave data bit
|
|
TWSD2 = $02; // TWI slave data bit
|
|
TWSD3 = $03; // TWI slave data bit
|
|
TWSD4 = $04; // TWI slave data bit
|
|
TWSD5 = $05; // TWI slave data bit
|
|
TWSD6 = $06; // TWI slave data bit
|
|
TWSD7 = $07; // TWI slave data bit
|
|
// TWI Slave Address Mask Register
|
|
TWAE = $00;
|
|
TWSAM1 = $01; // TWI Address Mask Bits
|
|
TWSAM2 = $02; // TWI Address Mask Bits
|
|
TWSAM3 = $03; // TWI Address Mask Bits
|
|
TWSAM4 = $04; // TWI Address Mask Bits
|
|
TWSAM5 = $05; // TWI Address Mask Bits
|
|
TWSAM6 = $06; // TWI Address Mask Bits
|
|
TWSAM7 = $07; // TWI Address Mask Bits
|
|
// TWI Slave Status Register A
|
|
TWAS = $00;
|
|
TWDIR = $01;
|
|
TWBE = $02;
|
|
TWC = $03;
|
|
TWRA = $04;
|
|
TWCH = $05;
|
|
TWASIF = $06;
|
|
TWDIF = $07;
|
|
// TWI Slave Control Register B
|
|
TWCMD0 = $00;
|
|
TWCMD1 = $01;
|
|
TWAA = $02;
|
|
TWHNM = $03;
|
|
// TWI Slave Control Register A
|
|
TWSME = $00;
|
|
TWPME = $01;
|
|
TWSIE = $02;
|
|
TWEN = $03;
|
|
TWASIE = $04;
|
|
TWDIE = $05;
|
|
TWSHE = $07;
|
|
// SPI Status Register
|
|
SPI2X = $00;
|
|
WCOL = $06;
|
|
SPIF = $07;
|
|
// SPI Control Register
|
|
SPR0 = $00; // SPI Clock Rate Selects
|
|
SPR1 = $01; // SPI Clock Rate Selects
|
|
CPHA = $02;
|
|
CPOL = $03;
|
|
MSTR = $04;
|
|
DORD = $05;
|
|
SPE = $06;
|
|
SPIE = $07;
|
|
// Timer/Counter2 Control Register C
|
|
FOC2B = $06;
|
|
FOC2A = $07;
|
|
// Timer/Counter2 Control Register B
|
|
CS20 = $00; // Clock Select bits
|
|
CS21 = $01; // Clock Select bits
|
|
CS22 = $02; // Clock Select bits
|
|
ICES2 = $06;
|
|
ICNC2 = $07;
|
|
// Timer/Counter2 Control Register A
|
|
WGM20 = $00; // Pulse Width Modulator Select Bits
|
|
WGM21 = $01; // Pulse Width Modulator Select Bits
|
|
COM2B0 = $04; // Compare Output Mode 2B, bits
|
|
COM2B1 = $05; // Compare Output Mode 2B, bits
|
|
COM2A0 = $06; // Compare Output Mode 2A, bits
|
|
COM2A1 = $07; // Compare Output Mode 2A, bits
|
|
|
|
|
|
implementation
|
|
{$define RELBRANCHES}
|
|
{$i avrcommon.inc}
|
|
|
|
procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
|
|
procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
|
|
procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
|
|
procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 4 Watchdog Time-out Interrupt
|
|
procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 5 Timer/Counter1 Capture Event
|
|
procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 6 Timer/Counter1 Compare Match A
|
|
procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 7 Timer/Counter1 Compare Match B
|
|
procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 8 Timer/Counter1 Overflow
|
|
procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 9 TimerCounter0 Compare Match A
|
|
procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 10 TimerCounter0 Compare Match B
|
|
procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 11 Timer/Couner0 Overflow
|
|
procedure ANA_COMP0_ISR; external name 'ANA_COMP0_ISR'; // Interrupt 12 Analog Comparator 0
|
|
procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 13 ADC Conversion Complete
|
|
procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 14 EEPROM Ready
|
|
procedure ANA_COMP1_ISR; external name 'ANA_COMP1_ISR'; // Interrupt 15 Analog Comparator 1
|
|
procedure TIMER2_CAPT_ISR; external name 'TIMER2_CAPT_ISR'; // Interrupt 16 Timer/Counter2 Capture Event
|
|
procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 17 Timer/Counter2 Compare Match A
|
|
procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 18 Timer/Counter2 Compare Match B
|
|
procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 19 Timer/Counter2 Overflow
|
|
procedure SPI_ISR; external name 'SPI_ISR'; // Interrupt 20 Serial Peripheral Interface
|
|
procedure USART0_START_ISR; external name 'USART0_START_ISR'; // Interrupt 21 USART0, Start
|
|
procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 22 USART0, Rx Complete
|
|
procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 23 USART0 Data Register Empty
|
|
procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 24 USART0, Tx Complete
|
|
procedure USART1_START_ISR; external name 'USART1_START_ISR'; // Interrupt 25 USART1, Start
|
|
procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 26 USART1, Rx Complete
|
|
procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 27 USART1 Data Register Empty
|
|
procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 28 USART1, Tx Complete
|
|
procedure TWI_SLAVE_ISR; external name 'TWI_SLAVE_ISR'; // Interrupt 29 Two-wire Serial Interface
|
|
|
|
procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
|
|
asm
|
|
rjmp __dtors_end
|
|
rjmp INT0_ISR
|
|
rjmp PCINT0_ISR
|
|
rjmp PCINT1_ISR
|
|
rjmp WDT_ISR
|
|
rjmp TIMER1_CAPT_ISR
|
|
rjmp TIMER1_COMPA_ISR
|
|
rjmp TIMER1_COMPB_ISR
|
|
rjmp TIMER1_OVF_ISR
|
|
rjmp TIMER0_COMPA_ISR
|
|
rjmp TIMER0_COMPB_ISR
|
|
rjmp TIMER0_OVF_ISR
|
|
rjmp ANA_COMP0_ISR
|
|
rjmp ADC_ISR
|
|
rjmp EE_RDY_ISR
|
|
rjmp ANA_COMP1_ISR
|
|
rjmp TIMER2_CAPT_ISR
|
|
rjmp TIMER2_COMPA_ISR
|
|
rjmp TIMER2_COMPB_ISR
|
|
rjmp TIMER2_OVF_ISR
|
|
rjmp SPI_ISR
|
|
rjmp USART0_START_ISR
|
|
rjmp USART0_RX_ISR
|
|
rjmp USART0_UDRE_ISR
|
|
rjmp USART0_TX_ISR
|
|
rjmp USART1_START_ISR
|
|
rjmp USART1_RX_ISR
|
|
rjmp USART1_UDRE_ISR
|
|
rjmp USART1_TX_ISR
|
|
rjmp TWI_SLAVE_ISR
|
|
|
|
.weak INT0_ISR
|
|
.weak PCINT0_ISR
|
|
.weak PCINT1_ISR
|
|
.weak WDT_ISR
|
|
.weak TIMER1_CAPT_ISR
|
|
.weak TIMER1_COMPA_ISR
|
|
.weak TIMER1_COMPB_ISR
|
|
.weak TIMER1_OVF_ISR
|
|
.weak TIMER0_COMPA_ISR
|
|
.weak TIMER0_COMPB_ISR
|
|
.weak TIMER0_OVF_ISR
|
|
.weak ANA_COMP0_ISR
|
|
.weak ADC_ISR
|
|
.weak EE_RDY_ISR
|
|
.weak ANA_COMP1_ISR
|
|
.weak TIMER2_CAPT_ISR
|
|
.weak TIMER2_COMPA_ISR
|
|
.weak TIMER2_COMPB_ISR
|
|
.weak TIMER2_OVF_ISR
|
|
.weak SPI_ISR
|
|
.weak USART0_START_ISR
|
|
.weak USART0_RX_ISR
|
|
.weak USART0_UDRE_ISR
|
|
.weak USART0_TX_ISR
|
|
.weak USART1_START_ISR
|
|
.weak USART1_RX_ISR
|
|
.weak USART1_UDRE_ISR
|
|
.weak USART1_TX_ISR
|
|
.weak TWI_SLAVE_ISR
|
|
|
|
.set INT0_ISR, Default_IRQ_handler
|
|
.set PCINT0_ISR, Default_IRQ_handler
|
|
.set PCINT1_ISR, Default_IRQ_handler
|
|
.set WDT_ISR, Default_IRQ_handler
|
|
.set TIMER1_CAPT_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER1_OVF_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER0_OVF_ISR, Default_IRQ_handler
|
|
.set ANA_COMP0_ISR, Default_IRQ_handler
|
|
.set ADC_ISR, Default_IRQ_handler
|
|
.set EE_RDY_ISR, Default_IRQ_handler
|
|
.set ANA_COMP1_ISR, Default_IRQ_handler
|
|
.set TIMER2_CAPT_ISR, Default_IRQ_handler
|
|
.set TIMER2_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER2_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER2_OVF_ISR, Default_IRQ_handler
|
|
.set SPI_ISR, Default_IRQ_handler
|
|
.set USART0_START_ISR, Default_IRQ_handler
|
|
.set USART0_RX_ISR, Default_IRQ_handler
|
|
.set USART0_UDRE_ISR, Default_IRQ_handler
|
|
.set USART0_TX_ISR, Default_IRQ_handler
|
|
.set USART1_START_ISR, Default_IRQ_handler
|
|
.set USART1_RX_ISR, Default_IRQ_handler
|
|
.set USART1_UDRE_ISR, Default_IRQ_handler
|
|
.set USART1_TX_ISR, Default_IRQ_handler
|
|
.set TWI_SLAVE_ISR, Default_IRQ_handler
|
|
end;
|
|
|
|
end.
|