tom_at_work 4e60ceb237 * removed code which splits "unaligned" 8 byte stores/loads into two 4 bytes stores/loads on ppc64. The processor manuals and extensive testing showed that PPC970+ class processors have hardware assisted handling of unaligned memory accesses, which results in 8 byte memory accesses to be always faster than 4 byte ones ... git-svn-id: trunk@9721 -		2008-01-12 13:47:55 +00:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	* removed code which splits "unaligned" 8 byte stores/loads into two 4 bytes stores/loads on ppc64. The processor manuals and extensive testing showed that PPC970+ class processors have hardware assisted handling of unaligned memory accesses, which results in 8 byte memory accesses to be always faster than 4 byte ones	2008-01-12 13:47:55 +00:00
cpubase.pas	+ default code now preserves mm registers	2007-10-27 12:02:28 +00:00
cpuinfo.pas
cpunode.pas
cpupara.pas	* treat procvardef parameters the same as records (fixes webtbs/tw9141)	2007-09-06 17:35:50 +00:00
cpupi.pas	+ PIC support for darwin/ppc64	2007-10-20 20:14:45 +00:00
cputarg.pas
itcpugas.pas	* r8717 for ppc64 (fixed compilation after r8715)	2007-10-02 08:31:04 +00:00
nppcadd.pas
nppccal.pas
nppccnv.pas	* remove registers{int/mmx/fpu} from firstpass	2007-09-26 21:12:01 +00:00
nppcld.pas
nppcmat.pas
ppcins.dat
ppcreg.dat
rappc.pas
rappcgas.pas	+ PIC support for darwin/ppc64	2007-10-20 20:14:45 +00:00
rppccon.inc
rppcdwrf.inc
rppcgas.inc
rppcgri.inc
rppcgss.inc
rppcmot.inc
rppcmri.inc
rppcnor.inc
rppcnum.inc
rppcrni.inc
rppcsri.inc
rppcstab.inc
rppcstd.inc
rppcsup.inc