mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-15 01:39:27 +02:00
54d3d736f5
and add usermode parsing of LDM/STM ops
This patch basically extends the ARM assembly reader a bit to properly parse CPSR and
SPSR flags for the MSR opcode, and allows the reader to understand
the ^ modifer for register lists for STMxx and LDMxx.
Previously the following combinations weren't possible in straight assembler:
MRS R0, CPSR
MRS R0, SPSR
MSR CPSR_CX, R0
LDMIA SP, {R0-R15}^
etc..
git-svn-id: trunk@22502 -
112 lines
2.7 KiB
Plaintext
112 lines
2.7 KiB
Plaintext
;
|
|
; ARM registers
|
|
;
|
|
; layout
|
|
; <name>,<type>,<subtype>,<value>,<stdname>,<stab idx>,<dwarf idx>
|
|
;
|
|
NO,$00,$00,$00,INVALID,-1,-1
|
|
; Integer registers
|
|
R0,$01,$00,$00,r0,0,0
|
|
R1,$01,$00,$01,r1,1,1
|
|
R2,$01,$00,$02,r2,2,2
|
|
R3,$01,$00,$03,r3,3,3
|
|
R4,$01,$00,$04,r4,4,4
|
|
R5,$01,$00,$05,r5,5,5
|
|
R6,$01,$00,$06,r6,6,6
|
|
R7,$01,$00,$07,r7,7,7
|
|
R8,$01,$00,$08,r8,8,8
|
|
R9,$01,$00,$09,r9,9,9
|
|
R10,$01,$00,$0a,r10,10,10
|
|
R11,$01,$00,$0b,r11,11,11
|
|
R12,$01,$00,$0c,r12,12,12
|
|
R13,$01,$00,$0d,r13,13,13
|
|
R14,$01,$00,$0e,r14,14,14
|
|
R15,$01,$00,$0f,r15,15,15
|
|
|
|
; Float registers
|
|
F0,$02,$00,$00,f0,32,16
|
|
F1,$02,$00,$01,f1,32,17
|
|
F2,$02,$00,$02,f2,32,18
|
|
F3,$02,$00,$03,f3,32,19
|
|
F4,$02,$00,$04,f4,32,20
|
|
F5,$02,$00,$05,f5,32,21
|
|
F6,$02,$00,$06,f6,32,22
|
|
F7,$02,$00,$07,f7,32,23
|
|
|
|
; MM registers
|
|
; odd numbered single registers must not be made available to the register
|
|
; allocator because it cannot deal with D0 conflicting with both S0 and S1.
|
|
; This unfortunately means that we can only use 16 single precision registers
|
|
; instead of 32, even if no double precision ones are used...
|
|
; Nevertheless the odd numbered single registers must have seperate register
|
|
; numbers to allow implementation of the "EABI VFP hardfloat" calling convention.
|
|
|
|
S0,$04,$06,$00,s0,0,0
|
|
S1,$04,$06,$20,s1,0,0
|
|
D0,$04,$07,$00,d0,0,0
|
|
S2,$04,$06,$01,s2,0,0
|
|
S3,$04,$06,$21,s3,0,0
|
|
D1,$04,$07,$01,d1,0,0
|
|
S4,$04,$06,$02,s4,0,0
|
|
S5,$04,$06,$22,s5,0,0
|
|
D2,$04,$07,$02,d2,0,0
|
|
S6,$04,$06,$03,s6,0,0
|
|
S7,$04,$06,$23,s7,0,0
|
|
D3,$04,$07,$03,d3,0,0
|
|
S8,$04,$06,$04,s8,0,0
|
|
S9,$04,$06,$24,s9,0,0
|
|
D4,$04,$07,$04,d4,0,0
|
|
S10,$04,$06,$05,s10,0,0
|
|
S11,$04,$06,$25,s11,0,0
|
|
D5,$04,$07,$05,d5,0,0
|
|
S12,$04,$06,$06,s12,0,0
|
|
S13,$04,$06,$26,s13,0,0
|
|
D6,$04,$07,$06,d6,0,0
|
|
S14,$04,$06,$07,s14,0,0
|
|
S15,$04,$06,$27,s15,0,0
|
|
D7,$04,$07,$07,d7,0,0
|
|
S16,$04,$06,$08,s16,0,0
|
|
S17,$04,$06,$28,s17,0,0
|
|
D8,$04,$07,$08,d8,0,0
|
|
S18,$04,$06,$09,s18,0,0
|
|
S19,$04,$06,$29,s19,0,0
|
|
D9,$04,$07,$09,d9,0,0
|
|
S20,$04,$06,$0A,s20,0,0
|
|
S21,$04,$06,$2A,s21,0,0
|
|
D10,$04,$07,$0A,d10,0,0
|
|
S22,$04,$06,$0B,s22,0,0
|
|
S23,$04,$06,$2B,s23,0,0
|
|
D11,$04,$07,$0B,d11,0,0
|
|
S24,$04,$06,$0C,s24,0,0
|
|
S25,$04,$06,$2C,s25,0,0
|
|
D12,$04,$07,$0C,d12,0,0
|
|
S26,$04,$06,$0D,s26,0,0
|
|
S27,$04,$06,$2D,s27,0,0
|
|
D13,$04,$07,$0D,d13,0,0
|
|
S28,$04,$06,$0E,s28,0,0
|
|
S29,$04,$06,$2E,s29,0,0
|
|
D14,$04,$07,$0E,d14,0,0
|
|
S30,$04,$06,$0F,s30,0,0
|
|
S31,$04,$06,$2F,s21,0,0
|
|
D15,$04,$07,$0F,d15,0,0
|
|
D16,$04,$07,$10,d16,0,0
|
|
D17,$04,$07,$11,d17,0,0
|
|
D18,$04,$07,$12,d18,0,0
|
|
D19,$04,$07,$13,d19,0,0
|
|
D20,$04,$07,$14,d20,0,0
|
|
D21,$04,$07,$15,d21,0,0
|
|
D22,$04,$07,$16,d22,0,0
|
|
D23,$04,$07,$17,d23,0,0
|
|
D24,$04,$07,$18,d24,0,0
|
|
D25,$04,$07,$19,d25,0,0
|
|
D26,$04,$07,$1A,d26,0,0
|
|
D27,$04,$07,$1B,d27,0,0
|
|
D28,$04,$07,$1C,d28,0,0
|
|
D29,$04,$07,$1D,d29,0,0
|
|
D30,$04,$07,$1E,d30,0,0
|
|
D31,$04,$07,$1F,d31,0,0
|
|
|
|
; special registers
|
|
CPSR,$05,$00,$00,cpsr,0,0
|
|
FPSCR,$05,$00,$01,fpscr,0,0
|
|
SPSR,$05,$00,$02,spsr,0,0 |