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a) cpu64bitaddr, which means that we are generating a compiler which will generate code for targets with a 64 bit address space/abi b) cpu64bitalu, which means that we are generating a compiler which will generate code for a cpu with support for 64 bit integer operations (possibly running in a 32 bit address space, depending on the cpu64bitaddr define) All cpus which had cpu64bit set now have both the above defines set, and none of the 32 bit cpus have cpu64bitalu set (and none will compile with it currently) + pint and puint types, similar to aint/aword (not pword because that that conflicts with pword=^word) * several changes from aint/aword to pint/pword * some changes of tcgsize2size[OS_INT] to sizeof(pint) git-svn-id: trunk@10320 -
201 lines
6.4 KiB
ObjectPascal
201 lines
6.4 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the powerpc specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit rgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cgbase,cgutils,
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cpubase,
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rgobj;
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type
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trgcpu = class(trgobj)
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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end;
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trgintcpu = class(trgcpu)
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{$ifdef user0}
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procedure add_cpu_interferences(p : tai);override;
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{$endif user0}
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end;
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implementation
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uses
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verbose, cutils,
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cgobj,
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procinfo;
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procedure trgcpu.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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tmpref : treference;
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helplist : TAsmList;
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hreg : tregister;
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ins : Taicpu;
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begin
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if (spilltemp.offset<low(smallint)) or
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(spilltemp.offset>high(smallint)) then
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begin
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helplist:=TAsmList.create;
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if (spilltemp.index<>NR_NO) then
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internalerror(200704201);
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if getregtype(tempreg)=R_INTREGISTER then
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begin
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hreg:=getregisterinline(helplist,R_SUBWHOLE);
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{Done by add_cpu_interferences now.
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add_edge(getsupreg(hreg),RS_R0);}
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end
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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reference_reset(tmpref);
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tmpref.offset:=spilltemp.offset;
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tmpref.refaddr := addr_higha;
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ins:=taicpu.op_reg_reg_ref(A_ADDIS,hreg,spilltemp.base,tmpref);
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add_cpu_interferences(ins);
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helplist.concat(ins);
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tmpref:=spilltemp;
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tmpref.refaddr := addr_low;
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tmpref.base:=hreg;
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ins:=spilling_create_load(tmpref,tempreg);
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add_cpu_interferences(ins);
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helplist.concat(ins);
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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else
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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tmpref : treference;
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helplist : TAsmList;
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hreg : tregister;
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ins : Taicpu;
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begin
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if (spilltemp.offset<low(smallint)) or
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(spilltemp.offset>high(smallint)) then
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begin
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helplist:=TAsmList.create;
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if (spilltemp.index<>NR_NO) then
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internalerror(200704201);
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if getregtype(tempreg)=R_INTREGISTER then
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begin
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hreg:=getregisterinline(helplist,R_SUBWHOLE);
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{Done by add_cpu_interferences now.
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add_edge(getsupreg(hreg),RS_R0);}
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end
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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reference_reset(tmpref);
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tmpref.offset:=spilltemp.offset;
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tmpref.refaddr := addr_higha;
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ins:=taicpu.op_reg_reg_ref(A_ADDIS,hreg,spilltemp.base,tmpref);
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add_cpu_interferences(ins);
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helplist.concat(ins);
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tmpref:=spilltemp;
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tmpref.refaddr := addr_low;
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tmpref.base:=hreg;
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ins:=spilling_create_store(tempreg,tmpref);
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add_cpu_interferences(ins);
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helplist.concat(ins);
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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else
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inherited do_spill_written(list,pos,spilltemp,tempreg);
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end;
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{$ifdef user0}
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procedure trgintcpu.add_cpu_interferences(p : tai);
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var
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r : tregister;
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begin
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if p.typ=ait_instruction then
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begin
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case taicpu(p).opcode of
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A_ADDI, A_ADDIS,
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A_STB, A_LBZ, A_STBX, A_LBZX, A_STH, A_LHZ, A_STHX, A_LHZX, A_LHA, A_LHAX,
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A_STW, A_LWZ, A_STWX, A_LWZX,
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A_STFS, A_LFS, A_STFSX, A_LFSX, A_STFD, A_LFD, A_STFDX, A_LFDX, A_STFIWX,
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A_STHBRX, A_LHBRX, A_STWBRX, A_LWBRX, A_STWCX_, A_LWARX,
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A_ECIWX, A_ECOWX,
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A_LMW, A_STMW,A_LSWI,A_LSWX,A_STSWI,A_STSWX
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{$ifdef cpu64bitalu}
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, A_STD, A_STDX,
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A_LD, A_LDX,
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A_LWA, A_LWAX,
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A_STDCX_,A_LDARX
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{$endif cpu64bitalu}
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:
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begin
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case taicpu(p).oper[1]^.typ of
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top_reg:
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add_edge(getsupreg(taicpu(p).oper[1]^.reg),RS_R0);
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top_ref:
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if (taicpu(p).oper[1]^.ref^.base <> NR_NO) then
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),RS_R0);
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end;
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end;
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A_DCBA, A_DCBI, A_DCBST, A_DCBT, A_DCBTST, A_DCBZ, A_DCBF, A_ICBI:
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begin
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case taicpu(p).oper[0]^.typ of
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top_reg:
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add_edge(getsupreg(taicpu(p).oper[0]^.reg),RS_R0);
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top_ref:
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if (taicpu(p).oper[0]^.ref^.base <> NR_NO) then
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),RS_R0);
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end;
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end;
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end;
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end;
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end;
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{$endif user0}
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end.
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