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Clean up cpuinfo tables Fixed ARMv7M bug(BLX <label> doesn't exist on that version) git-svn-id: branches/laksen/arm-embedded@22579 -
212 lines
5.1 KiB
ObjectPascal
212 lines
5.1 KiB
ObjectPascal
{
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Copyright (c) 2008 by the Free Pascal development team
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Basic Processor information for the AVR
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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Unit CPUInfo;
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Interface
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uses
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globtype;
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Type
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bestreal = double;
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ts32real = single;
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ts64real = double;
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ts80real = type extended;
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ts128real = type extended;
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ts64comp = comp;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_avr1,
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cpu_avr2,
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cpu_avr25,
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cpu_avr3,
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cpu_avr31,
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cpu_avr35,
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cpu_avr4,
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cpu_avr5,
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cpu_avr51,
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cpu_avr6
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);
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tfputype =
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(fpu_none,
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fpu_soft,
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fp_libgcc
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);
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tcontrollertype =
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(ct_none,
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ct_atmega16,
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ct_atmega32,
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ct_atmega48,
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ct_atmega64,
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ct_atmega128
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);
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Const
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{# Size of native extended floating point type }
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extended_size = 12;
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{# Size of a multimedia register }
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mmreg_size = 16;
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{ target cpu string (used by compiler options) }
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target_cpu_string = 'avr';
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_safecall,
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pocall_stdcall,
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{ same as stdcall only different name mangling }
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pocall_cdecl,
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{ same as stdcall only different name mangling }
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pocall_cppdecl,
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{ same as stdcall but floating point numbers are handled like equal sized integers }
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pocall_softfloat
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];
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cputypestr : array[tcputype] of string[5] = ('',
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'AVR1',
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'AVR2',
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'AVR25',
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'AVR3',
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'AVR31',
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'AVR35',
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'AVR4',
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'AVR5',
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'AVR51',
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'AVR6'
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);
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fputypestr : array[tfputype] of string[6] = (
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'NONE',
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'SOFT',
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'LIBGCC'
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);
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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((
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controllertypestr:'';
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controllerunitstr:'';
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flashbase:0;
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flashsize:0;
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srambase:0;
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sramsize:0;
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eeprombase:0;
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eepromsize:0
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),
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(
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controllertypestr:'ATMEGA16';
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controllerunitstr:'ATMEGA16';
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flashbase:0;
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flashsize:$4000;
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srambase:0;
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sramsize:1024;
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eeprombase:0;
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eepromsize:512
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),
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(
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controllertypestr:'ATMEGA32';
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controllerunitstr:'ATMEGA32';
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flashbase:0;
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flashsize:$8000;
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srambase:0;
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sramsize:1024;
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eeprombase:0;
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eepromsize:512
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),
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(
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controllertypestr:'ATMEGA48';
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controllerunitstr:'ATMEGA48';
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flashbase:0;
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flashsize:$1000;
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srambase:0;
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sramsize:512;
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eeprombase:0;
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eepromsize:256;
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),
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(
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controllertypestr:'ATMEGA64';
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controllerunitstr:'ATMEGA64';
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flashbase:0;
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flashsize:$10000;
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srambase:0;
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sramsize:4096;
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eeprombase:0;
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eepromsize:2048;
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),
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(
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controllertypestr:'ATMEGA128';
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controllerunitstr:'ATMEGA128';
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flashbase:0;
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flashsize:$20000;
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srambase:0;
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sramsize:4096;
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eeprombase:0;
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eepromsize:4096;
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)
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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genericlevel3optimizerswitches-
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{ no need to write info about those }
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[cs_opt_level1,cs_opt_level2,cs_opt_level3]+
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[cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
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cs_opt_stackframe,cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
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[cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion];
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level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
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type
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tcpuflags =
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(CPUAVR_HAS_JMP_CALL,
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CPUAVR_HAS_MOVW,
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CPUAVR_HAS_LPMX,
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CPUAVR_HAS_MUL,
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CPUAVR_HAS_RAMPZ,
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CPUAVR_HAS_ELPM,
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CPUAVR_HAS_ELPMX,
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CPUAVR_2_BYTE_PC,
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CPUAVR_3_BYTE_PC
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags =
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( { cpu_none } [],
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{ cpu_avr1 } [],
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{ cpu_avr2 } [],
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{ cpu_avr25 } [],
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{ cpu_avr3 } [],
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{ cpu_avr31 } [],
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{ cpu_avr35 } [],
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{ cpu_avr4 } [],
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{ cpu_avr5 } [],
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{ cpu_avr51 } [],
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{ cpu_avr6 } []
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);
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Implementation
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end.
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