mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-11-04 16:39:24 +01:00
d1538ab023
+ RTL support:
o VFP exceptions are disabled by default on Darwin,
because they cause kernel panics on iPhoneOS 2.2.1 at least
o all denormals are truncated to 0 on Darwin, because disabling
that also causes kernel panics on iPhoneOS 2.2.1 (probably
because otherwise denormals can also cause exceptions)
* set softfloat rounding mode correctly for non-wince/darwin/vfp
targets
+ compiler support: only half the number of single precision
registers is available due to limitations of the register
allocator
+ added a number of comments about why the stackframe on ARM is
set up the way it is by the compiler
+ added regtype and subregtype info to regsets, because they're
also used for VFP registers (+ support in assembler reader)
+ various generic support routines for dealing with floating point
values located in integer registers that have to be transferred to
mm registers (needed for VFP)
* renamed use_sse() to use_vectorfpu() and also use it for
ARM/vfp support
o only superficially tested for Linux (compiler compiled with -Cpvfpv6
-Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
the fpu exception handler still needs to be implemented), Darwin has
been tested more thoroughly
+ added ARMv6 cpu type and made it default for Darwin/ARM
+ ARMv6+ implementations of atomic operations using ldrex/strex
* don't use r9 on Darwin/ARM, as it's reserved under certain
circumstances (don't know yet which ones)
* changed C-test object files for ARM/Darwin to ARMv6 versions
* check in assembler reader that regsets are not empty, because
instructions with a regset operand have undefined behaviour in that
case
* fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
int64->single type conversion
* fixed constant pool locations in case 64 bit constants are generated,
and/or when vfp instructions with limited reach are present
WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
code with -Cparmv6 (or higher), or you will get crashes. The reason is
that storing/restoring multiple VFP registers must happen using
different instructions on pre/post-ARMv6.
git-svn-id: trunk@14317 -
338 lines
10 KiB
ObjectPascal
338 lines
10 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generates ARM inline nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narminl;
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{$i fpcdefs.inc}
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interface
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uses
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node,ninl,ncginl;
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type
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tarminlinenode = class(tcgInlineNode)
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function first_abs_real: tnode; override;
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function first_sqr_real: tnode; override;
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function first_sqrt_real: tnode; override;
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{ atn,sin,cos,lgn isn't supported by the linux fpe
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function first_arctan_real: tnode; override;
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function first_ln_real: tnode; override;
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function first_cos_real: tnode; override;
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function first_sin_real: tnode; override;
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}
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procedure second_abs_real; override;
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procedure second_sqr_real; override;
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procedure second_sqrt_real; override;
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{ atn,sin,cos,lgn isn't supported by the linux fpe
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procedure second_arctan_real; override;
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procedure second_ln_real; override;
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procedure second_cos_real; override;
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procedure second_sin_real; override;
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}
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procedure second_prefetch; override;
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private
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procedure load_fpu_location(out singleprec: boolean);
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,fmodule,
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cpuinfo,
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symconst,symdef,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cgbase,cgutils,
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pass_1,pass_2,
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cpubase,paramgr,
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nbas,ncon,ncal,ncnv,nld,
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tgobj,ncgutil,cgobj,cg64f32,rgobj,rgcpu,cgcpu;
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{*****************************************************************************
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tarminlinenode
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*****************************************************************************}
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procedure tarminlinenode.load_fpu_location(out singleprec: boolean);
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begin
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secondpass(left);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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location_force_fpureg(current_asmdata.CurrAsmList,left.location,true);
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location_copy(location,left.location);
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if left.location.loc=LOC_CFPUREGISTER then
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begin
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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location.loc := LOC_FPUREGISTER;
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end;
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end;
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fpu_vfpv2,
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fpu_vfpv3:
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begin
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location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,true);
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location_copy(location,left.location);
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if left.location.loc=LOC_CMMREGISTER then
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begin
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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location.loc := LOC_MMREGISTER;
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end;
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end;
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else
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internalerror(2009111801);
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end;
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singleprec:=tfloatdef(left.resultdef).floattype=s32real;
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end;
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function tarminlinenode.first_abs_real : tnode;
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begin
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if (cs_fp_emulation in current_settings.moduleswitches) then
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result:=inherited first_abs_real
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else
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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expectloc:=LOC_FPUREGISTER;
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fpu_vfpv2,
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fpu_vfpv3:
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expectloc:=LOC_MMREGISTER;
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else
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internalerror(2009112401);
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end;
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first_abs_real:=nil;
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end;
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end;
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function tarminlinenode.first_sqr_real : tnode;
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begin
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if (cs_fp_emulation in current_settings.moduleswitches) then
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result:=inherited first_sqr_real
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else
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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expectloc:=LOC_FPUREGISTER;
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fpu_vfpv2,
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fpu_vfpv3:
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expectloc:=LOC_MMREGISTER;
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else
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internalerror(2009112402);
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end;
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first_sqr_real:=nil;
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end;
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end;
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function tarminlinenode.first_sqrt_real : tnode;
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begin
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if cs_fp_emulation in current_settings.moduleswitches then
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result:=inherited first_sqrt_real
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else
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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expectloc:=LOC_FPUREGISTER;
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fpu_vfpv2,
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fpu_vfpv3:
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expectloc:=LOC_MMREGISTER;
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else
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internalerror(2009112403);
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end;
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first_sqrt_real := nil;
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end;
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end;
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{ atn,sin,cos,lgn isn't supported by the linux fpe
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function tarminlinenode.first_arctan_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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function tarminlinenode.first_ln_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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function tarminlinenode.first_cos_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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function tarminlinenode.first_sin_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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}
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procedure tarminlinenode.second_abs_real;
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var
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singleprec: boolean;
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op: TAsmOp;
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begin
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load_fpu_location(singleprec);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_ABS,location.register,left.location.register),get_fpu_postfix(resultdef)));
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fpu_vfpv2,
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fpu_vfpv3:
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begin
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if singleprec then
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op:=A_FABSS
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else
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op:=A_FABSD;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,location.register,left.location.register));
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end;
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else
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internalerror(2009111402);
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end;
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end;
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procedure tarminlinenode.second_sqr_real;
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var
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singleprec: boolean;
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op: TAsmOp;
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begin
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load_fpu_location(singleprec);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_MUF,location.register,left.location.register,left.location.register),get_fpu_postfix(resultdef)));
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fpu_vfpv2,
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fpu_vfpv3:
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begin
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if singleprec then
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op:=A_FMULS
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else
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op:=A_FMULD;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,left.location.register));
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end;
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else
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internalerror(2009111403);
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end;
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end;
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procedure tarminlinenode.second_sqrt_real;
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var
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singleprec: boolean;
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op: TAsmOp;
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begin
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load_fpu_location(singleprec);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_SQT,location.register,left.location.register),get_fpu_postfix(resultdef)));
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fpu_vfpv2,
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fpu_vfpv3:
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begin
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if singleprec then
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op:=A_FSQRTS
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else
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op:=A_FSQRTD;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,location.register,left.location.register));
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end;
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else
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internalerror(2009111402);
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end;
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end;
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{ atn, sin, cos, lgn isn't supported by the linux fpe
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procedure tarminlinenode.second_arctan_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_ATN,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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procedure tarminlinenode.second_ln_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_LGN,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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procedure tarminlinenode.second_cos_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_COS,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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procedure tarminlinenode.second_sin_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_SIN,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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}
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procedure tarminlinenode.second_prefetch;
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var
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ref : treference;
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r : tregister;
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begin
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if current_settings.cputype>=cpu_armv5 then
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begin
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secondpass(left);
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case left.location.loc of
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LOC_CREFERENCE,
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LOC_REFERENCE:
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begin
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r:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,left.location.reference,r);
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reference_reset_base(ref,r,0,left.location.reference.alignment);
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{ since the address might be nil we can't use ldr for older cpus }
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_PLD,ref));
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end;
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else
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internalerror(200402021);
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end;
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end;
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end;
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begin
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cinlinenode:=tarminlinenode;
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end.
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