mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-27 02:43:41 +02:00
497 lines
21 KiB
ObjectPascal
497 lines
21 KiB
ObjectPascal
unit ATtiny828;
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interface
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var
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// SPI
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SPDR : byte absolute $00+$4E; // SPI Data Register
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SPSR : byte absolute $00+$4D; // SPI Status Register
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SPCR : byte absolute $00+$4C; // SPI Control Register
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// PORTA
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PUEA : byte absolute $00+$23; // Pull-up Enable Control Register
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PORTA : byte absolute $00+$22; // Port A Data Register
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DDRA : byte absolute $00+$21; // Data Direction Register, Port A
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PINA : byte absolute $00+$20; // Port A Input Pins
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// PORTB
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PUEB : byte absolute $00+$27; // Pull-up Enable Control Register
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PORTB : byte absolute $00+$26; // Port B Data Register
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DDRB : byte absolute $00+$25; // Data Direction Register, Port B
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PINB : byte absolute $00+$24; // Port B Input Pins
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// PORTC
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PHDE : byte absolute $00+$34; // Port High Drive Enable Register
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PUEC : byte absolute $00+$2B; // Pull-up Enable Control Register
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PORTC : byte absolute $00+$2A; // Port C Data Register
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DDRC : byte absolute $00+$29; // Data Direction Register, Port C
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PINC : byte absolute $00+$28; // Port C Input Pins
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// PORTD
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PUED : byte absolute $00+$2F; // Pull-up Enable Control Register
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PORTD : byte absolute $00+$2E; // Port D Data Register
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DDRD : byte absolute $00+$2D; // Data Direction Register, Port D
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PIND : byte absolute $00+$2C; // Port D Input Pins
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// CPU
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PRR : byte absolute $00+$64; // Power Reduction Register
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CCP : byte absolute $00+$56; // Configuration Change Protection
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OSCCAL0 : byte absolute $00+$66; // Oscillator Calibration Value
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OSCCAL1 : byte absolute $00+$67; //
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OSCTCAL0A : byte absolute $00+$F0; //
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OSCTCAL0B : byte absolute $00+$F1; //
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CLKPR : byte absolute $00+$61; // Clock Prescale Register
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status Register
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GPIOR2 : byte absolute $00+$4B; // General Purpose I/O Register 2
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GPIOR1 : byte absolute $00+$4A; // General Purpose I/O Register 1
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GPIOR0 : byte absolute $00+$3E; // General Purpose I/O Register 0
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SMCR : byte absolute $00+$53; // Sleep Mode Control Register
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control and Status Register
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// TIMER_COUNTER_0
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OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register
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OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register
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TCNT0 : byte absolute $00+$46; // Timer/Counter0
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TCCR0B : byte absolute $00+$45; // Timer/Counter Control Register B
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TCCR0A : byte absolute $00+$44; // Timer/Counter Control Register A
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TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register
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TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register
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GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register
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// TIMER_COUNTER_1
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TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register
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TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register
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TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C
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TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes
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OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes
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OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register Bytes
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OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes
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OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes
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OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register Bytes
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ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes
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// TOCPM
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TOCPMSA1 : byte absolute $00+$E9; // Timer Output Compare Pin Mux Selection 1
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TOCPMSA0 : byte absolute $00+$E8; // Timer Output Compare Pin Mux Selection 0
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TOCPMCOE : byte absolute $00+$E2; // Timer Output Compare Pin Mux Channel Output Enable
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// AD_CONVERTER
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ADMUXA : byte absolute $00+$7C; // The ADC multiplexer Selection Register A
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ADMUXB : byte absolute $00+$7D; // The ADC multiplexer Selection Register B
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ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register
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ADC : word absolute $00+$78; // ADC Data Register Bytes
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ADCL : byte absolute $00+$78; // ADC Data Register Bytes
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ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
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DIDR3 : byte absolute $00+$DF; // Digital Input Disable Register 2
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DIDR2 : byte absolute $00+$DE; // Digital Input Disable Register 2
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DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 1
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DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
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// ANALOG_COMPARATOR
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ACSRB : byte absolute $00+$4F; // Analog Comparator Control And Status Register B
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ACSRA : byte absolute $00+$50; // Analog Comparator Control And Status Register A
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$69; // External Interrupt Control Register
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EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register
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EIFR : byte absolute $00+$3C; // External Interrupt Flag Register
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PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register
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PCMSK3 : byte absolute $00+$73; // Pin Change Mask Register 3
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PCMSK2 : byte absolute $00+$6D; // Pin Change Mask Register 2
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PCMSK1 : byte absolute $00+$6C; // Pin Change Mask Register 1
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PCMSK0 : byte absolute $00+$6B; // Pin Change Mask Register 0
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PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register
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// WATCHDOG
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WDTCSR : byte absolute $00+$60; // Watchdog Timer Control and Status Register
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// EEPROM
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EEAR : byte absolute $00+$41; // EEPROM Read/Write Access
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EEDR : byte absolute $00+$40; // EEPROM Data Register
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EECR : byte absolute $00+$3F; // EEPROM Control Register
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// TWI
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TWSCRA : byte absolute $00+$B8; // TWI Slave Control Register A
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TWSCRB : byte absolute $00+$B9; // TWI Slave Control Register B
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TWSSRA : byte absolute $00+$BA; // TWI Slave Status Register A
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TWSA : byte absolute $00+$BC; // TWI Slave Address Register
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TWSD : byte absolute $00+$BD; // TWI Slave Data Register
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TWSAM : byte absolute $00+$BB; // TWI Slave Address Mask Register
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// USART
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UDR : byte absolute $00+$C6; // USART I/O Data Register
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UCSRA : byte absolute $00+$C0; // USART Control and Status Register A
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UCSRB : byte absolute $00+$C1; // USART Control and Status Register B
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UCSRC : byte absolute $00+$C2; // USART Control and Status Register C
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UCSRD : byte absolute $00+$C3; // USART Control and Status Register D
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UBRR : word absolute $00+$C4; // USART Baud Rate Register Bytes
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UBRRL : byte absolute $00+$C4; // USART Baud Rate Register Bytes
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UBRRH : byte absolute $00+$C4+1; // USART Baud Rate Register Bytes
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const
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// PHDE
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PHDEC = 2; // Port C High Drive Enable
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// PRR
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PRTWI = 7; // Power Reduction TWI
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PRTIM0 = 5; // Power Reduction Timer/Counter0
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PRTIM1 = 3; // Power Reduction Timer/Counter1
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PRSPI = 2; // Power Reduction SPI
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PRUSART0 = 1; // Power Reduction USART 0
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PRADC = 0; // Power Reduction ADC
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// CLKPR
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CLKPS = 0; // Clock Prescaler Select Bits
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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IVSEL = 1; // Interrupt Vector Select
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// SMCR
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SM = 1; // Sleep Mode Select Bits
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SE = 0; // Sleep Enable
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// SPMCSR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read-While-Write Section Busy
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RSIG = 5; // Read Device Signature Imprint Table
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RWWSRE = 4; // Read-While-Write section read enable
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RWFLB = 3; // Read/Write Fuse and Lock Bits
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// TCCR0B
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FOC0A = 7; // Force Output Compare A
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FOC0B = 6; // Force Output Compare B
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WGM02 = 3; //
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CS0 = 0; // Clock Select
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// TCCR0A
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COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
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COM0B = 4; // Compare Output Mode, Fast PWm
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WGM0 = 0; // Waveform Generation Mode
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// TIMSK0
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OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable
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OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B
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OCF0A = 1; // Timer/Counter0 Output Compare Flag 0A
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
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// TIMSK1
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ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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OCIE1B = 2; // Timer/Counter1 Output CompareB Match Interrupt Enable
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OCIE1A = 1; // Timer/Counter1 Output CompareA Match Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 5; // Input Capture Flag 1
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OCF1B = 2; // Output Compare Flag 1B
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OCF1A = 1; // Output Compare Flag 1A
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Waveform Generation Mode
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Prescaler source of Timer/Counter 1
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// TCCR1C
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FOC1A = 7; //
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FOC1B = 6; //
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// GTCCR
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// TOCPMSA1
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TOCC7S = 6; // Timer Output Compare Channel 7 Selection Bits
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TOCC6S = 4; // Timer Output Compare Channel 6 Selection Bits
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TOCC5S = 2; // Timer Output Compare Channel 5 Selection Bits
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TOCC4S = 0; // Timer Output Compare Channel 4 Selection Bits
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// TOCPMSA0
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TOCC3S = 6; // Timer Output Compare Channel 3 Selection Bits
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TOCC2S = 4; // Timer Output Compare Channel 2 Selection Bits
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TOCC1S = 2; // Timer Output Compare Channel 1 Selection Bits
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TOCC0S = 0; // Timer Output Compare Channel 0 Selection Bits
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// TOCPMCOE
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TOCC7OE = 7; // Timer Output Compare Channel 7 Output Enable
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TOCC6OE = 6; // Timer Output Compare Channel 6 Output Enable
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TOCC5OE = 5; // Timer Output Compare Channel 5 Output Enable
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TOCC4OE = 4; // Timer Output Compare Channel 4 Output Enable
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TOCC3OE = 3; // Timer Output Compare Channel 3 Output Enable
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TOCC2OE = 2; // Timer Output Compare Channel 2 Output Enable
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TOCC1OE = 1; // Timer Output Compare Channel 1 Output Enable
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TOCC0OE = 0; // Timer Output Compare Channel 0 Output Enable
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// ADMUXA
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MUX = 0; // Analog Channel Selection Bits 4:0
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// ADMUXB
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REFS = 5; // Reference Selection Bit
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MUX5 = 0; // Analog Channel Selection Bit 5
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADLAR = 3; //
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR3
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ADC27D = 3; // ADC27 Digital input Disable
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ADC26D = 2; // ADC26 Digital input Disable
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ADC25D = 1; // ADC25 Digital input Disable
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ADC24D = 0; // ADC24 Digital input Disable
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// DIDR2
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ADC23D = 7; // ADC23 Digital input Disable
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ADC22D = 6; // ADC22 Digital input Disable
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ADC21D = 5; // ADC21 Digital input Disable
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ADC20D = 4; // ADC20 Digital input Disable
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ADC19D = 3; // ADC19 Digital input Disable
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ADC18D = 2; // ADC18 Digital input Disable
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ADC17D = 1; // ADC17 Digital input Disable
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ADC16D = 0; // ADC16 Digital input Disable
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// DIDR1
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ADC15D = 7; // ADC15 Digital input Disable
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ADC14D = 6; // ADC14 Digital input Disable
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ADC13D = 5; // ADC13 Digital input Disable
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ADC12D = 4; // ADC12 Digital input Disable
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ADC11D = 3; // ADC11 Digital input Disable
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ADC10D = 2; // ADC10 Digital input Disable
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ADC9D = 1; // ADC9 Digital input Disable
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ADC8D = 0; // ADC8 Digital input Disable
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// DIDR0
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ADC7D = 7; // ADC7 Digital input Disable
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ADC6D = 6; // ADC6 Digital input Disable
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ADC5D = 5; // ADC5 Digital input Disable
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ADC4D = 4; // ADC4 Digital input Disable
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ADC3D = 3; // ADC3 Digital input Disable
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ADC2D = 2; // ADC2 Digital input Disable
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ADC1D = 1; // ADC1 Digital input Disable
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ADC0D = 0; // ADC0 Digital input Disable
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// ACSRB
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HSEL = 7; // Hysteresis Select
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HLEV = 6; // Hysteresis Level
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ACNMUX = 2; // Analog Comparator Negative Input Multiplexer
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ACPMUX = 0; // Analog Comparator Positive Input Multiplexer Bits 1:0
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// ACSRA
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ACD = 7; // Analog Comparator Disable
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ACPMUX2 = 6; // Analog Comparator Positive Input Multiplexer Bit 2
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// EICRA
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ISC1 = 2; // External Interrupt Sense Control 1 Bits
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ISC0 = 0; // External Interrupt Sense Control 0 Bits
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// EIMSK
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INT = 0; // External Interrupt Request Enables
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// EIFR
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INTF = 0; // External Interrupt Flags
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// PCICR
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PCIE = 0; // Pin Change Interrupt Enables
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// PCMSK3
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PCINT = 0; // Pin Change Enable Masks
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// PCMSK2
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// PCMSK1
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// PCMSK0
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// PCIFR
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PCIF = 0; // Pin Change Interrupt Flags
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// WDTCSR
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WDIF = 7; // Watchdog Timer Interrupt Flag
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WDIE = 6; // Watchdog Timer Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDE = 3; // Watch Dog Enable
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// EECR
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EEPM = 4; // EEPROM Programming Mode Bits
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EERIE = 3; // EEProm Ready Interrupt Enable
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EEMPE = 2; // EEPROM Master Write Enable
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EEPE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// TWSCRA
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TWSHE = 7; // TWI SDA Hold Time Enable
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TWDIE = 5; // TWI Data Interrupt Enable
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TWASIE = 4; // TWI Address/Stop Interrupt Enable
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TWEN = 3; // Two-Wire Interface Enable
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TWSIE = 2; // TWI Stop Interrupt Enable
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TWPME = 1; // TWI Promiscuous Mode Enable
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TWSME = 0; // TWI Smart Mode Enable
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// TWSCRB
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TWHNM = 3; // TWI High Noise Mode
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TWAA = 2; // TWI Acknowledge Action
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TWCMD = 0; //
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// TWSSRA
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TWDIF = 7; // TWI Data Interrupt Flag.
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TWASIF = 6; // TWI Address/Stop Interrupt Flag
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TWCH = 5; // TWI Clock Hold
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TWRA = 4; // TWI Receive Acknowledge
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TWC = 3; // TWI Collision
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TWBE = 2; // TWI Bus Error
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TWDIR = 1; // TWI Read/Write Direction
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TWAS = 0; // TWI Address or Stop
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// TWSD
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// TWSAM
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TWAE = 0; // TWI Address Enable
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// UCSRA
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RXC = 7; // USART Receive Complete
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TXC = 6; // USART Transmitt Complete
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UDRE = 5; // USART Data Register Empty
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FE = 4; // Framing Error
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DOR = 3; // Data overRun
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UPE = 2; // Parity Error
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U2X = 1; // Double the USART transmission speed
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MPCM = 0; // Multi-processor Communication Mode
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// UCSRB
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RXCIE = 7; // RX Complete Interrupt Enable
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TXCIE = 6; // TX Complete Interrupt Enable
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UDRIE = 5; // USART Data register Empty Interrupt Enable
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RXEN = 4; // Receiver Enable
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TXEN = 3; // Transmitter Enable
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UCSZ2 = 2; // Character Size
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RXB8 = 1; // Receive Data Bit 8
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TXB8 = 0; // Transmit Data Bit 8
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// UCSRC
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UMSEL = 6; // USART Mode Select
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UPM = 4; // Parity Mode Bits
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USBS = 3; // Stop Bit Select
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UCSZ = 1; // Character Size
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UCPOL = 0; // Clock Polarity
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// UCSRD
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RXSIE = 7; // USART RX Start Interrupt Enable
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RXS = 6; // USART RX Start Flag
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SFDE = 5; // USART RX Start Frame Detection Enable
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 3 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 4 Pin Change Interrupt Request 1
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procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 5 Pin Change Interrupt Request 2
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procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 6 Pin Change Interrupt Request 3
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 7 Watchdog Time-out Interrupt
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 8 Timer/Counter1 Capture Event
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 9 Timer/Counter1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 10 Timer/Counter1 Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 11 Timer/Counter1 Overflow
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 12 Timer/Counter0 Compare Match A
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 13 Timer/Counter0 Compare Match B
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 14 Timer/Counter0 Overflow
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procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 15 SPI Serial Transfer Complete
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procedure USART__START_ISR; external name 'USART__START_ISR'; // Interrupt 16 USART, Start
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procedure USART__RX_ISR; external name 'USART__RX_ISR'; // Interrupt 17 USART Rx Complete
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procedure USART__UDRE_ISR; external name 'USART__UDRE_ISR'; // Interrupt 18 USART, Data Register Empty
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procedure USART__TX_ISR; external name 'USART__TX_ISR'; // Interrupt 19 USART Tx Complete
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 20 ADC Conversion Complete
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 21 EEPROM Ready
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procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 22 Analog Comparator
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procedure TWI_SLAVE_ISR; external name 'TWI_SLAVE_ISR'; // Interrupt 23 Two-wire Serial Interface
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procedure SPM_Ready_ISR; external name 'SPM_Ready_ISR'; // Interrupt 24 Store Program Memory Read
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procedure QTRIP_ISR; external name 'QTRIP_ISR'; // Interrupt 25 Touch Sensing
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp PCINT2_ISR
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rjmp PCINT3_ISR
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rjmp WDT_ISR
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rjmp TIMER1_CAPT_ISR
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rjmp TIMER1_COMPA_ISR
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rjmp TIMER1_COMPB_ISR
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rjmp TIMER1_OVF_ISR
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rjmp TIMER0_COMPA_ISR
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rjmp TIMER0_COMPB_ISR
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rjmp TIMER0_OVF_ISR
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rjmp SPI__STC_ISR
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rjmp USART__START_ISR
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rjmp USART__RX_ISR
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rjmp USART__UDRE_ISR
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rjmp USART__TX_ISR
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rjmp ADC_ISR
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rjmp EE_READY_ISR
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rjmp ANALOG_COMP_ISR
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rjmp TWI_SLAVE_ISR
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rjmp SPM_Ready_ISR
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rjmp QTRIP_ISR
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.weak INT0_ISR
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.weak INT1_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak PCINT2_ISR
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.weak PCINT3_ISR
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.weak WDT_ISR
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.weak TIMER1_CAPT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak TIMER0_OVF_ISR
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.weak SPI__STC_ISR
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.weak USART__START_ISR
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.weak USART__RX_ISR
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.weak USART__UDRE_ISR
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.weak USART__TX_ISR
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.weak ADC_ISR
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.weak EE_READY_ISR
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.weak ANALOG_COMP_ISR
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.weak TWI_SLAVE_ISR
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.weak SPM_Ready_ISR
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.weak QTRIP_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set PCINT2_ISR, Default_IRQ_handler
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.set PCINT3_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set TIMER1_CAPT_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set SPI__STC_ISR, Default_IRQ_handler
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.set USART__START_ISR, Default_IRQ_handler
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.set USART__RX_ISR, Default_IRQ_handler
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.set USART__UDRE_ISR, Default_IRQ_handler
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.set USART__TX_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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.set EE_READY_ISR, Default_IRQ_handler
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.set ANALOG_COMP_ISR, Default_IRQ_handler
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.set TWI_SLAVE_ISR, Default_IRQ_handler
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.set SPM_Ready_ISR, Default_IRQ_handler
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.set QTRIP_ISR, Default_IRQ_handler
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end;
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end.
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