mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-05-02 18:34:00 +02:00
9e5979e8be
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax. Updated VFP code in RTL to use UAL syntax too. Added preliminary ELF support for ARM. Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target. git-svn-id: branches/laksen/armiw@29247 -
404 lines
13 KiB
ObjectPascal
404 lines
13 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generates ARM inline nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narminl;
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{$i fpcdefs.inc}
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interface
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uses
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node,ninl,ncginl;
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type
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tarminlinenode = class(tcgInlineNode)
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function first_abs_real: tnode; override;
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function first_sqr_real: tnode; override;
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function first_sqrt_real: tnode; override;
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{ atn,sin,cos,lgn isn't supported by the linux fpe
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function first_arctan_real: tnode; override;
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function first_ln_real: tnode; override;
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function first_cos_real: tnode; override;
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function first_sin_real: tnode; override;
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}
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procedure second_abs_real; override;
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procedure second_sqr_real; override;
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procedure second_sqrt_real; override;
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{ atn,sin,cos,lgn isn't supported by the linux fpe
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procedure second_arctan_real; override;
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procedure second_ln_real; override;
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procedure second_cos_real; override;
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procedure second_sin_real; override;
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}
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procedure second_prefetch; override;
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procedure second_abs_long; override;
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private
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procedure load_fpu_location(out singleprec: boolean);
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end;
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implementation
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uses
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globtype,verbose,globals,
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cpuinfo, defutil,symdef,aasmdata,aasmcpu,
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cgbase,cgutils,pass_1,pass_2,
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cpubase,ncgutil,cgobj,cgcpu, hlcgobj;
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{*****************************************************************************
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tarminlinenode
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*****************************************************************************}
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procedure tarminlinenode.load_fpu_location(out singleprec: boolean);
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begin
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secondpass(left);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location_copy(location,left.location);
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if left.location.loc=LOC_CFPUREGISTER then
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begin
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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location.loc := LOC_FPUREGISTER;
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end;
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end;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16,
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fpu_fpv4_s16:
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begin
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location_copy(location,left.location);
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if left.location.loc=LOC_CMMREGISTER then
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begin
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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location.loc := LOC_MMREGISTER;
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end;
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end;
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fpu_soft:
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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location_copy(location,left.location);
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end
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else
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internalerror(2009111801);
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end;
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singleprec:=tfloatdef(left.resultdef).floattype=s32real;
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end;
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function tarminlinenode.first_abs_real : tnode;
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begin
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if (cs_fp_emulation in current_settings.moduleswitches) then
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begin
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firstpass(left);
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expectloc:=LOC_REGISTER;
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first_abs_real:=nil;
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end
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else
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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expectloc:=LOC_FPUREGISTER;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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expectloc:=LOC_MMREGISTER;
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fpu_fpv4_s16:
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begin
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if tfloatdef(left.resultdef).floattype=s32real then
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expectloc:=LOC_MMREGISTER
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else
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exit(inherited first_abs_real);
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end;
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else
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internalerror(2009112401);
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end;
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first_abs_real:=nil;
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end;
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end;
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function tarminlinenode.first_sqr_real : tnode;
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begin
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if (cs_fp_emulation in current_settings.moduleswitches) then
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result:=inherited first_sqr_real
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else
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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expectloc:=LOC_FPUREGISTER;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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expectloc:=LOC_MMREGISTER;
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fpu_fpv4_s16:
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begin
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if tfloatdef(left.resultdef).floattype=s32real then
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expectloc:=LOC_MMREGISTER
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else
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exit(inherited first_sqr_real);
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end;
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else
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internalerror(2009112402);
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end;
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first_sqr_real:=nil;
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end;
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end;
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function tarminlinenode.first_sqrt_real : tnode;
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begin
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if cs_fp_emulation in current_settings.moduleswitches then
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result:=inherited first_sqrt_real
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else
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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expectloc:=LOC_FPUREGISTER;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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expectloc:=LOC_MMREGISTER;
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fpu_fpv4_s16:
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begin
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if tfloatdef(left.resultdef).floattype=s32real then
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expectloc:=LOC_MMREGISTER
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else
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exit(inherited first_sqrt_real);
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end;
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else
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internalerror(2009112403);
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end;
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first_sqrt_real := nil;
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end;
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end;
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{ atn,sin,cos,lgn isn't supported by the linux fpe
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function tarminlinenode.first_arctan_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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function tarminlinenode.first_ln_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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function tarminlinenode.first_cos_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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function tarminlinenode.first_sin_real: tnode;
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begin
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expectloc:=LOC_FPUREGISTER;
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result:=nil;
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end;
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}
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procedure tarminlinenode.second_abs_real;
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var
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singleprec: boolean;
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pf: TOpPostfix;
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begin
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load_fpu_location(singleprec);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_ABS,location.register,left.location.register),get_fpu_postfix(resultdef)));
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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begin
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if singleprec then
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pf:=PF_F32
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register),pf));
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end;
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fpu_fpv4_s16:
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current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg(A_VABS,location.register,left.location.register), PF_F32));
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fpu_soft:
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begin
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if singleprec then
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,OS_32,tcgint($7fffffff),location.register)
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else
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,OS_32,tcgint($7fffffff),location.registerhi);
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end
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else
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internalerror(2009111402);
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end;
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end;
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procedure tarminlinenode.second_sqr_real;
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var
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singleprec: boolean;
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pf: TOpPostfix;
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begin
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load_fpu_location(singleprec);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_MUF,location.register,left.location.register,left.location.register),get_fpu_postfix(resultdef)));
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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begin
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if singleprec then
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pf:=PF_F32
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register),pf));
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end;
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fpu_fpv4_s16:
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current_asmdata.CurrAsmList.Concat(setoppostfix(taicpu.op_reg_reg_reg(A_VMUL,location.register,left.location.register,left.location.register), PF_F32));
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else
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internalerror(2009111403);
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end;
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end;
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procedure tarminlinenode.second_sqrt_real;
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var
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singleprec: boolean;
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op: TAsmOp;
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begin
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load_fpu_location(singleprec);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_SQT,location.register,left.location.register),get_fpu_postfix(resultdef)));
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16,
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fpu_fpv4_s16:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VSQRT,location.register,left.location.register));
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else
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internalerror(2009111402);
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end;
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end;
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{ atn, sin, cos, lgn isn't supported by the linux fpe
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procedure tarminlinenode.second_arctan_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_ATN,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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procedure tarminlinenode.second_ln_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_LGN,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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procedure tarminlinenode.second_cos_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_COS,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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procedure tarminlinenode.second_sin_real;
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begin
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load_fpu_location;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_SIN,location.register,left.location.register),get_fpu_postfix(resultdef)));
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end;
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}
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procedure tarminlinenode.second_prefetch;
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var
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ref : treference;
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r : tregister;
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begin
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if not(GenerateThumbCode) and (CPUARM_HAS_EDSP in cpu_capabilities[current_settings.cputype]) then
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begin
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secondpass(left);
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case left.location.loc of
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LOC_CREFERENCE,
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LOC_REFERENCE:
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begin
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r:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,left.location.reference,r);
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reference_reset_base(ref,r,0,left.location.reference.alignment);
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{ since the address might be nil we can't use ldr for older cpus }
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current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_PLD,ref));
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end;
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else
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internalerror(200402021);
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end;
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end;
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end;
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procedure tarminlinenode.second_abs_long;
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var
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opsize : tcgsize;
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hp : taicpu;
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begin
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if GenerateThumbCode then
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begin
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inherited second_abs_long;
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exit;
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end;
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secondpass(left);
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opsize:=def_cgsize(left.resultdef);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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location:=left.location;
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MOV,location.register,left.location.register), PF_S));
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if GenerateThumb2Code then
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current_asmdata.CurrAsmList.concat(taicpu.op_cond(A_IT,C_MI));
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current_asmdata.CurrAsmList.concat(setcondition(taicpu.op_reg_reg_const(A_RSB,location.register,location.register, 0), C_MI));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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end;
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begin
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cinlinenode:=tarminlinenode;
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end.
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