mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 12:11:34 +01:00
d6bcb83f95
* detection whether edi is used after instructions (since regalloc
info for it is now available)
* better regUsedAfterInstruction function
1869 lines
91 KiB
ObjectPascal
1869 lines
91 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2000 by Florian Klaempfl and Jonas Maebe
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This unit contains the peephole optimizer.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit POpt386;
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{$ifdef newOptimizations}
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{$define foropt}
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{$define replacereg}
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{$define arithopt}
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{$define foldarithops}
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{$endif newOptimizations}
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Interface
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Uses Aasm;
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Procedure PeepHoleOptPass1(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
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Implementation
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Uses
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globtype,systems,
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globals,verbose,hcodegen,
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{$ifdef finaldestdebug}
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cobjects,
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{$endif finaldestdebug}
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cpubase,cpuasm,DAOpt386;
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Function RegUsedAfterInstruction(Reg: TRegister; p: Pai; Var UsedRegs: TRegSet): Boolean;
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Begin
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UpdateUsedRegs(UsedRegs, Pai(p^.Next));
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RegUsedAfterInstruction :=
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(Reg in UsedRegs) and
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(not(getNextInstruction(p,p)) or
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not(regLoadedWithNewValue(reg,false,p)));
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End;
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Procedure PeepHoleOptPass1(Asml: PAasmOutput; BlockStart, BlockEnd: Pai);
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{First pass of peepholeoptimizations}
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Var
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l : longint;
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p ,hp1, hp2 : pai;
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{$ifdef foropt}
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hp3, hp4: pai;
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{$endif foropt}
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TmpBool1, TmpBool2: Boolean;
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TmpRef: TReference;
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UsedRegs, TmpUsedRegs: TRegSet;
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Function SkipLabels(hp: Pai; var hp2: pai): boolean;
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{skips all labels and returns the next "real" instruction}
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Begin
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While assigned(hp^.next) and
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(pai(hp^.next)^.typ In SkipInstr + [ait_label,ait_align]) Do
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hp := pai(hp^.next);
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If assigned(hp^.next) Then
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Begin
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SkipLabels := True;
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hp2 := pai(hp^.next)
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End
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Else
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Begin
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hp2 := hp;
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SkipLabels := False
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End;
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End;
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Procedure GetFinalDestination(AsmL: PAAsmOutput; hp: paicpu);
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{traces sucessive jumps to their final destination and sets it, e.g.
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je l1 je l3
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<code> <code>
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l1: becomes l1:
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je l2 je l3
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<code> <code>
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l2: l2:
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jmp l3 jmp l3}
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Var p1, p2: pai;
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l: pasmlabel;
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Function FindAnyLabel(hp: pai; var l: pasmlabel): Boolean;
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Begin
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FindAnyLabel := false;
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While assigned(hp^.next) and
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(pai(hp^.next)^.typ In (SkipInstr+[ait_align])) Do
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hp := pai(hp^.next);
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If assigned(hp^.next) and
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(pai(hp^.next)^.typ = ait_label) Then
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Begin
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FindAnyLabel := true;
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l := pai_label(hp^.next)^.l;
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End
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End;
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Begin
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If (pasmlabel(hp^.oper[0].sym)^.labelnr >= LoLab) and
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(pasmlabel(hp^.oper[0].sym)^.labelnr <= HiLab) and {range check, a jump can go past an assembler block!}
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Assigned(LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj) Then
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Begin
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p1 := LTable^[pasmlabel(hp^.oper[0].sym)^.labelnr-LoLab].PaiObj; {the jump's destination}
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SkipLabels(p1,p1);
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If (pai(p1)^.typ = ait_instruction) and
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(paicpu(p1)^.is_jmp) Then
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If { the next instruction after the label where the jump hp arrives}
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{ is unconditional or of the same type as hp, so continue }
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(paicpu(p1)^.condition in [C_None,hp^.condition]) or
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{ the next instruction after the label where the jump hp arrives}
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{ is the opposite of hp (so this one is never taken), but after }
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{ that one there is a branch that will be taken, so perform a }
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{ little hack: set p1 equal to this instruction (that's what the}
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{ last SkipLabels is for, only works with short bool evaluation)}
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((paicpu(p1)^.condition = inverse_cond[hp^.condition]) and
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SkipLabels(p1,p2) and
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(p2^.typ = ait_instruction) and
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(paicpu(p2)^.is_jmp) and
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(paicpu(p2)^.condition in [C_None,hp^.condition]) and
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SkipLabels(p1,p1)) Then
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Begin
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GetFinalDestination(asml, paicpu(p1));
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Dec(pasmlabel(hp^.oper[0].sym)^.refs);
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hp^.oper[0].sym:=paicpu(p1)^.oper[0].sym;
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inc(pasmlabel(hp^.oper[0].sym)^.refs);
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End
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Else
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If (paicpu(p1)^.condition = inverse_cond[hp^.condition]) then
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if not FindAnyLabel(p1,l) then
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begin
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{$ifdef finaldestdebug}
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insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
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strpnew('previous label inserted'))));
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{$endif finaldestdebug}
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getlabel(l);
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insertllitem(asml,p1,p1^.next,new(pai_label,init(l)));
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dec(pasmlabel(paicpu(hp)^.oper[0].sym)^.refs);
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hp^.oper[0].sym := l;
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inc(l^.refs);
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{ this won't work, since the new label isn't in the labeltable }
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{ so it will fail the rangecheck. Labeltable should become a }
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{ hashtable to support this: }
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{ GetFinalDestination(asml, hp); }
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end
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else
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begin
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{$ifdef finaldestdebug}
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insertllitem(asml,p1,p1^.next,new(pai_asm_comment,init(
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strpnew('next label reused'))));
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{$endif finaldestdebug}
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inc(l^.refs);
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hp^.oper[0].sym := l;
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GetFinalDestination(asml, hp);
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end;
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End;
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End;
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Function DoSubAddOpt(var p: Pai): Boolean;
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Begin
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DoSubAddOpt := False;
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If GetLastInstruction(p, hp1) And
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(hp1^.typ = ait_instruction) And
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(Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) then
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Case Paicpu(hp1)^.opcode Of
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A_DEC:
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If (Paicpu(hp1)^.oper[0].typ = top_reg) And
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(Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) Then
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Begin
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Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+1);
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AsmL^.Remove(hp1);
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Dispose(hp1, Done)
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End;
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A_SUB:
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If (Paicpu(hp1)^.oper[0].typ = top_const) And
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(Paicpu(hp1)^.oper[1].typ = top_reg) And
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(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
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Begin
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Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val+Paicpu(hp1)^.oper[0].val);
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AsmL^.Remove(hp1);
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Dispose(hp1, Done)
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End;
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A_ADD:
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If (Paicpu(hp1)^.oper[0].typ = top_const) And
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(Paicpu(hp1)^.oper[1].typ = top_reg) And
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(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
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Begin
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Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
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AsmL^.Remove(hp1);
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Dispose(hp1, Done);
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If (Paicpu(p)^.oper[0].val = 0) Then
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Begin
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hp1 := Pai(p^.next);
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AsmL^.Remove(p);
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Dispose(p, Done);
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If Not GetLastInstruction(hp1, p) Then
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p := hp1;
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DoSubAddOpt := True;
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End
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End;
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End;
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End;
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Begin
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P := BlockStart;
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UsedRegs := [];
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While (P <> BlockEnd) Do
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Begin
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UpDateUsedRegs(UsedRegs, Pai(p^.next));
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Case P^.Typ Of
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ait_instruction:
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Begin
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{ Handle Jmp Optimizations }
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if Paicpu(p)^.is_jmp then
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begin
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{the following if-block removes all code between a jmp and the next label,
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because it can never be executed}
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If (paicpu(p)^.opcode = A_JMP) Then
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Begin
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While GetNextInstruction(p, hp1) and
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((hp1^.typ <> ait_label) or
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{ skip unused labels, they're not referenced anywhere }
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Not(Pai_Label(hp1)^.l^.is_used)) Do
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If not(hp1^.typ in ([ait_label,ait_align]+skipinstr)) Then
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Begin
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AsmL^.Remove(hp1);
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Dispose(hp1, done);
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End;
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End;
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If GetNextInstruction(p, hp1) then
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Begin
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if FindLabel(pasmlabel(paicpu(p)^.oper[0].sym), hp1) then
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Begin
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hp2:=pai(hp1^.next);
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asml^.remove(p);
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dispose(p,done);
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p:=hp2;
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continue;
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end
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Else
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Begin
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if hp1^.typ = ait_label then
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SkipLabels(hp1,hp1);
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If (pai(hp1)^.typ=ait_instruction) and
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(paicpu(hp1)^.opcode=A_JMP) and
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GetNextInstruction(hp1, hp2) And
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FindLabel(PAsmLabel(paicpu(p)^.oper[0].sym), hp2)
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Then
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Begin
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if paicpu(p)^.opcode=A_Jcc then
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paicpu(p)^.condition:=inverse_cond[paicpu(p)^.condition]
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else
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begin
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If (LabDif <> 0) Then
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GetFinalDestination(asml, paicpu(p));
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p:=pai(p^.next);
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continue;
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end;
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Dec(pai_label(hp2)^.l^.refs);
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paicpu(p)^.oper[0].sym:=paicpu(hp1)^.oper[0].sym;
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Inc(paicpu(p)^.oper[0].sym^.refs);
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asml^.remove(hp1);
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dispose(hp1,done);
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If (LabDif <> 0) Then
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GetFinalDestination(asml, paicpu(p));
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end
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else
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If (LabDif <> 0) Then
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GetFinalDestination(asml, paicpu(p));
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end;
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end
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end
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else
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{ All other optimizes }
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begin
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For l := 0 to 2 Do
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If (Paicpu(p)^.oper[l].typ = top_ref) Then
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With Paicpu(p)^.oper[l].ref^ Do
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Begin
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If (base = R_NO) And
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(index <> R_NO) And
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(scalefactor in [0,1])
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Then
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Begin
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base := index;
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index := R_NO
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End
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End;
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Case Paicpu(p)^.opcode Of
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A_AND:
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Begin
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If (Paicpu(p)^.oper[0].typ = top_const) And
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(Paicpu(p)^.oper[1].typ = top_reg) And
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GetNextInstruction(p, hp1) And
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(Pai(hp1)^.typ = ait_instruction) And
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(Paicpu(hp1)^.opcode = A_AND) And
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(Paicpu(hp1)^.oper[0].typ = top_const) And
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(Paicpu(hp1)^.oper[1].typ = top_reg) And
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(Paicpu(hp1)^.oper[1].reg = Paicpu(hp1)^.oper[1].reg)
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Then
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{change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
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Begin
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Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val And Paicpu(hp1)^.oper[0].val);
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AsmL^.Remove(hp1);
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Dispose(hp1, Done)
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End
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Else
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{change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
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jump, but only if it's a conditional jump (PFV) }
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If (Paicpu(p)^.oper[1].typ = top_reg) And
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GetNextInstruction(p, hp1) And
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(hp1^.typ = ait_instruction) And
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(Paicpu(hp1)^.is_jmp) and
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(Paicpu(hp1)^.opcode<>A_JMP) and
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Not(Paicpu(p)^.oper[1].reg in UsedRegs) Then
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Paicpu(p)^.opcode := A_TEST;
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End;
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A_CMP:
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Begin
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If (Paicpu(p)^.oper[0].typ = top_const) And
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(Paicpu(p)^.oper[1].typ in [top_reg,top_ref]) And
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(Paicpu(p)^.oper[0].val = 0) Then
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{$ifdef foropt}
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If GetNextInstruction(p, hp1) And
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(hp1^.typ = ait_instruction) And
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(Paicpu(hp1)^.is_jmp) and
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(paicpu(hp1)^.opcode=A_Jcc) and
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(paicpu(hp1)^.condition in [C_LE,C_BE]) and
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GetNextInstruction(hp1,hp2) and
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(hp2^.typ = ait_instruction) and
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(Paicpu(hp2)^.opcode = A_DEC) And
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OpsEqual(Paicpu(hp2)^.oper[0],Paicpu(p)^.oper[1]) And
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GetNextInstruction(hp2, hp3) And
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(hp3^.typ = ait_instruction) and
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(Paicpu(hp3)^.is_jmp) and
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(Paicpu(hp3)^.opcode = A_JMP) And
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GetNextInstruction(hp3, hp4) And
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FindLabel(PAsmLabel(paicpu(hp1)^.oper[0].sym),hp4)
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Then
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Begin
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Paicpu(hp2)^.Opcode := A_SUB;
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Paicpu(hp2)^.Loadoper(1,Paicpu(hp2)^.oper[0]);
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Paicpu(hp2)^.LoadConst(0,1);
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Paicpu(hp2)^.ops:=2;
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Paicpu(hp3)^.Opcode := A_Jcc;
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Case paicpu(hp1)^.condition of
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C_LE: Paicpu(hp3)^.condition := C_GE;
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C_BE: Paicpu(hp3)^.condition := C_AE;
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End;
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AsmL^.Remove(p);
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AsmL^.Remove(hp1);
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Dispose(p, Done);
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Dispose(hp1, Done);
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p := hp2;
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continue;
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End
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Else
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{$endif foropt}
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{change "cmp $0, %reg" to "test %reg, %reg"}
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If (Paicpu(p)^.oper[1].typ = top_reg) Then
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Begin
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Paicpu(p)^.opcode := A_TEST;
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Paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
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End;
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End;
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A_FLD:
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Begin
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If (Paicpu(p)^.oper[0].typ = top_reg) And
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GetNextInstruction(p, hp1) And
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(hp1^.typ = Ait_Instruction) And
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(Paicpu(hp1)^.oper[0].typ = top_reg) And
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(Paicpu(hp1)^.oper[1].typ = top_reg) And
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(Paicpu(hp1)^.oper[0].reg = R_ST) And
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(Paicpu(hp1)^.oper[1].reg = R_ST1) Then
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{ change to
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fld reg fxxx reg,st
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fxxxp st, st1 (hp1)
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Remark: non commutative operations must be reversed!
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}
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begin
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Case Paicpu(hp1)^.opcode Of
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A_FMULP,A_FADDP,
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A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
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begin
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Case Paicpu(hp1)^.opcode Of
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A_FADDP: Paicpu(hp1)^.opcode := A_FADD;
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A_FMULP: Paicpu(hp1)^.opcode := A_FMUL;
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A_FSUBP: Paicpu(hp1)^.opcode := A_FSUBR;
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A_FSUBRP: Paicpu(hp1)^.opcode := A_FSUB;
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A_FDIVP: Paicpu(hp1)^.opcode := A_FDIVR;
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A_FDIVRP: Paicpu(hp1)^.opcode := A_FDIV;
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End;
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Paicpu(hp1)^.oper[0].reg := Paicpu(p)^.oper[0].reg;
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Paicpu(hp1)^.oper[1].reg := R_ST;
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AsmL^.Remove(p);
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Dispose(p, Done);
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p := hp1;
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Continue;
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end;
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end;
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end
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else
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If (Paicpu(p)^.oper[0].typ = top_ref) And
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GetNextInstruction(p, hp2) And
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(hp2^.typ = Ait_Instruction) And
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(Paicpu(hp2)^.oper[0].typ = top_reg) And
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(Paicpu(hp2)^.oper[1].typ = top_reg) And
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(Paicpu(p)^.opsize in [S_FS, S_FL]) And
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(Paicpu(hp2)^.oper[0].reg = R_ST) And
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(Paicpu(hp2)^.oper[1].reg = R_ST1) Then
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If GetLastInstruction(p, hp1) And
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(hp1^.typ = Ait_Instruction) And
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((Paicpu(hp1)^.opcode = A_FLD) Or
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(Paicpu(hp1)^.opcode = A_FST)) And
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(Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
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(Paicpu(hp1)^.oper[0].typ = top_ref) And
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RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^) Then
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If ((Paicpu(hp2)^.opcode = A_FMULP) Or
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(Paicpu(hp2)^.opcode = A_FADDP)) Then
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{ change to
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fld/fst mem1 (hp1) fld/fst mem1
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fld mem1 (p) fadd/
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faddp/ fmul st, st
|
|
fmulp st, st1 (hp2) }
|
|
Begin
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
If (Paicpu(hp2)^.opcode = A_FADDP) Then
|
|
Paicpu(hp2)^.opcode := A_FADD
|
|
Else
|
|
Paicpu(hp2)^.opcode := A_FMUL;
|
|
Paicpu(hp2)^.oper[1].reg := R_ST;
|
|
End
|
|
Else
|
|
{ change to
|
|
fld/fst mem1 (hp1) fld/fst mem1
|
|
fld mem1 (p) fld st}
|
|
Begin
|
|
Paicpu(p)^.changeopsize(S_FL);
|
|
Paicpu(p)^.loadreg(0,R_ST);
|
|
End
|
|
Else
|
|
Begin
|
|
Case Paicpu(hp2)^.opcode Of
|
|
A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
|
|
{ change to
|
|
fld/fst mem1 (hp1) fld/fst mem1
|
|
fld mem2 (p) fxxx mem2
|
|
fxxxp st, st1 (hp2) }
|
|
|
|
Begin
|
|
Case Paicpu(hp2)^.opcode Of
|
|
A_FADDP: Paicpu(p)^.opcode := A_FADD;
|
|
A_FMULP: Paicpu(p)^.opcode := A_FMUL;
|
|
A_FSUBP: Paicpu(p)^.opcode := A_FSUBR;
|
|
A_FSUBRP: Paicpu(p)^.opcode := A_FSUB;
|
|
A_FDIVP: Paicpu(p)^.opcode := A_FDIVR;
|
|
A_FDIVRP: Paicpu(p)^.opcode := A_FDIV;
|
|
End;
|
|
AsmL^.Remove(hp2);
|
|
Dispose(hp2, Done)
|
|
End
|
|
End
|
|
End
|
|
End;
|
|
A_FSTP,A_FISTP:
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].typ = top_ref) And
|
|
GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(((Paicpu(hp1)^.opcode = A_FLD) And
|
|
(Paicpu(p)^.opcode = A_FSTP)) Or
|
|
((Paicpu(p)^.opcode = A_FISTP) And
|
|
(Paicpu(hp1)^.opcode = A_FILD))) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_ref) And
|
|
(Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
|
|
RefsEqual(Paicpu(p)^.oper[0].ref^, Paicpu(hp1)^.oper[0].ref^)
|
|
Then
|
|
Begin
|
|
If GetNextInstruction(hp1, hp2) And
|
|
(hp2^.typ = ait_instruction) And
|
|
((Paicpu(hp2)^.opcode = A_LEAVE) Or
|
|
(Paicpu(hp2)^.opcode = A_RET)) And
|
|
(Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
|
|
(Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
|
|
(Paicpu(p)^.oper[0].ref^.Index = R_NO)
|
|
Then
|
|
Begin
|
|
AsmL^.Remove(p);
|
|
AsmL^.Remove(hp1);
|
|
Dispose(p, Done);
|
|
Dispose(hp1, Done);
|
|
p := hp2;
|
|
RemoveLastDeallocForFuncRes(asmL, p);
|
|
Continue
|
|
End
|
|
Else
|
|
{fst can't store an extended value!}
|
|
If (Paicpu(p)^.opsize <> S_FX) And
|
|
(Paicpu(p)^.opsize <> S_IQ) Then
|
|
Begin
|
|
If (Paicpu(p)^.opcode = A_FSTP) Then
|
|
Paicpu(p)^.opcode := A_FST
|
|
Else Paicpu(p)^.opcode := A_FIST;
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, done)
|
|
End
|
|
End;
|
|
End;
|
|
A_IMUL:
|
|
{changes certain "imul const, %reg"'s to lea sequences}
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].typ = Top_Const) And
|
|
(Paicpu(p)^.oper[1].typ = Top_Reg) And
|
|
(Paicpu(p)^.opsize = S_L) Then
|
|
If (Paicpu(p)^.oper[0].val = 1) Then
|
|
If (Paicpu(p)^.oper[2].typ = Top_None) Then
|
|
{remove "imul $1, reg"}
|
|
Begin
|
|
hp1 := Pai(p^.Next);
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
Continue;
|
|
End
|
|
Else
|
|
{change "imul $1, reg1, reg2" to "mov reg1, reg2"}
|
|
Begin
|
|
hp1 := New(Paicpu, Op_Reg_Reg(A_MOV, S_L, Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[2].reg));
|
|
InsertLLItem(AsmL, p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
End
|
|
Else If
|
|
((Paicpu(p)^.oper[2].typ = Top_Reg) or
|
|
(Paicpu(p)^.oper[2].typ = Top_None)) And
|
|
(aktoptprocessor < ClassP6) And
|
|
(Paicpu(p)^.oper[0].val <= 12) And
|
|
Not(CS_LittleSize in aktglobalswitches) And
|
|
(Not(GetNextInstruction(p, hp1)) Or
|
|
{GetNextInstruction(p, hp1) And}
|
|
Not((Pai(hp1)^.typ = ait_instruction) And
|
|
((paicpu(hp1)^.opcode=A_Jcc) and
|
|
(paicpu(hp1)^.condition in [C_O,C_NO]))))
|
|
Then
|
|
Begin
|
|
Reset_reference(tmpref);
|
|
Case Paicpu(p)^.oper[0].val Of
|
|
3: Begin
|
|
{imul 3, reg1, reg2 to
|
|
lea (reg1,reg1,2), reg2
|
|
imul 3, reg1 to
|
|
lea (reg1,reg1,2), reg1}
|
|
TmpRef.base := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.ScaleFactor := 2;
|
|
If (Paicpu(p)^.oper[2].typ = Top_None) Then
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
|
|
Else
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
End;
|
|
5: Begin
|
|
{imul 5, reg1, reg2 to
|
|
lea (reg1,reg1,4), reg2
|
|
imul 5, reg1 to
|
|
lea (reg1,reg1,4), reg1}
|
|
TmpRef.base := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.ScaleFactor := 4;
|
|
If (Paicpu(p)^.oper[2].typ = Top_None) Then
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
|
|
Else
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
End;
|
|
6: Begin
|
|
{imul 6, reg1, reg2 to
|
|
lea (,reg1,2), reg2
|
|
lea (reg2,reg1,4), reg2
|
|
imul 6, reg1 to
|
|
lea (reg1,reg1,2), reg1
|
|
add reg1, reg1}
|
|
If (aktoptprocessor <= Class386)
|
|
Then
|
|
Begin
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
If (Paicpu(p)^.oper[2].typ = Top_Reg)
|
|
Then
|
|
Begin
|
|
TmpRef.base := Paicpu(p)^.oper[2].reg;
|
|
TmpRef.ScaleFactor := 4;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
|
|
End
|
|
Else
|
|
Begin
|
|
hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
|
|
Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
|
|
End;
|
|
InsertLLItem(AsmL,p, p^.next, hp1);
|
|
Reset_reference(tmpref);
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.ScaleFactor := 2;
|
|
If (Paicpu(p)^.oper[2].typ = Top_Reg)
|
|
Then
|
|
Begin
|
|
TmpRef.base := R_NO;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
|
|
Paicpu(p)^.oper[2].reg));
|
|
End
|
|
Else
|
|
Begin
|
|
TmpRef.base := Paicpu(p)^.oper[1].reg;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
|
|
End;
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := Pai(hp1^.next);
|
|
End
|
|
End;
|
|
9: Begin
|
|
{imul 9, reg1, reg2 to
|
|
lea (reg1,reg1,8), reg2
|
|
imul 9, reg1 to
|
|
lea (reg1,reg1,8), reg1}
|
|
TmpRef.base := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.ScaleFactor := 8;
|
|
If (Paicpu(p)^.oper[2].typ = Top_None) Then
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg))
|
|
Else
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
End;
|
|
10: Begin
|
|
{imul 10, reg1, reg2 to
|
|
lea (reg1,reg1,4), reg2
|
|
add reg2, reg2
|
|
imul 10, reg1 to
|
|
lea (reg1,reg1,4), reg1
|
|
add reg1, reg1}
|
|
If (aktoptprocessor <= Class386) Then
|
|
Begin
|
|
If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
|
|
hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
|
|
Paicpu(p)^.oper[2].reg,Paicpu(p)^.oper[2].reg))
|
|
Else
|
|
hp1 := New(Paicpu, op_reg_reg(A_ADD, S_L,
|
|
Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p, p^.next, hp1);
|
|
TmpRef.base := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.ScaleFactor := 4;
|
|
If (Paicpu(p)^.oper[2].typ = Top_Reg)
|
|
Then
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg))
|
|
Else
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := Pai(hp1^.next);
|
|
End
|
|
End;
|
|
12: Begin
|
|
{imul 12, reg1, reg2 to
|
|
lea (,reg1,4), reg2
|
|
lea (,reg1,8) reg2
|
|
imul 12, reg1 to
|
|
lea (reg1,reg1,2), reg1
|
|
lea (,reg1,4), reg1}
|
|
If (aktoptprocessor <= Class386)
|
|
Then
|
|
Begin
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
|
|
Begin
|
|
TmpRef.base := Paicpu(p)^.oper[2].reg;
|
|
TmpRef.ScaleFactor := 8;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
|
|
End
|
|
Else
|
|
Begin
|
|
TmpRef.base := R_NO;
|
|
TmpRef.ScaleFactor := 4;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
|
|
End;
|
|
InsertLLItem(AsmL,p, p^.next, hp1);
|
|
Reset_reference(tmpref);
|
|
TmpRef.Index := Paicpu(p)^.oper[1].reg;
|
|
If (Paicpu(p)^.oper[2].typ = Top_Reg) Then
|
|
Begin
|
|
TmpRef.base := R_NO;
|
|
TmpRef.ScaleFactor := 4;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[2].reg));
|
|
End
|
|
Else
|
|
Begin
|
|
TmpRef.base := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.ScaleFactor := 2;
|
|
hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef), Paicpu(p)^.oper[1].reg));
|
|
End;
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := Pai(hp1^.next);
|
|
End
|
|
End
|
|
End;
|
|
End;
|
|
End;
|
|
A_LEA:
|
|
Begin
|
|
{removes seg register prefixes from LEA operations, as they
|
|
don't do anything}
|
|
Paicpu(p)^.oper[0].ref^.Segment := R_NO;
|
|
{changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
|
|
If (Paicpu(p)^.oper[0].ref^.Base In [R_EAX..R_EDI]) And
|
|
(Paicpu(p)^.oper[0].ref^.Index = R_NO) And
|
|
{$ifndef newOptimizations}
|
|
(Paicpu(p)^.oper[0].ref^.Offset = 0) And
|
|
{$endif newOptimizations}
|
|
(Not(Assigned(Paicpu(p)^.oper[0].ref^.Symbol))) Then
|
|
If (Paicpu(p)^.oper[0].ref^.Base <> Paicpu(p)^.oper[1].reg)
|
|
{$ifdef newOptimizations}
|
|
and (Paicpu(p)^.oper[0].ref^.Offset = 0)
|
|
{$endif newOptimizations}
|
|
Then
|
|
Begin
|
|
hp1 := New(Paicpu, op_reg_reg(A_MOV, S_L,Paicpu(p)^.oper[0].ref^.Base,
|
|
Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous,p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
Continue;
|
|
End
|
|
Else
|
|
{$ifdef newOptimizations}
|
|
if (Paicpu(p)^.oper[0].ref^.Offset = 0) then
|
|
{$endif newOptimizations}
|
|
Begin
|
|
hp1 := Pai(p^.Next);
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
Continue;
|
|
End
|
|
{$ifdef newOptimizations}
|
|
else
|
|
with Paicpu(p)^.oper[0].ref^ do
|
|
if (Base = Paicpu(p)^.oper[1].reg) then
|
|
begin
|
|
l := offset+offsetfixup;
|
|
case l of
|
|
1,-1:
|
|
begin
|
|
if l = 1 then
|
|
paicpu(p)^.opcode := A_INC
|
|
else paicpu(p)^.opcode := A_DEC;
|
|
paicpu(p)^.loadreg(0,Paicpu(p)^.oper[1].reg);
|
|
paicpu(p)^.ops := 1;
|
|
end;
|
|
else
|
|
begin
|
|
paicpu(p)^.opcode := A_ADD;
|
|
paicpu(p)^.loadconst(0,offset+offsetfixup);
|
|
end;
|
|
end;
|
|
end;
|
|
{$endif newOptimizations}
|
|
|
|
End;
|
|
A_MOV:
|
|
Begin
|
|
TmpUsedRegs := UsedRegs;
|
|
If (Paicpu(p)^.oper[1].typ = top_reg) And
|
|
(Paicpu(p)^.oper[1].reg In [R_EAX, R_EBX, R_EDX, R_EDI]) And
|
|
GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_MOV) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
|
|
Then
|
|
{we have "mov x, %treg; mov %treg, y}
|
|
If not(RegUsedAfterInstruction(Paicpu(p)^.oper[1].reg, hp1, TmpUsedRegs)) then
|
|
{we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
|
|
Case Paicpu(p)^.oper[0].typ Of
|
|
top_reg:
|
|
Begin
|
|
{ change "mov %reg, %treg; mov %treg, y"
|
|
to "mov %reg, y" }
|
|
Paicpu(hp1)^.LoadOper(0,Paicpu(p)^.oper[0]);
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
continue;
|
|
End;
|
|
top_ref:
|
|
If (Paicpu(hp1)^.oper[1].typ = top_reg) Then
|
|
Begin
|
|
{ change "mov mem, %treg; mov %treg, %reg"
|
|
to "mov mem, %reg" }
|
|
Paicpu(p)^.Loadoper(1,Paicpu(hp1)^.oper[1]);
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done);
|
|
continue;
|
|
End;
|
|
End
|
|
Else
|
|
Else
|
|
{Change "mov %reg1, %reg2; xxx %reg2, ???" to
|
|
"mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
|
|
penalty}
|
|
If (Paicpu(p)^.oper[0].typ = top_reg) And
|
|
(Paicpu(p)^.oper[1].typ = top_reg) And
|
|
GetNextInstruction(p,hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg)
|
|
Then
|
|
{we have "mov %reg1, %reg2; XXX %reg2, ???"}
|
|
Begin
|
|
If ((Paicpu(hp1)^.opcode = A_OR) Or
|
|
(Paicpu(hp1)^.opcode = A_TEST)) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[0].reg = Paicpu(hp1)^.oper[1].reg)
|
|
Then
|
|
{we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
|
|
Begin
|
|
TmpUsedRegs := UsedRegs;
|
|
If GetNextInstruction(hp1, hp2) And
|
|
(hp2^.typ = ait_instruction) And
|
|
paicpu(hp2)^.is_jmp and
|
|
Not(RegUsedAfterInstruction(Paicpu(hp1)^.oper[0].reg, hp1, TmpUsedRegs))
|
|
Then
|
|
{change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
|
|
"test %reg1, %reg1; jxx"}
|
|
Begin
|
|
Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
|
|
Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
|
|
AsmL^.Remove(p);
|
|
Dispose(p, done);
|
|
p := hp1;
|
|
continue
|
|
End
|
|
Else
|
|
{change "mov %reg1, %reg2; test/or %reg2, %reg2" to
|
|
"mov %reg1, %reg2; test/or %reg1, %reg1"}
|
|
Begin
|
|
Paicpu(hp1)^.Loadoper(0,Paicpu(p)^.oper[0]);
|
|
Paicpu(hp1)^.Loadoper(1,Paicpu(p)^.oper[0]);
|
|
End;
|
|
End
|
|
{ Else
|
|
If (Paicpu(p^.next)^.opcode
|
|
In [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
|
|
{change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
|
|
"mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
|
|
End
|
|
Else
|
|
{leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
|
|
x >= RetOffset) as it doesn't do anything (it writes either to a
|
|
parameter or to the temporary storage room for the function
|
|
result)}
|
|
If GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction)
|
|
Then
|
|
If ((Paicpu(hp1)^.opcode = A_LEAVE) Or
|
|
(Paicpu(hp1)^.opcode = A_RET)) And
|
|
(Paicpu(p)^.oper[1].typ = top_ref) And
|
|
(Paicpu(p)^.oper[1].ref^.base = procinfo^.FramePointer) And
|
|
(Paicpu(p)^.oper[1].ref^.offset >= procinfo^.Return_Offset) And
|
|
(Paicpu(p)^.oper[1].ref^.index = R_NO) And
|
|
(Paicpu(p)^.oper[0].typ = top_reg)
|
|
Then
|
|
Begin
|
|
AsmL^.Remove(p);
|
|
Dispose(p, done);
|
|
p := hp1;
|
|
RemoveLastDeallocForFuncRes(asmL,p);
|
|
End
|
|
Else
|
|
If (Paicpu(p)^.oper[0].typ = top_reg) And
|
|
(Paicpu(p)^.oper[1].typ = top_ref) And
|
|
(Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) And
|
|
(Paicpu(hp1)^.opcode = A_CMP) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_ref) And
|
|
RefsEqual(Paicpu(p)^.oper[1].ref^, Paicpu(hp1)^.oper[1].ref^)
|
|
Then
|
|
{change "mov reg, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
|
|
Paicpu(hp1)^.loadreg(1,Paicpu(p)^.oper[0].reg);
|
|
{ Next instruction is also a MOV ? }
|
|
If GetNextInstruction(p, hp1) And
|
|
(pai(hp1)^.typ = ait_instruction) and
|
|
(Paicpu(hp1)^.opcode = A_MOV) and
|
|
(Paicpu(hp1)^.opsize = Paicpu(p)^.opsize)
|
|
Then
|
|
Begin
|
|
If (Paicpu(hp1)^.oper[0].typ = Paicpu(p)^.oper[1].typ) and
|
|
(Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[0].typ)
|
|
Then
|
|
{mov reg1, mem1 or mov mem1, reg1
|
|
mov mem2, reg2 mov reg2, mem2}
|
|
Begin
|
|
If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
|
|
{mov reg1, mem1 or mov mem1, reg1
|
|
mov mem2, reg1 mov reg2, mem1}
|
|
Begin
|
|
If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[1]) Then
|
|
{ Removes the second statement from
|
|
mov reg1, mem1
|
|
mov mem1, reg1 }
|
|
Begin
|
|
AsmL^.remove(hp1);
|
|
Dispose(hp1,done);
|
|
End
|
|
Else
|
|
Begin
|
|
TmpUsedRegs := UsedRegs;
|
|
UpdateUsedRegs(TmpUsedRegs, Pai(hp1^.next));
|
|
If (Paicpu(p)^.oper[0].typ = top_reg) And
|
|
{ mov reg1, mem1
|
|
mov mem2, reg1 }
|
|
GetNextInstruction(hp1, hp2) And
|
|
(hp2^.typ = ait_instruction) And
|
|
(Paicpu(hp2)^.opcode = A_CMP) And
|
|
(Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
|
|
(Paicpu(hp2)^.oper[0].typ = TOp_Ref) And
|
|
(Paicpu(hp2)^.oper[1].typ = TOp_Reg) And
|
|
RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(p)^.oper[1].ref^) And
|
|
(Paicpu(hp2)^.oper[1].reg = Paicpu(p)^.oper[0].reg) And
|
|
Not(RegUsedAfterInstruction(Paicpu(p)^.oper[0].reg, hp2, TmpUsedRegs)) Then
|
|
{ change to
|
|
mov reg1, mem1 mov reg1, mem1
|
|
mov mem2, reg1 cmp reg1, mem2
|
|
cmp mem1, reg1 }
|
|
Begin
|
|
AsmL^.Remove(hp2);
|
|
Dispose(hp2, Done);
|
|
Paicpu(hp1)^.opcode := A_CMP;
|
|
Paicpu(hp1)^.loadref(1,newreference(Paicpu(hp1)^.oper[0].ref^));
|
|
Paicpu(hp1)^.loadreg(0,Paicpu(p)^.oper[0].reg);
|
|
End;
|
|
End;
|
|
End
|
|
Else
|
|
Begin
|
|
tmpUsedRegs := UsedRegs;
|
|
If GetNextInstruction(hp1, hp2) And
|
|
(Paicpu(p)^.oper[0].typ = top_ref) And
|
|
(Paicpu(p)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_ref) And
|
|
(Pai(hp2)^.typ = ait_instruction) And
|
|
(Paicpu(hp2)^.opcode = A_MOV) And
|
|
(Paicpu(hp2)^.opsize = Paicpu(p)^.opsize) and
|
|
(Paicpu(hp2)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp2)^.oper[0].typ = top_ref) And
|
|
RefsEqual(Paicpu(hp2)^.oper[0].ref^, Paicpu(hp1)^.oper[1].ref^) Then
|
|
If (Paicpu(p)^.oper[1].reg in [R_DI,R_EDI]) and
|
|
not(RegUsedAfterInstruction(R_EDI,hp1,tmpUsedRegs)) Then
|
|
{ mov mem1, %edi
|
|
mov %edi, mem2
|
|
mov mem2, reg2
|
|
to:
|
|
mov mem1, reg2
|
|
mov reg2, mem2}
|
|
Begin
|
|
Paicpu(p)^.Loadoper(1,Paicpu(hp2)^.oper[1]);
|
|
Paicpu(hp1)^.loadoper(0,Paicpu(hp2)^.oper[1]);
|
|
AsmL^.Remove(hp2);
|
|
Dispose(hp2,Done);
|
|
End
|
|
Else
|
|
If (Paicpu(p)^.oper[1].reg <> Paicpu(hp2)^.oper[1].reg) And
|
|
not(RegInRef(Paicpu(p)^.oper[1].reg,Paicpu(p)^.oper[0].ref^)) And
|
|
not(RegInRef(Paicpu(hp2)^.oper[1].reg,Paicpu(hp2)^.oper[0].ref^))
|
|
Then
|
|
{ mov mem1, reg1 mov mem1, reg1
|
|
mov reg1, mem2 mov reg1, mem2
|
|
mov mem2, reg2 mov mem2, reg1
|
|
to: to:
|
|
mov mem1, reg1 mov mem1, reg1
|
|
mov mem1, reg2 mov reg1, mem2
|
|
mov reg1, mem2
|
|
|
|
or (if mem1 depends on reg1
|
|
and/or if mem2 depends on reg2)
|
|
to:
|
|
mov mem1, reg1
|
|
mov reg1, mem2
|
|
mov reg1, reg2
|
|
}
|
|
Begin
|
|
Paicpu(hp1)^.LoadRef(0,newreference(Paicpu(p)^.oper[0].ref^));
|
|
Paicpu(hp1)^.LoadReg(1,Paicpu(hp2)^.oper[1].reg);
|
|
Paicpu(hp2)^.LoadRef(1,newreference(Paicpu(hp2)^.oper[0].ref^));
|
|
Paicpu(hp2)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
|
|
End
|
|
Else
|
|
If (Paicpu(hp1)^.Oper[0].reg <> Paicpu(hp2)^.Oper[1].reg) Then
|
|
Paicpu(hp2)^.LoadReg(0,Paicpu(hp1)^.Oper[0].reg)
|
|
Else
|
|
Begin
|
|
AsmL^.Remove(hp2);
|
|
Dispose(hp2, Done);
|
|
End
|
|
End;
|
|
End
|
|
Else
|
|
(* {movl [mem1],reg1
|
|
movl [mem1],reg2
|
|
to:
|
|
movl [mem1],reg1
|
|
movl reg1,reg2 }
|
|
If (Paicpu(p)^.oper[0].typ = top_ref) and
|
|
(Paicpu(p)^.oper[1].typ = top_reg) and
|
|
(Paicpu(hp1)^.oper[0].typ = top_ref) and
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) and
|
|
(Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
|
|
RefsEqual(TReference(Paicpu(p)^.oper[0]^),Paicpu(hp1)^.oper[0]^.ref^) and
|
|
(Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.base) and
|
|
(Paicpu(p)^.oper[1].reg<>Paicpu(hp1)^.oper[0]^.ref^.index) then
|
|
Paicpu(hp1)^.LoadReg(0,Paicpu(p)^.oper[1].reg)
|
|
Else*)
|
|
{ movl const1,[mem1]
|
|
movl [mem1],reg1
|
|
to:
|
|
movl const1,reg1
|
|
movl reg1,[mem1] }
|
|
If (Paicpu(p)^.oper[0].typ = top_const) and
|
|
(Paicpu(p)^.oper[1].typ = top_ref) and
|
|
(Paicpu(hp1)^.oper[0].typ = top_ref) and
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) and
|
|
(Paicpu(p)^.opsize = Paicpu(hp1)^.opsize) and
|
|
RefsEqual(Paicpu(hp1)^.oper[0].ref^,Paicpu(p)^.oper[1].ref^) then
|
|
Begin
|
|
Paicpu(hp1)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
|
|
Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[1].ref^));
|
|
Paicpu(p)^.LoadReg(1,Paicpu(hp1)^.oper[0].reg);
|
|
End
|
|
End;
|
|
End;
|
|
A_MOVZX:
|
|
Begin
|
|
{removes superfluous And's after movzx's}
|
|
If (Paicpu(p)^.oper[1].typ = top_reg) And
|
|
GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_AND) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_const) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
|
|
Then
|
|
Case Paicpu(p)^.opsize Of
|
|
S_BL, S_BW:
|
|
If (Paicpu(hp1)^.oper[0].val = $ff) Then
|
|
Begin
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done);
|
|
End;
|
|
S_WL:
|
|
If (Paicpu(hp1)^.oper[0].val = $ffff) Then
|
|
Begin
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done);
|
|
End;
|
|
End;
|
|
{changes some movzx constructs to faster synonims (all examples
|
|
are given with eax/ax, but are also valid for other registers)}
|
|
If (Paicpu(p)^.oper[1].typ = top_reg) Then
|
|
If (Paicpu(p)^.oper[0].typ = top_reg) Then
|
|
Case Paicpu(p)^.opsize of
|
|
S_BW:
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].reg = Reg16ToReg8(Paicpu(p)^.oper[1].reg)) And
|
|
Not(CS_LittleSize In aktglobalswitches)
|
|
Then
|
|
{Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
|
|
Begin
|
|
Paicpu(p)^.opcode := A_AND;
|
|
Paicpu(p)^.changeopsize(S_W);
|
|
Paicpu(p)^.LoadConst(0,$ff);
|
|
End
|
|
Else
|
|
If GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_AND) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_const) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
|
|
Then
|
|
{Change "movzbw %reg1, %reg2; andw $const, %reg2"
|
|
to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
|
|
Begin
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Paicpu(p)^.changeopsize(S_W);
|
|
Paicpu(p)^.LoadReg(0,Reg8ToReg16(Paicpu(p)^.oper[0].reg));
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
|
|
End;
|
|
End;
|
|
S_BL:
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].reg = Reg32ToReg8(Paicpu(p)^.oper[1].reg)) And
|
|
Not(CS_LittleSize in aktglobalswitches)
|
|
Then
|
|
{Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
|
|
Begin
|
|
Paicpu(p)^.opcode := A_AND;
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(p)^.loadconst(0,$ff)
|
|
End
|
|
Else
|
|
If GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_AND) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_const) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
|
|
Then
|
|
{Change "movzbl %reg1, %reg2; andl $const, %reg2"
|
|
to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
|
|
Begin
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(p)^.LoadReg(0,Reg8ToReg32(Paicpu(p)^.oper[0].reg));
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
|
|
End
|
|
End;
|
|
S_WL:
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].reg = Reg32ToReg16(Paicpu(p)^.oper[1].reg)) And
|
|
Not(CS_LittleSize In aktglobalswitches)
|
|
Then
|
|
{Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
|
|
Begin
|
|
Paicpu(p)^.opcode := A_AND;
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(p)^.LoadConst(0,$ffff);
|
|
End
|
|
Else
|
|
If GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_AND) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_const) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg)
|
|
Then
|
|
{Change "movzwl %reg1, %reg2; andl $const, %reg2"
|
|
to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
|
|
Begin
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(p)^.LoadReg(0,Reg16ToReg32(Paicpu(p)^.oper[0].reg));
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
|
|
End;
|
|
End;
|
|
End
|
|
Else
|
|
If (Paicpu(p)^.oper[0].typ = top_ref) Then
|
|
Begin
|
|
If GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_AND) And
|
|
(Paicpu(hp1)^.oper[0].typ = Top_Const) And
|
|
(Paicpu(hp1)^.oper[1].typ = Top_Reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Then
|
|
Begin
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Case Paicpu(p)^.opsize Of
|
|
S_BL:
|
|
Begin
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
|
|
End;
|
|
S_WL:
|
|
Begin
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ffff);
|
|
End;
|
|
S_BW:
|
|
Begin
|
|
Paicpu(p)^.changeopsize(S_W);
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val And $ff);
|
|
End;
|
|
End;
|
|
End;
|
|
End;
|
|
End;
|
|
A_POP:
|
|
Begin
|
|
if (Paicpu(p)^.oper[0].typ = top_reg) And
|
|
GetNextInstruction(p, hp1) And
|
|
(pai(hp1)^.typ=ait_instruction) and
|
|
(Paicpu(hp1)^.opcode=A_PUSH) and
|
|
(Paicpu(hp1)^.oper[0].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[0].reg=Paicpu(p)^.oper[0].reg) then
|
|
{ This can't be done, because the register which is popped
|
|
can still be used after the push (PFV)
|
|
If (Not(cs_regalloc in aktglobalswitches)) Then
|
|
Begin
|
|
hp2:=pai(hp1^.next);
|
|
asml^.remove(p);
|
|
asml^.remove(hp1);
|
|
dispose(p,done);
|
|
dispose(hp1,done);
|
|
p:=hp2;
|
|
continue
|
|
End
|
|
Else }
|
|
Begin
|
|
{ change it to a two op operation }
|
|
Paicpu(p)^.oper[1].typ:=top_none;
|
|
Paicpu(p)^.ops:=2;
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Paicpu(p)^.Loadoper(1,Paicpu(p)^.oper[0]);
|
|
Reset_reference(tmpref);
|
|
TmpRef.base := R_ESP;
|
|
Paicpu(p)^.LoadRef(0,newReference(TmpRef));
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done)
|
|
End;
|
|
end;
|
|
A_PUSH:
|
|
Begin
|
|
If (Paicpu(p)^.opsize = S_W) And
|
|
(Paicpu(p)^.oper[0].typ = Top_Const) And
|
|
GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_PUSH) And
|
|
(Paicpu(hp1)^.oper[0].typ = Top_Const) And
|
|
(Paicpu(hp1)^.opsize = S_W) Then
|
|
Begin
|
|
Paicpu(p)^.changeopsize(S_L);
|
|
Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val shl 16 + word(Paicpu(hp1)^.oper[0].val));
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done)
|
|
End;
|
|
End;
|
|
A_SHL, A_SAL:
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].typ = Top_Const) And
|
|
(Paicpu(p)^.oper[1].typ = Top_Reg) And
|
|
(Paicpu(p)^.opsize = S_L) And
|
|
(Paicpu(p)^.oper[0].val <= 3)
|
|
{Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
|
|
Then
|
|
Begin
|
|
TmpBool1 := True; {should we check the next instruction?}
|
|
TmpBool2 := False; {have we found an add/sub which could be
|
|
integrated in the lea?}
|
|
Reset_reference(tmpref);
|
|
TmpRef.index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
|
|
While TmpBool1 And
|
|
GetNextInstruction(p, hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
((Paicpu(hp1)^.opcode = A_ADD) Or
|
|
(Paicpu(hp1)^.opcode = A_SUB)) And
|
|
(Paicpu(hp1)^.oper[1].typ = Top_Reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) Do
|
|
Begin
|
|
TmpBool1 := False;
|
|
If (Paicpu(hp1)^.oper[0].typ = Top_Const)
|
|
Then
|
|
Begin
|
|
TmpBool1 := True;
|
|
TmpBool2 := True;
|
|
If Paicpu(hp1)^.opcode = A_ADD Then
|
|
Inc(TmpRef.offset, Paicpu(hp1)^.oper[0].val)
|
|
Else
|
|
Dec(TmpRef.offset, Paicpu(hp1)^.oper[0].val);
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done);
|
|
End
|
|
Else
|
|
If (Paicpu(hp1)^.oper[0].typ = Top_Reg) And
|
|
(Paicpu(hp1)^.opcode = A_ADD) And
|
|
(TmpRef.base = R_NO) Then
|
|
Begin
|
|
TmpBool1 := True;
|
|
TmpBool2 := True;
|
|
TmpRef.base := Paicpu(hp1)^.oper[0].reg;
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done);
|
|
End;
|
|
End;
|
|
If TmpBool2 Or
|
|
((aktoptprocessor < ClassP6) And
|
|
(Paicpu(p)^.oper[0].val <= 3) And
|
|
Not(CS_LittleSize in aktglobalswitches))
|
|
Then
|
|
Begin
|
|
If Not(TmpBool2) And
|
|
(Paicpu(p)^.oper[0].val = 1)
|
|
Then
|
|
Begin
|
|
hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
|
|
Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg))
|
|
End
|
|
Else hp1 := New(Paicpu, op_ref_reg(A_LEA, S_L, newReference(TmpRef),
|
|
Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
End;
|
|
End
|
|
Else
|
|
If (aktoptprocessor < ClassP6) And
|
|
(Paicpu(p)^.oper[0].typ = top_const) And
|
|
(Paicpu(p)^.oper[1].typ = top_reg) Then
|
|
If (Paicpu(p)^.oper[0].val = 1)
|
|
Then
|
|
{changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
|
|
but faster on a 486, and pairable in both U and V pipes on the Pentium
|
|
(unlike shl, which is only pairable in the U pipe)}
|
|
Begin
|
|
hp1 := new(Paicpu,op_reg_reg(A_ADD,Paicpu(p)^.opsize,
|
|
Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, done);
|
|
p := hp1;
|
|
End
|
|
Else If (Paicpu(p)^.opsize = S_L) and
|
|
(Paicpu(p)^.oper[0].val<= 3) Then
|
|
{changes "shl $2, %reg" to "lea (,%reg,4), %reg"
|
|
"shl $3, %reg" to "lea (,%reg,8), %reg}
|
|
Begin
|
|
Reset_reference(tmpref);
|
|
TmpRef.index := Paicpu(p)^.oper[1].reg;
|
|
TmpRef.scalefactor := 1 shl Paicpu(p)^.oper[0].val;
|
|
hp1 := new(Paicpu,op_ref_reg(A_LEA,S_L,newReference(TmpRef), Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous, p^.next, hp1);
|
|
Dispose(p, done);
|
|
p := hp1;
|
|
End
|
|
End;
|
|
A_SAR, A_SHR:
|
|
{changes the code sequence
|
|
shr/sar const1, x
|
|
shl const2, x
|
|
to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
|
|
Begin
|
|
If GetNextInstruction(p, hp1) And
|
|
(pai(hp1)^.typ = ait_instruction) and
|
|
(Paicpu(hp1)^.opcode = A_SHL) and
|
|
(Paicpu(p)^.oper[0].typ = top_const) and
|
|
(Paicpu(hp1)^.oper[0].typ = top_const) and
|
|
(Paicpu(hp1)^.opsize = Paicpu(p)^.opsize) And
|
|
(Paicpu(hp1)^.oper[1].typ = Paicpu(p)^.oper[1].typ) And
|
|
OpsEqual(Paicpu(hp1)^.oper[1], Paicpu(p)^.oper[1])
|
|
Then
|
|
If (Paicpu(p)^.oper[0].val > Paicpu(hp1)^.oper[0].val) And
|
|
Not(CS_LittleSize In aktglobalswitches)
|
|
Then
|
|
{ shr/sar const1, %reg
|
|
shl const2, %reg
|
|
with const1 > const2 }
|
|
Begin
|
|
Paicpu(p)^.LoadConst(0,Paicpu(p)^.oper[0].val-Paicpu(hp1)^.oper[0].val);
|
|
Paicpu(hp1)^.opcode := A_AND;
|
|
l := (1 shl (Paicpu(hp1)^.oper[0].val)) - 1;
|
|
Case Paicpu(p)^.opsize Of
|
|
S_L: Paicpu(hp1)^.LoadConst(0,l Xor longint(-1));
|
|
S_B: Paicpu(hp1)^.LoadConst(0,l Xor $ff);
|
|
S_W: Paicpu(hp1)^.LoadConst(0,l Xor $ffff);
|
|
End;
|
|
End
|
|
Else
|
|
If (Paicpu(p)^.oper[0].val<Paicpu(hp1)^.oper[0].val) And
|
|
Not(CS_LittleSize In aktglobalswitches)
|
|
Then
|
|
{ shr/sar const1, %reg
|
|
shl const2, %reg
|
|
with const1 < const2 }
|
|
Begin
|
|
Paicpu(hp1)^.LoadConst(0,Paicpu(hp1)^.oper[0].val-Paicpu(p)^.oper[0].val);
|
|
Paicpu(p)^.opcode := A_AND;
|
|
l := (1 shl (Paicpu(p)^.oper[0].val))-1;
|
|
Case Paicpu(p)^.opsize Of
|
|
S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
|
|
S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
|
|
S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
|
|
End;
|
|
End
|
|
Else
|
|
{ shr/sar const1, %reg
|
|
shl const2, %reg
|
|
with const1 = const2 }
|
|
Begin
|
|
Paicpu(p)^.opcode := A_AND;
|
|
l := (1 shl (Paicpu(p)^.oper[0].val))-1;
|
|
Case Paicpu(p)^.opsize Of
|
|
S_B: Paicpu(p)^.LoadConst(0,l Xor $ff);
|
|
S_W: Paicpu(p)^.LoadConst(0,l Xor $ffff);
|
|
S_L: Paicpu(p)^.LoadConst(0,l Xor $ffffffff);
|
|
End;
|
|
AsmL^.remove(hp1);
|
|
dispose(hp1, done);
|
|
End;
|
|
End;
|
|
A_SETcc :
|
|
{ changes
|
|
setcc (funcres) setcc reg
|
|
movb (funcres), reg to leave/ret
|
|
leave/ret }
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].typ = top_ref) And
|
|
GetNextInstruction(p, hp1) And
|
|
GetNextInstruction(hp1, hp2) And
|
|
(hp2^.typ = ait_instruction) And
|
|
((Paicpu(hp2)^.opcode = A_LEAVE) or
|
|
(Paicpu(hp2)^.opcode = A_RET)) And
|
|
(Paicpu(p)^.oper[0].ref^.Base = procinfo^.FramePointer) And
|
|
(Paicpu(p)^.oper[0].ref^.Index = R_NO) And
|
|
(Paicpu(p)^.oper[0].ref^.Offset >= procinfo^.Return_Offset) And
|
|
(hp1^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_MOV) And
|
|
(Paicpu(hp1)^.opsize = S_B) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_ref) And
|
|
RefsEqual(Paicpu(hp1)^.oper[0].ref^, Paicpu(p)^.oper[0].ref^) Then
|
|
Begin
|
|
Paicpu(p)^.LoadReg(0,Paicpu(hp1)^.oper[1].reg);
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done)
|
|
End
|
|
End;
|
|
A_SUB:
|
|
{ * change "subl $2, %esp; pushw x" to "pushl x"}
|
|
{ * change "sub/add const1, reg" or "dec reg" followed by
|
|
"sub const2, reg" to one "sub ..., reg" }
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].typ = top_const) And
|
|
(Paicpu(p)^.oper[1].typ = top_reg) Then
|
|
If (Paicpu(p)^.oper[0].val = 2) And
|
|
(Paicpu(p)^.oper[1].reg = R_ESP) Then
|
|
Begin
|
|
hp1 := Pai(p^.next);
|
|
While Assigned(hp1) And
|
|
(Pai(hp1)^.typ In [ait_instruction]+SkipInstr) And
|
|
Not((Pai(hp1)^.typ = ait_instruction) And
|
|
((Paicpu(hp1)^.opcode = A_CALL) or
|
|
(Paicpu(hp1)^.opcode = A_PUSH) or
|
|
((Paicpu(hp1)^.opcode = A_MOV) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_ref) And
|
|
(Paicpu(hp1)^.oper[1].ref^.base = R_ESP)))) do
|
|
hp1 := Pai(hp1^.next);
|
|
If Assigned(hp1) And
|
|
(Pai(hp1)^.typ = ait_instruction) And
|
|
(Paicpu(hp1)^.opcode = A_PUSH) And
|
|
(Paicpu(hp1)^.opsize = S_W)
|
|
Then
|
|
Begin
|
|
Paicpu(hp1)^.changeopsize(S_L);
|
|
if Paicpu(hp1)^.oper[0].typ=top_reg then
|
|
Paicpu(hp1)^.LoadReg(0,Reg16ToReg32(Paicpu(hp1)^.oper[0].reg));
|
|
hp1 := Pai(p^.next);
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
Continue
|
|
End;
|
|
If DoSubAddOpt(p) Then continue;
|
|
End
|
|
Else If DoSubAddOpt(p) Then Continue
|
|
End;
|
|
A_TEST, A_OR:
|
|
{removes the line marked with (x) from the sequence
|
|
And/or/xor/add/sub/... $x, %y
|
|
test/or %y, %y (x)
|
|
j(n)z _Label
|
|
as the first instruction already adjusts the ZF}
|
|
Begin
|
|
If OpsEqual(Paicpu(p)^.oper[0],Paicpu(p)^.oper[1]) Then
|
|
If GetLastInstruction(p, hp1) And
|
|
(pai(hp1)^.typ = ait_instruction) Then
|
|
Case Paicpu(hp1)^.opcode Of
|
|
A_ADD, A_SUB, A_OR, A_XOR, A_AND, A_SHL, A_SHR:
|
|
Begin
|
|
If OpsEqual(Paicpu(hp1)^.oper[1],Paicpu(p)^.oper[0]) Then
|
|
Begin
|
|
hp1 := pai(p^.next);
|
|
asml^.remove(p);
|
|
dispose(p, done);
|
|
p := pai(hp1);
|
|
continue
|
|
End;
|
|
End;
|
|
A_DEC, A_INC, A_NEG:
|
|
Begin
|
|
If OpsEqual(Paicpu(hp1)^.oper[0],Paicpu(p)^.oper[0]) Then
|
|
Begin
|
|
Case Paicpu(hp1)^.opcode Of
|
|
A_DEC, A_INC:
|
|
{replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
|
|
Begin
|
|
Case Paicpu(hp1)^.opcode Of
|
|
A_DEC: Paicpu(hp1)^.opcode := A_SUB;
|
|
A_INC: Paicpu(hp1)^.opcode := A_ADD;
|
|
End;
|
|
Paicpu(hp1)^.Loadoper(1,Paicpu(hp1)^.oper[0]);
|
|
Paicpu(hp1)^.LoadConst(0,1);
|
|
Paicpu(hp1)^.ops:=2;
|
|
End
|
|
End;
|
|
hp1 := pai(p^.next);
|
|
asml^.remove(p);
|
|
dispose(p, done);
|
|
p := pai(hp1);
|
|
continue
|
|
End;
|
|
End
|
|
End
|
|
Else
|
|
End;
|
|
A_XOR:
|
|
If (Paicpu(p)^.oper[0].typ = top_reg) And
|
|
(Paicpu(p)^.oper[1].typ = top_reg) And
|
|
(Paicpu(p)^.oper[0].reg = Paicpu(p)^.oper[1].reg) then
|
|
{ temporarily change this to 'mov reg,0' to make it easier }
|
|
{ for the CSE. Will be changed back in pass 2 }
|
|
begin
|
|
paicpu(p)^.opcode := A_MOV;
|
|
paicpu(p)^.loadconst(0,0);
|
|
end;
|
|
End;
|
|
end; { if is_jmp }
|
|
End;
|
|
{ ait_label:
|
|
Begin
|
|
If Not(Pai_Label(p)^.l^.is_used)
|
|
Then
|
|
Begin
|
|
hp1 := Pai(p^.next);
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
Continue
|
|
End;
|
|
End;}
|
|
End;
|
|
p:=pai(p^.next);
|
|
end;
|
|
end;
|
|
|
|
{$ifdef foldArithOps}
|
|
Function IsArithOp(opcode: TAsmOp): Boolean;
|
|
Begin
|
|
IsArithOp := False;
|
|
Case opcode Of
|
|
A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR: IsArithOp := True
|
|
End;
|
|
End;
|
|
{$endif foldArithOps}
|
|
|
|
|
|
Procedure PeepHoleOptPass2(AsmL: PAasmOutput; BlockStart, BlockEnd: Pai);
|
|
|
|
var
|
|
p,hp1,hp2: pai;
|
|
{$ifdef foldArithOps}
|
|
UsedRegs, TmpUsedRegs: TRegSet;
|
|
{$endif foldArithOps}
|
|
Begin
|
|
P := BlockStart;
|
|
{$ifdef foldArithOps}
|
|
UsedRegs := [];
|
|
{$endif foldArithOps}
|
|
While (P <> BlockEnd) Do
|
|
Begin
|
|
{$ifdef foldArithOps}
|
|
UpdateUsedRegs(UsedRegs, Pai(p^.next));
|
|
{$endif foldArithOps}
|
|
Case P^.Typ Of
|
|
Ait_Instruction:
|
|
Begin
|
|
Case Paicpu(p)^.opcode Of
|
|
A_CALL:
|
|
If (AktOptProcessor < ClassP6) And
|
|
GetNextInstruction(p, hp1) And
|
|
(hp1^.typ = ait_instruction) And
|
|
(paicpu(hp1)^.opcode = A_JMP) Then
|
|
Begin
|
|
Inc(paicpu(hp1)^.oper[0].sym^.refs);
|
|
hp2 := New(Paicpu,op_sym(A_PUSH,S_L,paicpu(hp1)^.oper[0].sym));
|
|
InsertLLItem(AsmL, p^.previous, p, hp2);
|
|
Paicpu(p)^.opcode := A_JMP;
|
|
AsmL^.Remove(hp1);
|
|
Dispose(hp1, Done)
|
|
End;
|
|
A_MOV:
|
|
Begin
|
|
If (Paicpu(p)^.oper[0].typ = top_reg) And
|
|
(Paicpu(p)^.oper[1].typ = top_reg) And
|
|
GetNextInstruction(p, hp1) And
|
|
(hp1^.typ = ait_Instruction) And
|
|
((Paicpu(hp1)^.opcode = A_MOV) or
|
|
(Paicpu(hp1)^.opcode = A_MOVZX) or
|
|
(Paicpu(hp1)^.opcode = A_MOVSX)) And
|
|
(Paicpu(hp1)^.oper[0].typ = top_ref) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
((Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Or
|
|
(Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg)) And
|
|
(Reg32(Paicpu(hp1)^.oper[1].reg) = Paicpu(p)^.oper[1].reg) Then
|
|
{mov reg1, reg2
|
|
mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
|
|
Begin
|
|
If (Paicpu(hp1)^.oper[0].ref^.Base = Paicpu(p)^.oper[1].reg) Then
|
|
Paicpu(hp1)^.oper[0].ref^.Base := Paicpu(p)^.oper[0].reg;
|
|
If (Paicpu(hp1)^.oper[0].ref^.Index = Paicpu(p)^.oper[1].reg) Then
|
|
Paicpu(hp1)^.oper[0].ref^.Index := Paicpu(p)^.oper[0].reg;
|
|
AsmL^.Remove(p);
|
|
Dispose(p, Done);
|
|
p := hp1;
|
|
Continue;
|
|
End
|
|
{$ifdef foldArithOps}
|
|
Else If (Paicpu(p)^.oper[0].typ = top_ref) And
|
|
GetNextInstruction(p,hp1) And
|
|
(hp1^.typ = ait_instruction) And
|
|
IsArithOp(Paicpu(hp1)^.opcode) And
|
|
(Paicpu(hp1)^.oper[0].typ in [top_reg,top_const]) And
|
|
(Paicpu(hp1)^.oper[1].typ = top_reg) And
|
|
(Paicpu(hp1)^.oper[1].reg = Paicpu(p)^.oper[1].reg) And
|
|
GetNextInstruction(hp1,hp2) And
|
|
(hp2^.typ = ait_instruction) And
|
|
(Paicpu(hp2)^.opcode = A_MOV) And
|
|
(Paicpu(hp2)^.oper[0].typ = top_reg) And
|
|
(Paicpu(hp2)^.oper[0].reg = Paicpu(p)^.oper[1].reg) And
|
|
(Paicpu(hp2)^.oper[1].typ = top_ref) Then
|
|
Begin
|
|
TmpUsedRegs := UsedRegs;
|
|
UpdateUsedRegs(TmpUsedRegs,Pai(hp1^.next));
|
|
If (RefsEqual(Paicpu(hp2)^.oper[1].ref^, Paicpu(p)^.oper[0].ref^) And
|
|
Not(RegUsedAfterInstruction(Reg32(Paicpu(p)^.oper[1].reg),
|
|
hp2, TmpUsedRegs)))
|
|
Then
|
|
{ change mov (ref), reg }
|
|
{ add/sub/or/... reg2/$const, reg }
|
|
{ mov (reg), ref }
|
|
{ # release reg }
|
|
{ to add/sub/or/... reg2/$const, (ref) }
|
|
Begin
|
|
Paicpu(hp1)^.LoadRef(1,newreference(Paicpu(p)^.oper[0].ref^));
|
|
AsmL^.Remove(p);
|
|
AsmL^.Remove(hp2);
|
|
Dispose(p,done);
|
|
Dispose(hp2,Done);
|
|
p := hp1
|
|
End;
|
|
End
|
|
{$endif foldArithOps}
|
|
else if (Paicpu(p)^.oper[0].typ = Top_Const) And
|
|
(Paicpu(p)^.oper[0].val = 0) And
|
|
(Paicpu(p)^.oper[1].typ = Top_Reg) Then
|
|
{ change "mov $0, %reg" into "xor %reg, %reg" }
|
|
Begin
|
|
Paicpu(p)^.opcode := A_XOR;
|
|
Paicpu(p)^.LoadReg(0,Paicpu(p)^.oper[1].reg);
|
|
End
|
|
End;
|
|
A_MOVZX:
|
|
Begin
|
|
If (Paicpu(p)^.oper[1].typ = top_reg) Then
|
|
If (Paicpu(p)^.oper[0].typ = top_reg)
|
|
Then
|
|
Case Paicpu(p)^.opsize of
|
|
S_BL:
|
|
Begin
|
|
If IsGP32Reg(Paicpu(p)^.oper[1].reg) And
|
|
Not(CS_LittleSize in aktglobalswitches) And
|
|
(aktoptprocessor = ClassP5)
|
|
Then
|
|
{Change "movzbl %reg1, %reg2" to
|
|
"xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
|
|
PentiumMMX}
|
|
Begin
|
|
hp1 := New(Paicpu, op_reg_reg(A_XOR, S_L,
|
|
Paicpu(p)^.oper[1].reg, Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous, p, hp1);
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Paicpu(p)^.changeopsize(S_B);
|
|
Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
|
|
End;
|
|
End;
|
|
End
|
|
Else
|
|
If (Paicpu(p)^.oper[0].typ = top_ref) And
|
|
(Paicpu(p)^.oper[0].ref^.base <> Paicpu(p)^.oper[1].reg) And
|
|
(Paicpu(p)^.oper[0].ref^.index <> Paicpu(p)^.oper[1].reg) And
|
|
Not(CS_LittleSize in aktglobalswitches) And
|
|
IsGP32Reg(Paicpu(p)^.oper[1].reg) And
|
|
(aktoptprocessor = ClassP5) And
|
|
(Paicpu(p)^.opsize = S_BL)
|
|
Then
|
|
{changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
|
|
Pentium and PentiumMMX}
|
|
Begin
|
|
hp1 := New(Paicpu,op_reg_reg(A_XOR, S_L, Paicpu(p)^.oper[1].reg,
|
|
Paicpu(p)^.oper[1].reg));
|
|
Paicpu(p)^.opcode := A_MOV;
|
|
Paicpu(p)^.changeopsize(S_B);
|
|
Paicpu(p)^.LoadReg(1,Reg32ToReg8(Paicpu(p)^.oper[1].reg));
|
|
InsertLLItem(AsmL,p^.previous, p, hp1);
|
|
End;
|
|
End;
|
|
End;
|
|
End;
|
|
End;
|
|
p := Pai(p^.next)
|
|
End;
|
|
End;
|
|
|
|
End.
|
|
|
|
{
|
|
$Log$
|
|
Revision 1.80 2000-01-22 16:05:15 jonas
|
|
+ change "lea x(reg),reg" to "add x,reg" (-dnewoptimizations)
|
|
* detection whether edi is used after instructions (since regalloc
|
|
info for it is now available)
|
|
* better regUsedAfterInstruction function
|
|
|
|
Revision 1.79 2000/01/21 11:26:19 pierre
|
|
* bug fix for bug 802
|
|
|
|
Revision 1.78 2000/01/11 17:14:49 jonas
|
|
* fixed a serious memory leak
|
|
|
|
Revision 1.77 2000/01/09 12:35:02 jonas
|
|
* changed edi allocation to use getexplicitregister32/ungetregister
|
|
(adapted tgeni386 a bit for this) and enabled it by default
|
|
* fixed very big and stupid bug of mine in cg386mat that broke the
|
|
include() code (and make cycle :( ) if you compiled without
|
|
-dnewoptimizations
|
|
|
|
Revision 1.76 2000/01/07 01:14:30 peter
|
|
* updated copyright to 2000
|
|
|
|
Revision 1.75 1999/12/30 17:56:44 peter
|
|
* fixed and;jmp being translated into test;jmp
|
|
|
|
Revision 1.74 1999/12/05 16:48:43 jonas
|
|
* CSE of constant loading in regs works properly again
|
|
+ if a constant is stored into memory using "mov const, ref" and
|
|
there is a reg that contains this const, it is changed into
|
|
"mov reg, ref"
|
|
|
|
Revision 1.73 1999/12/02 11:26:41 peter
|
|
* newoptimizations define added
|
|
|
|
Revision 1.72 1999/11/30 10:40:45 peter
|
|
+ ttype, tsymlist
|
|
|
|
Revision 1.71 1999/11/27 23:47:55 jonas
|
|
+ change "mov var,reg; add/shr/... x,reg; mov reg,var" to
|
|
"add/shr/... x,var" (if x is a const or reg, suggestion from Peter)
|
|
Enable with -dfoldArithOps
|
|
|
|
Revision 1.70 1999/11/21 13:09:41 jonas
|
|
* fixed some missed optimizations because 8bit regs were not always
|
|
taken into account
|
|
|
|
Revision 1.69 1999/11/13 19:03:56 jonas
|
|
* don't remove align objects between JMP's and labels
|
|
|
|
Revision 1.68 1999/11/06 16:24:00 jonas
|
|
* getfinaldestination works completely again (a lot of functionality
|
|
got lost in the conversion resulting from the removal of
|
|
ait_labeled_instruction)
|
|
|
|
Revision 1.67 1999/11/06 14:34:23 peter
|
|
* truncated log to 20 revs
|
|
|
|
Revision 1.66 1999/09/27 23:44:55 peter
|
|
* procinfo is now a pointer
|
|
* support for result setting in sub procedure
|
|
|
|
Revision 1.65 1999/09/05 14:27:19 florian
|
|
+ fld reg;fxxx to fxxxr reg optimization
|
|
|
|
Revision 1.64 1999/08/25 12:00:02 jonas
|
|
* changed pai386, paippc and paiapha (same for tai*) to paicpu (taicpu)
|
|
|
|
Revision 1.63 1999/08/23 10:20:46 jonas
|
|
* fixed pop/push optmization
|
|
|
|
Revision 1.62 1999/08/10 12:30:00 pierre
|
|
* avoid unused locals
|
|
|
|
Revision 1.61 1999/08/05 15:02:48 jonas
|
|
* "add/sub const,%esp;sub $2,%esp" wasn't always optimized
|
|
|
|
Revision 1.60 1999/08/04 00:23:16 florian
|
|
* renamed i386asm and i386base to cpuasm and cpubase
|
|
|
|
Revision 1.59 1999/08/03 17:13:28 jonas
|
|
* fix for sar/shr-shl optimization
|
|
|
|
Revision 1.58 1999/07/30 18:17:55 jonas
|
|
* fix so (,reg) gets optimized to (reg)
|
|
|
|
Revision 1.57 1999/07/01 18:12:16 jonas
|
|
* enabled "mov reg1,reg2;mov (reg2,..), reg2" also if the second mov is
|
|
a movzx or movsx
|
|
|
|
Revision 1.56 1999/06/23 12:33:52 jonas
|
|
* merged
|
|
|
|
Revision 1.54.2.2 1999/06/23 11:55:08 jonas
|
|
* fixed bug in "mov mem1,reg1;mov reg1,mem2;mov mem2,reg2" optimization
|
|
|
|
Revision 1.55 1999/06/18 09:55:31 peter
|
|
* merged
|
|
|
|
Revision 1.54.2.1 1999/06/18 09:52:40 peter
|
|
* pop;push -> mov (esp),reg always instead of being removed
|
|
|
|
Revision 1.54 1999/05/27 19:44:49 peter
|
|
* removed oldasm
|
|
* plabel -> pasmlabel
|
|
* -a switches to source writing automaticly
|
|
* assembler readers OOPed
|
|
* asmsymbol automaticly external
|
|
* jumptables and other label fixes for asm readers
|
|
|
|
Revision 1.53 1999/05/12 00:19:52 peter
|
|
* removed R_DEFAULT_SEG
|
|
* uniform float names
|
|
|
|
Revision 1.52 1999/05/05 16:19:04 jonas
|
|
+ remove the segment prefixes from LEA instructions
|
|
|
|
Revision 1.51 1999/05/05 10:05:54 florian
|
|
* a delphi compiled compiler recompiles ppc
|
|
|
|
Revision 1.50 1999/05/02 21:33:55 florian
|
|
* several bugs regarding -Or fixed
|
|
|
|
Revision 1.49 1999/05/02 14:26:31 peter
|
|
* fixed dec -> sub $1 opt which didn't set ops=2
|
|
|
|
} |