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f3fc72095f
* merged isconvertable and is_equal into compare_defs(_ext) * made operator search faster by walking the list only once
481 lines
19 KiB
ObjectPascal
481 lines
19 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate generic mathematical nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncgmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,cpubase,cgbase,cginfo;
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type
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tcgunaryminusnode = class(tunaryminusnode)
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procedure pass_2;override;
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protected
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{ This routine is called to change the sign of the
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floating point value in the floating point
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register r.
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This routine should be overriden, since
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the generic version is not optimal at all. The
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generic version assumes that floating
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point values are stored in the register
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in IEEE-754 format.
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}
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procedure emit_float_sign_change(r: tregister; _size : tcgsize);virtual;
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end;
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tcgmoddivnode = class(tmoddivnode)
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procedure pass_2;override;
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protected
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{ This routine must do an actual 32-bit division, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the division must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a divide.
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}
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procedure emit_div_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
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{ This routine must do an actual 32-bit modulo, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the modulo must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a modulo.
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}
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procedure emit_mod_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
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{ This routine must do an actual 64-bit division, be it
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signed or unsigned. The result must set into the the
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@var(num) register.
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@param(signed Indicates if the division must be signed)
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@param(denum Register containing the denominator
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@param(num Register containing the numerator, will also receive result)
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The actual optimizations regarding shifts have already
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been done and emitted, so this should really a do a divide.
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Currently, this routine should only be implemented on
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64-bit systems, otherwise a helper is called in 1st pass.
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}
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procedure emit64_div_reg_reg(signed: boolean;denum,num : tregister64);virtual;
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end;
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tcgshlshrnode = class(tshlshrnode)
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procedure pass_2;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,aasmbase,aasmtai,aasmcpu,defutil,
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pass_1,pass_2,
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ncon,
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cpuinfo,
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tgobj,ncgutil,cgobj,rgobj,rgcpu,paramgr,cg64f32;
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{*****************************************************************************
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TCGUNARYMINUSNODE
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*****************************************************************************}
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procedure tcgunaryminusnode.emit_float_sign_change(r: tregister; _size : tcgsize);
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var
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href : treference;
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hreg : tregister;
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begin
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{ get a temporary memory reference to store the floating
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point value
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}
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tg.gettemp(exprasmlist,tcgsize2size[_size],tt_normal,href);
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{ store the floating point value in the temporary memory area }
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cg.a_loadfpu_reg_ref(exprasmlist,_size,r,href);
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{ only single and double ieee are supported }
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if _size = OS_F64 then
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begin
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{ on little-endian machine the most significant
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32-bit value is stored at the highest address
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}
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if target_info.endian = endian_little then
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inc(href.offset,4);
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end
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else
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if _size <> OS_F32 then
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internalerror(20020814);
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hreg := rg.getregisterint(exprasmlist);
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{ load value }
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cg.a_load_ref_reg(exprasmlist,OS_32,href,hreg);
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{ bitwise complement copied value }
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cg.a_op_reg_reg(exprasmlist,OP_NOT,OS_32,hreg,hreg);
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{ sign-bit is bit 31/63 of single/double }
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cg.a_op_const_reg(exprasmlist,OP_AND,$80000000,hreg);
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{ or with value in reference memory }
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cg.a_op_reg_ref(exprasmlist,OP_OR,OS_32,hreg,href);
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rg.ungetregister(exprasmlist,hreg);
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{ store the floating point value in the temporary memory area }
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if _size = OS_F64 then
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begin
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{ on little-endian machine the most significant
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32-bit value is stored at the highest address
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}
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if target_info.endian = endian_little then
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dec(href.offset,4);
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end;
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cg.a_loadfpu_ref_reg(exprasmlist,_size,href,r);
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end;
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procedure tcgunaryminusnode.pass_2;
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begin
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if is_64bitint(left.resulttype.def) then
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begin
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secondpass(left);
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{ load left operator in a register }
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location_copy(location,left.location);
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location_force_reg(exprasmlist,location,OS_64,false);
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cg64.a_op64_loc_reg(exprasmlist,OP_NEG,
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location,joinreg64(location.registerlow,location.registerhigh));
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end
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else
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begin
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secondpass(left);
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location_reset(location,LOC_REGISTER,OS_INT);
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case left.location.loc of
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LOC_REGISTER:
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begin
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location.register:=left.location.register;
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cg.a_op_reg_reg(exprasmlist,OP_NEG,OS_INT,location.register,
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location.register);
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end;
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LOC_CREGISTER:
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begin
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location.register:=rg.getregisterint(exprasmlist);
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,left.location.register,
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location.register);
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cg.a_op_reg_reg(exprasmlist,OP_NEG,OS_INT,location.register,
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location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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reference_release(exprasmlist,left.location.reference);
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if (left.resulttype.def.deftype=floatdef) then
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
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location.register:=rg.getregisterfpu(exprasmlist);
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cg.a_loadfpu_ref_reg(exprasmlist,
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def_cgsize(left.resulttype.def),
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left.location.reference,location.register);
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emit_float_sign_change(location.register,def_cgsize(left.resulttype.def));
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end
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else
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begin
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location.register:=rg.getregisterint(exprasmlist);
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{ why is the size is OS_INT, since in pass_1 we convert
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everything to a signed natural value anyways
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}
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cg.a_load_ref_reg(exprasmlist,OS_INT,
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left.location.reference,location.register);
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cg.a_op_reg_reg(exprasmlist,OP_NEG,OS_INT,location.register,
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location.register);
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end;
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end;
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LOC_FPUREGISTER:
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
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location.register:=left.location.register;
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emit_float_sign_change(location.register,def_cgsize(left.resulttype.def));
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end;
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LOC_CFPUREGISTER:
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
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location.register:=rg.getregisterfpu(exprasmlist);
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cg.a_loadfpu_reg_reg(exprasmlist,left.location.register,location.register);
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emit_float_sign_change(location.register,def_cgsize(left.resulttype.def));
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end;
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else
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internalerror(200203225);
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end;
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end;
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end;
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{*****************************************************************************
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TCGMODDIVNODE
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*****************************************************************************}
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procedure tcgmoddivnode.emit64_div_reg_reg(signed: boolean; denum,num:tregister64);
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begin
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{ handled in pass_1 already, unless pass_1 is
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overriden
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}
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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end;
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procedure tcgmoddivnode.pass_2;
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var
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hreg1 : tregister;
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hdenom,hnumerator : tregister;
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shrdiv,popeax,popedx : boolean;
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power : longint;
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hl : tasmlabel;
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pushedregs : tmaybesave;
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begin
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shrdiv := false;
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secondpass(left);
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if codegenerror then
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exit;
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maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
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secondpass(right);
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maybe_restore(exprasmlist,left.location,pushedregs);
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if codegenerror then
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exit;
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location_copy(location,left.location);
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if is_64bitint(resulttype.def) then
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begin
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{ this code valid for 64-bit cpu's only ,
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otherwise helpers are called in pass_1
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}
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location_force_reg(exprasmlist,location,OS_64,false);
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location_copy(location,left.location);
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location_force_reg(exprasmlist,right.location,OS_64,false);
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emit64_div_reg_reg(is_signed(left.resulttype.def),
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joinreg64(right.location.registerlow,right.location.registerhigh),
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joinreg64(location.registerlow,location.registerhigh));
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end
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else
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begin
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{ put numerator in register }
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location_force_reg(exprasmlist,left.location,OS_INT,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and
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(right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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Begin
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shrdiv := true;
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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If is_signed(left.resulttype.def) Then
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Begin
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objectlibrary.getlabel(hl);
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cg.a_cmp_const_reg_label(exprasmlist,OS_INT,OC_GT,0,hreg1,hl);
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if power=1 then
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cg.a_op_const_reg(exprasmlist,OP_ADD,1,hreg1)
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else
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cg.a_op_const_reg(exprasmlist,OP_ADD,
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tordconstnode(right).value-1,hreg1);
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cg.a_label(exprasmlist,hl);
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cg.a_op_const_reg(exprasmlist,OP_SAR,power,hreg1);
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End
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Else { not signed }
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Begin
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cg.a_op_const_reg(exprasmlist,OP_SHR,power,hreg1);
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end;
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End
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else
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begin
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{ bring denominator to hdenom }
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{ hdenom is always free, it's }
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{ only used for temporary }
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{ purposes }
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hdenom := rg.getregisterint(exprasmlist);
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if right.location.loc<>LOC_CREGISTER then
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location_release(exprasmlist,right.location);
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cg.a_load_loc_reg(exprasmlist,right.location,hdenom);
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{ verify if the divisor is zero, if so return an error
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immediately
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}
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objectlibrary.getlabel(hl);
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cg.a_cmp_const_reg_label(exprasmlist,OS_INT,OC_NE,0,hdenom,hl);
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cg.a_param_const(exprasmlist,OS_S32,200,paramanager.getintparaloc(1));
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cg.a_call_name(exprasmlist,'FPC_HANDLERROR');
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cg.a_label(exprasmlist,hl);
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if nodetype = modn then
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emit_mod_reg_reg(is_signed(left.resulttype.def),hdenom,hreg1)
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else
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emit_div_reg_reg(is_signed(left.resulttype.def),hdenom,hreg1);
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end;
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location_reset(location,LOC_REGISTER,OS_INT);
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location.register:=hreg1;
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end;
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cg.g_overflowcheck(exprasmlist,self);
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end;
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{*****************************************************************************
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TCGSHLRSHRNODE
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*****************************************************************************}
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procedure tcgshlshrnode.pass_2;
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var
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hcountreg : tregister;
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op : topcg;
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l1,l2,l3 : tasmlabel;
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pushedregs : tmaybesave;
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freescratch : boolean;
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begin
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freescratch:=false;
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secondpass(left);
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maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
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secondpass(right);
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maybe_restore(exprasmlist,left.location,pushedregs);
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{ determine operator }
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case nodetype of
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shln: op:=OP_SHL;
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shrn: op:=OP_SHR;
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end;
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if is_64bitint(left.resulttype.def) then
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begin
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{ already hanled in 1st pass }
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internalerror(2002081501);
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(* Normally for 64-bit cpu's this here should be here,
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and only pass_1 need to be overriden, but dunno how to
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do that!
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location_reset(location,LOC_REGISTER,OS_64);
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{ load left operator in a register }
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location_force_reg(exprasmlist,left.location,OS_64,false);
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location_copy(location,left.location);
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if (right.nodetype=ordconstn) then
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begin
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cg64.a_op64_const_reg(exprasmlist,op,tordconstnode(right).value,
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joinreg64(location.registerlow,location.registerhigh));
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end
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else
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begin
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{ this should be handled in pass_1 }
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internalerror(2002081501);
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if right.location.loc<>LOC_REGISTER then
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begin
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if right.location.loc<>LOC_CREGISTER then
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location_release(exprasmlist,right.location);
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hcountreg:=cg.get_scratch_reg_int(exprasmlist);
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cg.a_load_loc_reg(exprasmlist,right.location,hcountreg);
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freescratch := true;
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end
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else
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hcountreg:=right.location.register;
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cg64.a_op64_reg_reg(exprasmlist,op,hcountreg,
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joinreg64(location.registerlow,location.registerhigh));
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if freescratch then
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cg.free_scratch_reg(exprasmlist,hcountreg);
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end;*)
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end
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else
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begin
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{ load left operators in a register }
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location_copy(location,left.location);
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location_force_reg(exprasmlist,location,OS_INT,false);
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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{ l shl 32 should 0 imho, but neither TP nor Delphi do it in this way (FK)
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if right.value<=31 then
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}
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cg.a_op_const_reg(exprasmlist,op,tordconstnode(right).value and 31,
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location.register);
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{
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else
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emit_reg_reg(A_XOR,S_L,hregister1,
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hregister1);
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}
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end
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else
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begin
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{ load right operators in a register - this
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is done since most target cpu which will use this
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node do not support a shift count in a mem. location (cec)
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}
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if right.location.loc<>LOC_REGISTER then
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begin
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if right.location.loc<>LOC_CREGISTER then
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location_release(exprasmlist,right.location);
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hcountreg:=cg.get_scratch_reg_int(exprasmlist);
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freescratch := true;
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cg.a_load_loc_reg(exprasmlist,right.location,hcountreg);
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end
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else
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hcountreg:=right.location.register;
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cg.a_op_reg_reg(exprasmlist,op,OS_INT,hcountreg,location.register);
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if freescratch then
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cg.free_scratch_reg(exprasmlist,hcountreg);
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end;
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end;
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end;
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begin
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cmoddivnode:=tcgmoddivnode;
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cunaryminusnode:=tcgunaryminusnode;
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cshlshrnode:=tcgshlshrnode;
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end.
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{
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$Log$
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Revision 1.5 2002-11-25 17:43:18 peter
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* splitted defbase in defutil,symutil,defcmp
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* merged isconvertable and is_equal into compare_defs(_ext)
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* made operator search faster by walking the list only once
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Revision 1.4 2002/09/17 18:54:02 jonas
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* a_load_reg_reg() now has two size parameters: source and dest. This
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allows some optimizations on architectures that don't encode the
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register size in the register name.
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Revision 1.3 2002/08/23 16:14:48 peter
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* tempgen cleanup
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* tt_noreuse temp type added that will be used in genentrycode
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Revision 1.2 2002/08/15 15:15:55 carl
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* jmpbuf size allocation for exceptions is now cpu specific (as it should)
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* more generic nodes for maths
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* several fixes for better m68k support
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Revision 1.1 2002/08/14 19:26:55 carl
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+ generic int_to_real type conversion
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+ generic unaryminus node
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}
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