fpc/compiler/mips
2013-12-11 10:56:07 +00:00
..
aasmcpu.pas * MIPS: emit PIC-friendly instruction sequences instead of "J" when fixing up branches outside of 128K range. Resolves #25399. 2013-12-11 10:56:07 +00:00
aoptcpu.pas + MIPS peephole optimizer: eliminate redundant moves of floating point registers. 2013-11-25 13:57:19 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas * MIPS: don't optimize reference twice for 64-bit loads and stores. Now loading/storing 64-bit value to global variable takes typically 3 instructions. 2013-11-25 14:27:35 +00:00
cpubase.pas
cpuelf.pas
cpugas.pas
cpuinfo.pas
cpunode.pas
cpupara.pas
cpupi.pas
cputarg.pas
hlcgcpu.pas
itcpugas.pas
mipsreg.dat
ncpuadd.pas * Function tjvmaddnode.cmpnode2topcmp is, in fact, not specific to any target. Moved it to generic tcgaddnode and reused in tmipsaddnode, where the same functionality was implemented in different way. 2013-11-28 11:52:47 +00:00
ncpucall.pas
ncpucnv.pas
ncpuinln.pas
ncpuld.pas
ncpumat.pas * MIPS: removed specific handling of 32-bit shifts, generic code does the job just well. 2013-11-27 11:33:52 +00:00
ncpuset.pas
opcode.inc
racpugas.pas
rgcpu.pas
rmipscon.inc
rmipsdwf.inc
rmipsgas.inc
rmipsgri.inc
rmipsgss.inc
rmipsnor.inc
rmipsnum.inc
rmipsrni.inc
rmipssri.inc
rmipssta.inc
rmipsstd.inc
rmipssup.inc
strinst.inc