mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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402 lines
15 KiB
ObjectPascal
402 lines
15 KiB
ObjectPascal
{
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Copyright (c) 2000-2006 by Florian Klaempfl and Jonas Maebe
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Code generation for add nodes on the LoongArch64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpuadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,nadd,ncgadd,cpubase;
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type
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tloongarch64addnode = class(tcgaddnode)
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private
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procedure Cmp(signed,is_smallset: boolean);
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protected
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procedure second_cmpsmallset;override;
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procedure second_cmpordinal;override;
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procedure second_cmp64bit; override;
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procedure second_addordinal; override;
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procedure second_add64bit; override;
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procedure pass_left_and_right;
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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public
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function use_generic_mul32to64: boolean; override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,
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aasmbase,aasmtai,aasmdata,aasmcpu,defutil,htypechk,
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cgbase,cpuinfo,pass_1,pass_2,
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cpupara,cgcpu,cgutils,procinfo,
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ncon,nset,
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ncgutil,tgobj,rgobj,rgcpu,cgobj,hlcgobj;
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procedure tloongarch64addnode.Cmp(signed,is_smallset: boolean);
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var
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flabel,tlabel: tasmlabel;
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op, opi: TAsmOp;
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allow_constant : boolean;
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begin
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pass_left_right;
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allow_constant:=(not is_smallset) or not (nodetype in [lten,gten]);
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force_reg_left_right(true,allow_constant);
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if nf_swapped in flags then
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swapleftright;
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location_reset(location,LOC_REGISTER,OS_INT);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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if signed then op:=A_SLT else op:=A_SLTU;
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if signed then opi:=A_SLTI else opi:=A_SLTUI;
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case nodetype of
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equaln:
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begin
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if not (left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if (right.location.loc=LOC_CONSTANT) and
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(not is_uimm12(right.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if right.location.loc=LOC_CONSTANT then
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if right.location.value = 0 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,left.location.register,location.register)
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_XORI,location.register,left.location.register,right.location.value))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_XOR,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTUI,location.register,location.register,1));
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end;
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unequaln:
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begin
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if not (left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if (right.location.loc=LOC_CONSTANT) and
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(not is_uimm12(right.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if right.location.loc=LOC_CONSTANT then
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if right.location.value = 0 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,left.location.register,location.register)
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_XORI,location.register,left.location.register,right.location.value))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_XOR,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_SLTU,location.register,NR_R0,location.register));
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end;
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ltn:
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begin
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if not (left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if (right.location.loc=LOC_CONSTANT) and
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(not is_simm12(right.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if right.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,left.location.register,right.location.value))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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end;
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gtn:
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begin
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if not (right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if (left.location.loc=LOC_CONSTANT) and
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(not is_simm12(left.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if left.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,right.location.register,left.location.value))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,right.location.register,left.location.register));
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end;
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lten:
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begin
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if not (right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if (left.location.loc=LOC_CONSTANT) and
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(not is_simm12(left.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if is_smallset then
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begin
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_ANDN,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTUI,location.register,location.register,1));
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end
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else
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begin
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if left.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,right.location.register,left.location.value))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,right.location.register,left.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_XORI,location.register,location.register,1));
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end;
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end;
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gten:
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begin
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if not (left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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if (right.location.loc=LOC_CONSTANT) and
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(not is_simm12(right.location.value)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
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if is_smallset then
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begin
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_ANDN,location.register,right.location.register,left.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_SLTUI,location.register,location.register,1));
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end
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else
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begin
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if right.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(opi,location.register,left.location.register,right.location.value))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_const(A_XORI,location.register,location.register,1));
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end;
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end;
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else
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Internalerror(2022111946);
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end;
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end;
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{ Smallset means the one all bits in another one. }
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procedure tloongarch64addnode.second_cmpsmallset;
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begin
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Cmp(false,true);
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end;
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procedure tloongarch64addnode.second_cmpordinal;
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var
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unsigned: Boolean;
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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Cmp(not unsigned,false);
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end;
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procedure tloongarch64addnode.second_cmp64bit;
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var
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unsigned: Boolean;
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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Cmp(not unsigned,false);
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end;
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procedure tloongarch64addnode.second_addordinal;
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const
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multops: array[boolean] of TAsmOp = (A_MULW_D_W,A_MULW_D_WU);
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var
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unsigned: boolean;
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begin
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{ 32x32->64 multiplication }
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if (nodetype=muln) and
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is_32bit(left.resultdef) and
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is_32bit(right.resultdef) and
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is_64bit(resultdef) then
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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pass_left_right;
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force_reg_left_right(true,true);
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{ force_reg_left_right can leave right as a LOC_CONSTANT (we can't
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say "a constant register is okay, but an ordinal constant isn't) }
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if right.location.loc=LOC_CONSTANT then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(multops[unsigned],location.register,left.location.register,right.location.register));
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end
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else
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inherited second_addordinal;
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end;
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procedure tloongarch64addnode.second_add64bit;
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begin
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second_addordinal;
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end;
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procedure tloongarch64addnode.pass_left_and_right;
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begin
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{ calculate the operator which is more difficult }
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firstcomplex(self);
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{ in case of constant put it to the left }
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if (left.nodetype=ordconstn) then
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swapleftright;
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secondpass(left);
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secondpass(right);
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end;
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procedure tloongarch64addnode.second_addfloat;
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var
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op : TAsmOp;
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cmpop,
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singleprec: boolean;
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begin
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pass_left_and_right;
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if (nf_swapped in flags) then
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swapleftright;
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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cmpop:=false;
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singleprec:=tfloatdef(left.resultdef).floattype=s32real;
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case nodetype of
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addn :
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if singleprec then
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op:=A_FADD_S
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else
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op:=A_FADD_D;
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muln :
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if singleprec then
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op:=A_FMUL_S
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else
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op:=A_FMUL_D;
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subn :
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if singleprec then
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op:=A_FSUB_S
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else
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op:=A_FSUB_D;
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slashn :
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if singleprec then
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op:=A_FDIV_S
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else
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op:=A_FDIV_D;
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equaln:
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begin
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if singleprec then
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op:=A_FCMP_CEQ_S
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else
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op:=A_FCMP_CEQ_D;
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cmpop:=true;
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end;
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unequaln:
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begin
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if singleprec then
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op:=A_FCMP_CUNE_S
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else
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op:=A_FCMP_CUNE_D;
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cmpop:=true;
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end;
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ltn:
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begin
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if singleprec then
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op:=A_FCMP_SLT_S
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else
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op:=A_FCMP_SLT_D;
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cmpop:=true;
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end;
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lten:
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begin
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if singleprec then
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op:=A_FCMP_SLE_S
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else
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op:=A_FCMP_SLE_D;
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cmpop:=true;
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end;
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gtn:
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begin
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if singleprec then
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op:=A_FCMP_SGT_S
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else
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op:=A_FCMP_SGT_D;
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cmpop:=true;
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end;
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gten:
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begin
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if singleprec then
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op:=A_FCMP_SGE_S
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else
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op:=A_FCMP_SGE_D;
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cmpop:=true;
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end;
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else
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internalerror(2022111947);
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end;
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if cmpop then
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begin
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{ TODO This should be like mips, but... }
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{ location_reset(location, LOC_FLAGS, OS_NO); }
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{ location.register := cg.getfpuregister(current_asmdata.CurrAsmList,location.size); }
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location_reset(location,LOC_REGISTER,OS_8);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,NR_FCC0,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_MOVCF2GR,location.register,NR_FCC0));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end
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else
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begin
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location_reset(location, LOC_FPUREGISTER, def_cgsize(resultdef));
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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end;
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procedure tloongarch64addnode.second_cmpfloat;
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begin
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second_addfloat;
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end;
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function tloongarch64addnode.use_generic_mul32to64: boolean;
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begin
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result:=false;
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end;
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begin
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caddnode := tloongarch64addnode;
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end.
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