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515774b864
-- Zusammenführen der Unterschiede zwischen Projektarchiv-URLs in ».«: U rtl/arm/setjump.inc A rtl/arm/thumb2.inc U rtl/arm/divide.inc A rtl/embedded/arm/stm32f103.pp U rtl/inc/system.inc U compiler/alpha/cgcpu.pas U compiler/sparc/cgcpu.pas U compiler/i386/cgcpu.pas U compiler/ncgld.pas U compiler/powerpc/cgcpu.pas U compiler/avr/cgcpu.pas U compiler/aggas.pas U compiler/powerpc64/cgcpu.pas U compiler/x86_64/cgcpu.pas U compiler/cgobj.pas U compiler/psystem.pas U compiler/aasmtai.pas U compiler/m68k/cgcpu.pas U compiler/ncgutil.pas U compiler/rautils.pas U compiler/arm/raarmgas.pas U compiler/arm/armatts.inc U compiler/arm/cgcpu.pas U compiler/arm/armins.dat U compiler/arm/rgcpu.pas U compiler/arm/cpubase.pas U compiler/arm/agarmgas.pas U compiler/arm/cpuinfo.pas U compiler/arm/armop.inc U compiler/arm/narmadd.pas U compiler/arm/aoptcpu.pas U compiler/arm/armatt.inc U compiler/arm/aasmcpu.pas U compiler/systems/t_embed.pas U compiler/psub.pas U compiler/options.pas git-svn-id: trunk@13801 -
359 lines
12 KiB
ObjectPascal
359 lines
12 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the ARM
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgadd,cpubase;
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type
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tarmaddnode = class(tcgaddnode)
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private
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function GetResFlags(unsigned:Boolean):TResFlags;
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protected
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function pass_1 : tnode;override;
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpordinal;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,
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aasmbase,aasmtai,aasmdata,aasmcpu,defutil,htypechk,
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cgbase,cgutils,cgcpu,
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cpuinfo,pass_1,pass_2,regvars,procinfo,
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cpupara,
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ncon,nset,nadd,
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ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32;
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{*****************************************************************************
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TSparcAddNode
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*****************************************************************************}
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function tarmaddnode.GetResFlags(unsigned:Boolean):TResFlags;
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begin
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case NodeType of
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equaln:
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GetResFlags:=F_EQ;
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unequaln:
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GetResFlags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case NodeType of
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ltn:
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GetResFlags:=F_GT;
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lten:
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GetResFlags:=F_GE;
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gtn:
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GetResFlags:=F_LT;
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gten:
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GetResFlags:=F_LE;
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LT;
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lten:
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GetResFlags:=F_LE;
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gtn:
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GetResFlags:=F_GT;
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gten:
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GetResFlags:=F_GE;
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end;
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end
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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GetResFlags:=F_HI;
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lten:
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GetResFlags:=F_CS;
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gtn:
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GetResFlags:=F_CC;
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gten:
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GetResFlags:=F_LS;
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_CC;
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lten:
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GetResFlags:=F_LS;
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gtn:
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GetResFlags:=F_HI;
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gten:
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GetResFlags:=F_CS;
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end;
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end;
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end;
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end;
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procedure tarmaddnode.second_addfloat;
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var
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op : TAsmOp;
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begin
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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case nodetype of
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addn :
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op:=A_ADF;
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muln :
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op:=A_MUF;
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subn :
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op:=A_SUF;
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slashn :
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op:=A_DVF;
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else
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internalerror(200308313);
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end;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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location_force_fpureg(current_asmdata.CurrAsmList,left.location,true);
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location_force_fpureg(current_asmdata.CurrAsmList,right.location,(left.location.loc<>LOC_CFPUREGISTER));
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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if left.location.loc<>LOC_CFPUREGISTER then
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location.register:=left.location.register
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else
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location.register:=right.location.register;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op,
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location.register,left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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location.loc:=LOC_FPUREGISTER;
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end;
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fpu_soft:
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{ this case should be handled already by pass1 }
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internalerror(200308252);
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else
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internalerror(200308251);
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end;
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end;
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procedure tarmaddnode.second_cmpfloat;
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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location_force_fpureg(current_asmdata.CurrAsmList,left.location,true);
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location_force_fpureg(current_asmdata.CurrAsmList,right.location,true);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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if nodetype in [equaln,unequaln] then
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_CMF,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]))
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else
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_CMFE,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(false);
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end;
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procedure tarmaddnode.second_cmpsmallset;
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var
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tmpreg : tregister;
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begin
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pass_left_right;
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location_reset(location,LOC_FLAGS,OS_NO);
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force_reg_left_right(false,false);
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case nodetype of
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equaln:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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location.resflags:=F_EQ;
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end;
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unequaln:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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location.resflags:=F_NE;
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end;
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lten,
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gten:
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begin
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if (not(nf_swapped in flags) and
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(nodetype = lten)) or
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((nf_swapped in flags) and
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(nodetype = gten)) then
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swapleftright;
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_AND,tmpreg,left.location.register,right.location.register));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,tmpreg,right.location.register));
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2004012401);
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end;
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end;
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procedure tarmaddnode.second_cmp64bit;
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var
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unsigned : boolean;
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oldnodetype : tnodetype;
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begin
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pass_left_right;
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force_reg_left_right(false,false);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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{ operation requiring proper N, Z and C flags ? }
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if unsigned or (nodetype in [equaln,unequaln]) then
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi));
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if current_settings.cputype in cpu_thumb2 then
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current_asmdata.CurrAsmList.concat(taicpu.op_cond(A_IT, C_EQ));
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current_asmdata.CurrAsmList.concat(setcondition(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo),C_EQ));
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end
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else
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{ operation requiring proper N, Z and V flags ? }
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begin
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location_reset(location,LOC_JUMP,OS_NO);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi));
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{ the jump the sequence is a little bit hairy }
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case nodetype of
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ltn,gtn:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(false),current_procinfo.CurrTrueLabel);
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{ cheat a little bit for the negative test }
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toggleflag(nf_swapped);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(false),current_procinfo.CurrFalseLabel);
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toggleflag(nf_swapped);
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end;
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lten,gten:
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begin
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oldnodetype:=nodetype;
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if nodetype=lten then
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nodetype:=ltn
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else
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nodetype:=gtn;
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),current_procinfo.CurrTrueLabel);
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{ cheat for the negative test }
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if nodetype=ltn then
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nodetype:=gtn
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else
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nodetype:=ltn;
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),current_procinfo.CurrFalseLabel);
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nodetype:=oldnodetype;
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end;
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
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{ the comparisaion of the low dword have to be
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always unsigned! }
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),current_procinfo.CurrTrueLabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,current_procinfo.CurrFalseLabel);
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end;
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end;
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function tarmaddnode.pass_1 : tnode;
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var
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unsigned : boolean;
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begin
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result:=inherited pass_1;
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if not(assigned(result)) then
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if is_64bit(left.resultdef) and
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((nodetype in [equaln,unequaln]) or
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(unsigned and (nodetype in [ltn,lten,gtn,gten]))
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) then
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expectloc:=LOC_FLAGS;
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end;
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end;
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procedure tarmaddnode.second_cmpordinal;
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var
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unsigned : boolean;
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tmpreg : tregister;
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b : byte;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if right.location.loc = LOC_CONSTANT then
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begin
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if is_shifter_const(right.location.value,b) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,right.location.value))
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else
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begin
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,
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right.location.value,tmpreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,tmpreg));
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end;
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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end;
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begin
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caddnode:=tarmaddnode;
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end.
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