mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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65c3ba277c
ungetcpuregister * renamed (get|unget)explicitregister(s) to ..cpuregister * removed location-release/reference_release
940 lines
33 KiB
ObjectPascal
940 lines
33 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 2000-2002 by Florian Klaempfl
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Common code generation for add nodes on the i386 and x86
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx86add;
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{$i fpcdefs.inc}
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interface
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uses
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cgbase,
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cpubase,
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node,nadd,ncgadd;
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type
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tx86addnode = class(tcgaddnode)
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protected
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function getresflags(unsigned : boolean) : tresflags;
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procedure left_must_be_reg(opsize:TCGSize;noswap:boolean);
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procedure left_and_right_must_be_fpureg;
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procedure emit_op_right_left(op:TAsmOp;opsize:TCgSize);
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procedure emit_generic_code(op:TAsmOp;opsize:TCgSize;unsigned,extra_not,mboverflow:boolean);
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procedure second_cmpfloatsse;
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procedure second_addfloatsse;
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procedure second_mul;virtual;abstract;
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public
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{$ifdef i386}
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function first_addstring : tnode; override;
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procedure second_addstring;override;
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{$endif i386}
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procedure second_addfloat;override;
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procedure second_addsmallset;override;
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procedure second_add64bit;override;
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procedure second_addordinal;override;
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procedure second_cmpfloat;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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procedure second_cmpordinal;override;
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end;
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implementation
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uses
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globtype,globals,
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verbose,cutils,
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cpuinfo,
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aasmbase,aasmtai,aasmcpu,
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symconst,symdef,
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cgobj,cgx86,cga,
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paramgr,parabase,
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htypechk,
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pass_2,ncgutil,
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ncon,nset,
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defutil;
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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procedure tx86addnode.emit_generic_code(op:TAsmOp;opsize:TCGSize;unsigned,extra_not,mboverflow:boolean);
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var
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power : longint;
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hl4 : tasmlabel;
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r : Tregister;
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begin
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{ at this point, left.location.loc should be LOC_REGISTER }
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if right.location.loc=LOC_REGISTER then
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begin
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{ right.location is a LOC_REGISTER }
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{ when swapped another result register }
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if (nodetype=subn) and (nf_swaped in flags) then
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begin
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if extra_not then
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emit_reg(A_NOT,TCGSize2Opsize[opsize],left.location.register);
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emit_reg_reg(op,TCGSize2Opsize[opsize],left.location.register,right.location.register);
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{ newly swapped also set swapped flag }
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location_swap(left.location,right.location);
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toggleflag(nf_swaped);
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end
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else
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begin
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if extra_not then
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emit_reg(A_NOT,TCGSize2Opsize[opsize],right.location.register);
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if (op=A_ADD) or (op=A_OR) or (op=A_AND) or (op=A_XOR) or (op=A_IMUL) then
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location_swap(left.location,right.location);
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emit_reg_reg(op,TCGSize2Opsize[opsize],right.location.register,left.location.register);
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end;
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end
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else
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begin
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{ right.location is not a LOC_REGISTER }
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if (nodetype=subn) and (nf_swaped in flags) then
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begin
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if extra_not then
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cg.a_op_reg_reg(exprasmlist,OP_NOT,opsize,left.location.register,left.location.register);
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r:=cg.getintregister(exprasmlist,opsize);
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cg.a_load_loc_reg(exprasmlist,opsize,right.location,r);
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emit_reg_reg(op,TCGSize2Opsize[opsize],left.location.register,r);
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cg.a_load_reg_reg(exprasmlist,opsize,opsize,r,left.location.register);
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end
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else
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begin
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{ Optimizations when right.location is a constant value }
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if (op=A_CMP) and
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(nodetype in [equaln,unequaln]) and
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(right.location.loc=LOC_CONSTANT) and
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(right.location.value=0) then
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begin
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emit_reg_reg(A_TEST,TCGSize2Opsize[opsize],left.location.register,left.location.register);
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end
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else
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if (op=A_ADD) and
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(right.location.loc=LOC_CONSTANT) and
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(right.location.value=1) and
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not(cs_check_overflow in aktlocalswitches) then
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begin
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emit_reg(A_INC,TCGSize2Opsize[opsize],left.location.register);
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end
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else
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if (op=A_SUB) and
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(right.location.loc=LOC_CONSTANT) and
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(right.location.value=1) and
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not(cs_check_overflow in aktlocalswitches) then
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begin
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emit_reg(A_DEC,TCGSize2Opsize[opsize],left.location.register);
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end
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else
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if (op=A_IMUL) and
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(right.location.loc=LOC_CONSTANT) and
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(ispowerof2(int64(right.location.value),power)) and
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not(cs_check_overflow in aktlocalswitches) then
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begin
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emit_const_reg(A_SHL,TCGSize2Opsize[opsize],power,left.location.register);
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end
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else
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begin
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if extra_not then
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begin
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r:=cg.getintregister(exprasmlist,opsize);
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cg.a_load_loc_reg(exprasmlist,opsize,right.location,r);
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emit_reg(A_NOT,TCGSize2Opsize[opsize],r);
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emit_reg_reg(A_AND,TCGSize2Opsize[opsize],r,left.location.register);
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end
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else
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begin
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emit_op_right_left(op,opsize);
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end;
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end;
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end;
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end;
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{ only in case of overflow operations }
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{ produce overflow code }
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{ we must put it here directly, because sign of operation }
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{ is in unsigned VAR!! }
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if mboverflow then
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begin
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if cs_check_overflow in aktlocalswitches then
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begin
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objectlibrary.getlabel(hl4);
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if unsigned then
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cg.a_jmp_flags(exprasmlist,F_AE,hl4)
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else
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cg.a_jmp_flags(exprasmlist,F_NO,hl4);
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cg.a_call_name(exprasmlist,'FPC_OVERFLOW');
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cg.a_label(exprasmlist,hl4);
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end;
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end;
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end;
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procedure tx86addnode.left_must_be_reg(opsize:TCGSize;noswap:boolean);
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begin
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{ left location is not a register? }
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if (left.location.loc<>LOC_REGISTER) then
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begin
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{ if right is register then we can swap the locations }
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if (not noswap) and
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(right.location.loc=LOC_REGISTER) then
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begin
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location_swap(left.location,right.location);
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toggleflag(nf_swaped);
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end
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else
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begin
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{ maybe we can reuse a constant register when the
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operation is a comparison that doesn't change the
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value of the register }
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location_force_reg(exprasmlist,left.location,opsize,(nodetype in [ltn,lten,gtn,gten,equaln,unequaln]));
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end;
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end;
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end;
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procedure tx86addnode.left_and_right_must_be_fpureg;
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begin
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if (right.location.loc<>LOC_FPUREGISTER) then
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begin
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cg.a_loadfpu_loc_reg(exprasmlist,right.location,NR_ST);
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if (right.location.loc <> LOC_CFPUREGISTER) then
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location_freetemp(exprasmlist,left.location);
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if (left.location.loc<>LOC_FPUREGISTER) then
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begin
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cg.a_loadfpu_loc_reg(exprasmlist,left.location,NR_ST);
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if (left.location.loc <> LOC_CFPUREGISTER) then
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location_freetemp(exprasmlist,left.location);
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end
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else
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begin
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{ left was on the stack => swap }
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toggleflag(nf_swaped);
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end;
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end
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{ the nominator in st0 }
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else if (left.location.loc<>LOC_FPUREGISTER) then
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begin
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cg.a_loadfpu_loc_reg(exprasmlist,left.location,NR_ST);
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if (left.location.loc <> LOC_CFPUREGISTER) then
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location_freetemp(exprasmlist,left.location);
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end
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else
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begin
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{ fpu operands are always in the wrong order on the stack }
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toggleflag(nf_swaped);
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end;
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end;
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procedure tx86addnode.emit_op_right_left(op:TAsmOp;opsize:TCgsize);
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{$ifdef x86_64}
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var
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tmpreg : tregister;
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{$endif x86_64}
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begin
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{ left must be a register }
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case right.location.loc of
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LOC_REGISTER,
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LOC_CREGISTER :
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exprasmlist.concat(taicpu.op_reg_reg(op,TCGSize2Opsize[opsize],right.location.register,left.location.register));
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LOC_REFERENCE,
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LOC_CREFERENCE :
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exprasmlist.concat(taicpu.op_ref_reg(op,TCGSize2Opsize[opsize],right.location.reference,left.location.register));
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LOC_CONSTANT :
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begin
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{$ifdef x86_64}
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{ x86_64 only supports signed 32 bits constants directly }
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if (opsize in [OS_S64,OS_64]) and
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((right.location.value<low(longint)) or (right.location.value>high(longint))) then
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begin
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tmpreg:=cg.getintregister(exprasmlist,opsize);
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cg.a_load_const_reg(exprasmlist,opsize,right.location.value,tmpreg);
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exprasmlist.concat(taicpu.op_reg_reg(op,TCGSize2Opsize[opsize],tmpreg,left.location.register));
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end
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else
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{$endif x86_64}
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exprasmlist.concat(taicpu.op_const_reg(op,TCGSize2Opsize[opsize],right.location.value,left.location.register));
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end;
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else
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internalerror(200203232);
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end;
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end;
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function tx86addnode.getresflags(unsigned : boolean) : tresflags;
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begin
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case nodetype of
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equaln : getresflags:=F_E;
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unequaln : getresflags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swaped in flags then
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case nodetype of
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ltn : getresflags:=F_G;
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lten : getresflags:=F_GE;
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gtn : getresflags:=F_L;
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gten : getresflags:=F_LE;
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end
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else
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case nodetype of
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ltn : getresflags:=F_L;
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lten : getresflags:=F_LE;
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gtn : getresflags:=F_G;
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gten : getresflags:=F_GE;
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end;
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end
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else
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begin
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if nf_swaped in flags then
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case nodetype of
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ltn : getresflags:=F_A;
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lten : getresflags:=F_AE;
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gtn : getresflags:=F_B;
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gten : getresflags:=F_BE;
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end
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else
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case nodetype of
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ltn : getresflags:=F_B;
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lten : getresflags:=F_BE;
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gtn : getresflags:=F_A;
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gten : getresflags:=F_AE;
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end;
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end;
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end;
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end;
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{*****************************************************************************
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AddSmallSet
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*****************************************************************************}
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procedure tx86addnode.second_addsmallset;
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var
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opsize : TCGSize;
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op : TAsmOp;
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extra_not,
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noswap : boolean;
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begin
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pass_left_right;
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noswap:=false;
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extra_not:=false;
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opsize:=OS_32;
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case nodetype of
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addn :
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begin
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{ this is a really ugly hack!!!!!!!!!! }
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{ this could be done later using EDI }
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{ as it is done for subn }
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{ instead of two registers!!!! }
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{ adding elements is not commutative }
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if (nf_swaped in flags) and (left.nodetype=setelementn) then
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swapleftright;
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{ are we adding set elements ? }
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if right.nodetype=setelementn then
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begin
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{ no range support for smallsets! }
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if assigned(tsetelementnode(right).right) then
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internalerror(43244);
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{ bts requires both elements to be registers }
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location_force_reg(exprasmlist,left.location,opsize,false);
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location_force_reg(exprasmlist,right.location,opsize,true);
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op:=A_BTS;
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noswap:=true;
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end
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else
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op:=A_OR;
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end;
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symdifn :
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op:=A_XOR;
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muln :
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op:=A_AND;
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subn :
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begin
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op:=A_AND;
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if (not(nf_swaped in flags)) and
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(right.location.loc=LOC_CONSTANT) then
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right.location.value := not(right.location.value)
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else if (nf_swaped in flags) and
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(left.location.loc=LOC_CONSTANT) then
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left.location.value := not(left.location.value)
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else
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extra_not:=true;
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end;
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xorn :
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op:=A_XOR;
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orn :
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op:=A_OR;
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andn :
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op:=A_AND;
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else
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internalerror(2003042215);
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end;
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{ left must be a register }
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left_must_be_reg(opsize,noswap);
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emit_generic_code(op,opsize,true,extra_not,false);
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location_freetemp(exprasmlist,right.location);
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set_result_location_reg;
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end;
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procedure tx86addnode.second_cmpsmallset;
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var
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opsize : TCGSize;
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op : TAsmOp;
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begin
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pass_left_right;
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opsize:=OS_32;
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case nodetype of
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equaln,
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unequaln :
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op:=A_CMP;
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lten,gten:
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begin
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if (not(nf_swaped in flags) and (nodetype = lten)) or
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((nf_swaped in flags) and (nodetype = gten)) then
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swapleftright;
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location_force_reg(exprasmlist,left.location,opsize,true);
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emit_op_right_left(A_AND,opsize);
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op:=A_CMP;
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{ warning: ugly hack, we need a JE so change the node to equaln }
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nodetype:=equaln;
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end;
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else
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internalerror(2003042215);
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end;
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{ left must be a register }
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left_must_be_reg(opsize,false);
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emit_generic_code(op,opsize,true,false,false);
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location_freetemp(exprasmlist,right.location);
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location_freetemp(exprasmlist,left.location);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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end;
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{*****************************************************************************
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AddFloat
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*****************************************************************************}
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procedure tx86addnode.second_addfloatsse;
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var
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op : topcg;
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begin
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pass_left_right;
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if (nf_swaped in flags) then
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swapleftright;
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case nodetype of
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addn :
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op:=OP_ADD;
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muln :
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op:=OP_MUL;
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subn :
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op:=OP_SUB;
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slashn :
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op:=OP_DIV;
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else
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internalerror(200312231);
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end;
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location_reset(location,LOC_MMREGISTER,def_cgsize(resulttype.def));
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{ we can use only right as left operand if the operation is commutative }
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if (right.location.loc=LOC_MMREGISTER) and (op in [OP_ADD,OP_MUL]) then
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begin
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location.register:=right.location.register;
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{ force floating point reg. location to be written to memory,
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we don't force it to mm register because writing to memory
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allows probably shorter code because there is no direct fpu->mm register
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copy instruction
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}
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if left.location.loc in [LOC_FPUREGISTER,LOC_CFPUREGISTER] then
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location_force_mem(exprasmlist,left.location);
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cg.a_opmm_loc_reg(exprasmlist,op,location.size,left.location,location.register,mms_movescalar);
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end
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else
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begin
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location_force_mmregscalar(exprasmlist,left.location,false);
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location.register:=left.location.register;
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{ force floating point reg. location to be written to memory,
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we don't force it to mm register because writing to memory
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allows probably shorter code because there is no direct fpu->mm register
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copy instruction
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}
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if right.location.loc in [LOC_FPUREGISTER,LOC_CFPUREGISTER] then
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location_force_mem(exprasmlist,right.location);
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cg.a_opmm_loc_reg(exprasmlist,op,location.size,right.location,location.register,mms_movescalar);
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end;
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end;
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procedure tx86addnode.second_cmpfloatsse;
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var
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op : tasmop;
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begin
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if is_single(left.resulttype.def) then
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op:=A_COMISS
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else if is_double(left.resulttype.def) then
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op:=A_COMISD
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else
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internalerror(200402222);
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pass_left_right;
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|
|
location_reset(location,LOC_FLAGS,def_cgsize(resulttype.def));
|
|
{ we can use only right as left operand if the operation is commutative }
|
|
if (right.location.loc=LOC_MMREGISTER) then
|
|
begin
|
|
{ force floating point reg. location to be written to memory,
|
|
we don't force it to mm register because writing to memory
|
|
allows probably shorter code because there is no direct fpu->mm register
|
|
copy instruction
|
|
}
|
|
if left.location.loc in [LOC_FPUREGISTER,LOC_CFPUREGISTER] then
|
|
location_force_mem(exprasmlist,left.location);
|
|
case left.location.loc of
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
exprasmlist.concat(taicpu.op_ref_reg(op,S_NO,left.location.reference,right.location.register));
|
|
LOC_MMREGISTER,LOC_CMMREGISTER:
|
|
exprasmlist.concat(taicpu.op_reg_reg(op,S_NO,left.location.register,right.location.register));
|
|
else
|
|
internalerror(200402221);
|
|
end;
|
|
if nf_swaped in flags then
|
|
exclude(flags,nf_swaped)
|
|
else
|
|
include(flags,nf_swaped)
|
|
end
|
|
else
|
|
begin
|
|
location_force_mmregscalar(exprasmlist,left.location,false);
|
|
{ force floating point reg. location to be written to memory,
|
|
we don't force it to mm register because writing to memory
|
|
allows probably shorter code because there is no direct fpu->mm register
|
|
copy instruction
|
|
}
|
|
if right.location.loc in [LOC_FPUREGISTER,LOC_CFPUREGISTER] then
|
|
location_force_mem(exprasmlist,right.location);
|
|
case right.location.loc of
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
exprasmlist.concat(taicpu.op_ref_reg(op,S_NO,right.location.reference,left.location.register));
|
|
LOC_MMREGISTER,LOC_CMMREGISTER:
|
|
exprasmlist.concat(taicpu.op_reg_reg(op,S_NO,right.location.register,left.location.register));
|
|
else
|
|
internalerror(200402223);
|
|
end;
|
|
end;
|
|
location.resflags:=getresflags(true);
|
|
end;
|
|
|
|
|
|
procedure tx86addnode.second_addfloat;
|
|
var
|
|
op : TAsmOp;
|
|
begin
|
|
if use_sse(resulttype.def) then
|
|
begin
|
|
second_addfloatsse;
|
|
exit;
|
|
end;
|
|
|
|
pass_left_right;
|
|
|
|
case nodetype of
|
|
addn :
|
|
op:=A_FADDP;
|
|
muln :
|
|
op:=A_FMULP;
|
|
subn :
|
|
op:=A_FSUBP;
|
|
slashn :
|
|
op:=A_FDIVP;
|
|
else
|
|
internalerror(2003042214);
|
|
end;
|
|
|
|
left_and_right_must_be_fpureg;
|
|
|
|
{ if we swaped the tree nodes, then use the reverse operator }
|
|
if nf_swaped in flags then
|
|
begin
|
|
if (nodetype=slashn) then
|
|
op:=A_FDIVRP
|
|
else if (nodetype=subn) then
|
|
op:=A_FSUBRP;
|
|
end;
|
|
|
|
emit_reg_reg(op,S_NO,NR_ST,NR_ST1);
|
|
tcgx86(cg).dec_fpu_stack;
|
|
|
|
location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
|
|
location.register:=NR_ST;
|
|
end;
|
|
|
|
|
|
procedure tx86addnode.second_cmpfloat;
|
|
var
|
|
resflags : tresflags;
|
|
begin
|
|
if use_sse(left.resulttype.def) or use_sse(right.resulttype.def) then
|
|
begin
|
|
second_cmpfloatsse;
|
|
exit;
|
|
end;
|
|
|
|
pass_left_right;
|
|
left_and_right_must_be_fpureg;
|
|
|
|
{$ifndef x86_64}
|
|
if aktspecificoptprocessor<ClassPentium2 then
|
|
begin
|
|
emit_none(A_FCOMPP,S_NO);
|
|
tcgx86(cg).dec_fpu_stack;
|
|
tcgx86(cg).dec_fpu_stack;
|
|
|
|
{ load fpu flags }
|
|
cg.getcpuregister(exprasmlist,NR_AX);
|
|
emit_reg(A_FNSTSW,S_NO,NR_AX);
|
|
emit_none(A_SAHF,S_NO);
|
|
cg.ungetcpuregister(exprasmlist,NR_AX);
|
|
if nf_swaped in flags then
|
|
begin
|
|
case nodetype of
|
|
equaln : resflags:=F_E;
|
|
unequaln : resflags:=F_NE;
|
|
ltn : resflags:=F_A;
|
|
lten : resflags:=F_AE;
|
|
gtn : resflags:=F_B;
|
|
gten : resflags:=F_BE;
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
case nodetype of
|
|
equaln : resflags:=F_E;
|
|
unequaln : resflags:=F_NE;
|
|
ltn : resflags:=F_B;
|
|
lten : resflags:=F_BE;
|
|
gtn : resflags:=F_A;
|
|
gten : resflags:=F_AE;
|
|
end;
|
|
end;
|
|
end
|
|
else
|
|
{$endif x86_64}
|
|
begin
|
|
exprasmlist.concat(taicpu.op_reg_reg(A_FCOMIP,S_NO,NR_ST1,NR_ST0));
|
|
{ fcomip pops only one fpu register }
|
|
exprasmlist.concat(taicpu.op_reg(A_FSTP,S_NO,NR_ST0));
|
|
tcgx86(cg).dec_fpu_stack;
|
|
tcgx86(cg).dec_fpu_stack;
|
|
|
|
{ load fpu flags }
|
|
if nf_swaped in flags then
|
|
begin
|
|
case nodetype of
|
|
equaln : resflags:=F_E;
|
|
unequaln : resflags:=F_NE;
|
|
ltn : resflags:=F_A;
|
|
lten : resflags:=F_AE;
|
|
gtn : resflags:=F_B;
|
|
gten : resflags:=F_BE;
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
case nodetype of
|
|
equaln : resflags:=F_E;
|
|
unequaln : resflags:=F_NE;
|
|
ltn : resflags:=F_B;
|
|
lten : resflags:=F_BE;
|
|
gtn : resflags:=F_A;
|
|
gten : resflags:=F_AE;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
location.resflags:=resflags;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
Addstring
|
|
*****************************************************************************}
|
|
|
|
{$ifdef i386}
|
|
{ note: if you implemented an fpc_shortstr_concat similar to the }
|
|
{ one in i386.inc, you have to override first_addstring like in }
|
|
{ ti386addnode.first_string and implement the shortstring concat }
|
|
{ manually! The generic routine is different from the i386 one (JM) }
|
|
function tx86addnode.first_addstring : tnode;
|
|
begin
|
|
{ special cases for shortstrings, handled in pass_2 (JM) }
|
|
{ can't handle fpc_shortstr_compare with compilerproc either because it }
|
|
{ returns its results in the flags instead of in eax }
|
|
if (nodetype in [ltn,lten,gtn,gten,equaln,unequaln]) and
|
|
is_shortstring(left.resulttype.def) and
|
|
not(((left.nodetype=stringconstn) and (str_length(left)=0)) or
|
|
((right.nodetype=stringconstn) and (str_length(right)=0))) then
|
|
begin
|
|
expectloc:=LOC_FLAGS;
|
|
calcregisters(self,0,0,0);
|
|
result := nil;
|
|
exit;
|
|
end;
|
|
{ otherwise, use the generic code }
|
|
result := inherited first_addstring;
|
|
end;
|
|
|
|
|
|
procedure tx86addnode.second_addstring;
|
|
var
|
|
paraloc1,
|
|
paraloc2 : tcgpara;
|
|
hregister1,
|
|
hregister2 : tregister;
|
|
begin
|
|
{ string operations are not commutative }
|
|
if nf_swaped in flags then
|
|
swapleftright;
|
|
case tstringdef(left.resulttype.def).string_typ of
|
|
st_shortstring:
|
|
begin
|
|
case nodetype of
|
|
ltn,lten,gtn,gten,equaln,unequaln :
|
|
begin
|
|
paraloc1.init;
|
|
paraloc2.init;
|
|
paramanager.getintparaloc(pocall_default,1,paraloc1);
|
|
paramanager.getintparaloc(pocall_default,2,paraloc2);
|
|
{ process parameters }
|
|
secondpass(left);
|
|
if paraloc2.location^.loc=LOC_REGISTER then
|
|
begin
|
|
hregister2:=cg.getaddressregister(exprasmlist);
|
|
cg.a_loadaddr_ref_reg(exprasmlist,left.location.reference,hregister2);
|
|
end
|
|
else
|
|
begin
|
|
paramanager.allocparaloc(exprasmlist,paraloc2);
|
|
cg.a_paramaddr_ref(exprasmlist,left.location.reference,paraloc2);
|
|
end;
|
|
secondpass(right);
|
|
if paraloc1.location^.loc=LOC_REGISTER then
|
|
begin
|
|
hregister1:=cg.getaddressregister(exprasmlist);
|
|
cg.a_loadaddr_ref_reg(exprasmlist,right.location.reference,hregister1);
|
|
end
|
|
else
|
|
begin
|
|
paramanager.allocparaloc(exprasmlist,paraloc1);
|
|
cg.a_paramaddr_ref(exprasmlist,right.location.reference,paraloc1);
|
|
end;
|
|
{ push parameters }
|
|
if paraloc1.location^.loc=LOC_REGISTER then
|
|
begin
|
|
paramanager.allocparaloc(exprasmlist,paraloc2);
|
|
cg.a_param_reg(exprasmlist,OS_ADDR,hregister2,paraloc2);
|
|
end;
|
|
if paraloc2.location^.loc=LOC_REGISTER then
|
|
begin
|
|
paramanager.allocparaloc(exprasmlist,paraloc1);
|
|
cg.a_param_reg(exprasmlist,OS_ADDR,hregister1,paraloc1);
|
|
end;
|
|
paramanager.freeparaloc(exprasmlist,paraloc1);
|
|
paramanager.freeparaloc(exprasmlist,paraloc2);
|
|
cg.alloccpuregisters(exprasmlist,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
|
|
cg.a_call_name(exprasmlist,'FPC_SHORTSTR_COMPARE');
|
|
cg.dealloccpuregisters(exprasmlist,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
|
|
location_freetemp(exprasmlist,left.location);
|
|
location_freetemp(exprasmlist,right.location);
|
|
paraloc1.done;
|
|
paraloc2.done;
|
|
end;
|
|
end;
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
location.resflags:=getresflags(true);
|
|
end;
|
|
else
|
|
{ rest should be handled in first pass (JM) }
|
|
internalerror(200108303);
|
|
end;
|
|
end;
|
|
{$endif i386}
|
|
|
|
|
|
{*****************************************************************************
|
|
Add64bit
|
|
*****************************************************************************}
|
|
|
|
procedure tx86addnode.second_add64bit;
|
|
begin
|
|
{$ifdef cpu64bit}
|
|
second_addordinal;
|
|
{$else cpu64bit}
|
|
{ must be implemented separate }
|
|
internalerror(200402042);
|
|
{$endif cpu64bit}
|
|
end;
|
|
|
|
|
|
procedure tx86addnode.second_cmp64bit;
|
|
begin
|
|
{$ifdef cpu64bit}
|
|
second_cmpordinal;
|
|
{$else cpu64bit}
|
|
{ must be implemented separate }
|
|
internalerror(200402043);
|
|
{$endif cpu64bit}
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
AddOrdinal
|
|
*****************************************************************************}
|
|
|
|
procedure tx86addnode.second_addordinal;
|
|
var
|
|
mboverflow : boolean;
|
|
op : tasmop;
|
|
opsize : tcgsize;
|
|
{ true, if unsigned types are compared }
|
|
unsigned : boolean;
|
|
{ true, if for sets subtractions the extra not should generated }
|
|
extra_not : boolean;
|
|
begin
|
|
{ defaults }
|
|
extra_not:=false;
|
|
mboverflow:=false;
|
|
unsigned:=not(is_signed(left.resulttype.def)) or
|
|
not(is_signed(right.resulttype.def));
|
|
opsize:=def_cgsize(left.resulttype.def);
|
|
|
|
pass_left_right;
|
|
|
|
case nodetype of
|
|
addn :
|
|
begin
|
|
op:=A_ADD;
|
|
mboverflow:=true;
|
|
end;
|
|
muln :
|
|
begin
|
|
if unsigned then
|
|
op:=A_MUL
|
|
else
|
|
op:=A_IMUL;
|
|
mboverflow:=true;
|
|
end;
|
|
subn :
|
|
begin
|
|
op:=A_SUB;
|
|
mboverflow:=true;
|
|
end;
|
|
xorn :
|
|
op:=A_XOR;
|
|
orn :
|
|
op:=A_OR;
|
|
andn :
|
|
op:=A_AND;
|
|
else
|
|
internalerror(200304229);
|
|
end;
|
|
|
|
{ filter MUL, which requires special handling }
|
|
if op=A_MUL then
|
|
begin
|
|
second_mul;
|
|
exit;
|
|
end;
|
|
|
|
left_must_be_reg(opsize,false);
|
|
emit_generic_code(op,opsize,unsigned,extra_not,mboverflow);
|
|
location_freetemp(exprasmlist,right.location);
|
|
|
|
set_result_location_reg;
|
|
end;
|
|
|
|
|
|
procedure tx86addnode.second_cmpordinal;
|
|
var
|
|
opsize : tcgsize;
|
|
unsigned : boolean;
|
|
begin
|
|
unsigned:=not(is_signed(left.resulttype.def)) or
|
|
not(is_signed(right.resulttype.def));
|
|
opsize:=def_cgsize(left.resulttype.def);
|
|
|
|
pass_left_right;
|
|
|
|
left_must_be_reg(opsize,false);
|
|
emit_generic_code(A_CMP,opsize,unsigned,false,false);
|
|
location_freetemp(exprasmlist,right.location);
|
|
location_freetemp(exprasmlist,left.location);
|
|
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
location.resflags:=getresflags(unsigned);
|
|
end;
|
|
|
|
begin
|
|
caddnode:=tx86addnode;
|
|
end.
|
|
{
|
|
$Log$
|
|
Revision 1.13 2004-09-25 14:23:55 peter
|
|
* ungetregister is now only used for cpuregisters, renamed to
|
|
ungetcpuregister
|
|
* renamed (get|unget)explicitregister(s) to ..cpuregister
|
|
* removed location-release/reference_release
|
|
|
|
Revision 1.12 2004/09/21 17:25:13 peter
|
|
* paraloc branch merged
|
|
|
|
Revision 1.11.4.1 2004/08/31 20:43:06 peter
|
|
* paraloc patch
|
|
|
|
Revision 1.11 2004/06/20 08:55:32 florian
|
|
* logs truncated
|
|
|
|
Revision 1.10 2004/06/16 20:07:11 florian
|
|
* dwarf branch merged
|
|
|
|
Revision 1.9.2.4 2004/05/02 16:46:28 peter
|
|
* disable i386 optimized shortstr_compare for x86_64
|
|
|
|
Revision 1.9.2.3 2004/04/28 18:35:42 peter
|
|
* cardinal fixes for x86-64
|
|
|
|
Revision 1.9.2.2 2004/04/27 18:18:26 peter
|
|
* aword -> aint
|
|
|
|
Revision 1.9.2.1 2004/04/26 15:54:33 peter
|
|
* small x86-64 fixes
|
|
|
|
}
|