fpc/compiler/riscv64
florian 69786ffe73 somehow committing went wrong, second part of last commit:
+ AArch64: support for vX.8b/vX.16b register names
+ support for more than 256 registers in the register dat files
- removed totherregisterset
+ AArch64: use vmov to load immediates if possible
+ AArch64: use eor to clear mm registers

git-svn-id: trunk@42917 -
2019-09-03 21:07:33 +00:00
..
aoptcpu.pas * fix case completeness and unreachable code warnings in compiler that would 2019-05-12 14:29:03 +00:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas * fix case completeness and unreachable code warnings in compiler that would 2019-05-12 14:29:03 +00:00
cpubase.pas somehow committing went wrong, second part of last commit: 2019-09-03 21:07:33 +00:00
cpuinfo.pas - Fix bug in 64bit softfloat double negation. 2019-07-07 11:32:27 +00:00
cpunode.pas
cpupara.pas * fix case completeness and unreachable code warnings in compiler that would 2019-05-12 14:29:03 +00:00
cpupi.pas * fix case completeness and unreachable code warnings in compiler that would 2019-05-12 14:29:03 +00:00
cputarg.pas
hlcgcpu.pas
itcpugas.pas
nrv64add.pas
nrv64cal.pas
nrv64cnv.pas
nrv64ld.pas
nrv64mat.pas
rarv64gas.pas * fix case completeness and unreachable code warnings in compiler that would 2019-05-12 14:29:03 +00:00
rarv.pas
rrv32con.inc
rrv32dwa.inc
rrv32nor.inc
rrv32num.inc
rrv32rni.inc
rrv32sri.inc
rrv32sta.inc
rrv32std.inc
rrv32sup.inc
rv32reg.dat
symcpu.pas